From 2234f50223d4610ad21e3476c224ec97e957f142 Mon Sep 17 00:00:00 2001 From: Sebastien Bourdeauducq Date: Mon, 1 Sep 2014 19:54:39 +0800 Subject: [PATCH] k7ddrphy: add bitslip control for incoming DQ --- misoclib/sdramphy/k7ddrphy.py | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/misoclib/sdramphy/k7ddrphy.py b/misoclib/sdramphy/k7ddrphy.py index 410cd8661..f6012940b 100644 --- a/misoclib/sdramphy/k7ddrphy.py +++ b/misoclib/sdramphy/k7ddrphy.py @@ -18,6 +18,7 @@ class K7DDRPHY(Module, AutoCSR): self._r_dly_sel = CSRStorage(d//8) self._r_rdly_dq_rst = CSR() self._r_rdly_dq_inc = CSR() + self._r_rdly_dq_bitslip = CSR() self._r_wdly_dq_rst = CSR() self._r_wdly_dq_inc = CSR() self._r_wdly_dqs_rst = CSR() @@ -225,9 +226,9 @@ class K7DDRPHY(Module, AutoCSR): i_DDLY=dq_i_delayed, i_CE1=1, - i_RST=ResetSignal(), + i_RST=ResetSignal() | (self._r_dly_sel.storage[i//8] & self._r_wdly_dq_rst.re), i_CLK=ClockSignal("sys4x"), i_CLKB=~ClockSignal("sys4x"), i_CLKDIV=ClockSignal(), - i_BITSLIP=0, + i_BITSLIP=self._r_dly_sel.storage[i//8] & self._r_rdly_dq_bitslip.re, o_Q8=self.dfi.phases[0].rddata[i], o_Q7=self.dfi.phases[0].rddata[d+i], o_Q6=self.dfi.phases[1].rddata[i], o_Q5=self.dfi.phases[1].rddata[d+i], o_Q4=self.dfi.phases[2].rddata[i], o_Q3=self.dfi.phases[2].rddata[d+i],