From 22afa34a64532726bac27e5542d3e481e9ecfc96 Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Wed, 21 Aug 2024 11:17:55 +0200 Subject: [PATCH] soc/cores/hyperbus: WiP to make increase similarities between x1/x2 versions. --- litex/soc/cores/hyperbus.py | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/litex/soc/cores/hyperbus.py b/litex/soc/cores/hyperbus.py index 8277caf89..bf0cd318c 100644 --- a/litex/soc/cores/hyperbus.py +++ b/litex/soc/cores/hyperbus.py @@ -116,7 +116,7 @@ class HyperRAM(LiteXModule): # CSn. pads.cs_n.reset = 2**len(pads.cs_n) - 1 - self.sync.sys += pads.cs_n[0].eq(~cs) # Only supporting 1 CS. + self.sync += pads.cs_n[0].eq(~cs) # Only supporting 1 CS. # Clk. pads_clk = Signal() @@ -145,9 +145,9 @@ class HyperRAM(LiteXModule): ] cases = { 0b00 : clk.eq(0), # 0° - 0b01 : clk.eq(cs), # 90° + 0b01 : clk.eq(cs), # 90° / Set Clk. 0b10 : clk.eq(cs), # 180° - 0b11 : clk.eq(0), # 270° + 0b11 : clk.eq(0), # 270° / Clr Clk. } self.sync.sys_2x += Case(clk_phase, cases)