diff --git a/litex/boards/platforms/arty.py b/litex/boards/platforms/arty.py index 1e2d8743e..712cd9aba 100644 --- a/litex/boards/platforms/arty.py +++ b/litex/boards/platforms/arty.py @@ -3,7 +3,8 @@ # License: BSD from litex.build.generic_platform import * -from litex.build.xilinx import XilinxPlatform, VivadoProgrammer +from litex.build.xilinx import XilinxPlatform +from litex.build.openocd import OpenOCD # IOs ---------------------------------------------------------------------------------------------- @@ -257,4 +258,9 @@ class Platform(XilinxPlatform): self.add_platform_command("set_property INTERNAL_VREF 0.675 [get_iobanks 34]") def create_programmer(self): - return VivadoProgrammer(flash_part="n25q128-3.3v-spi-x1_x2_x4") + bscan_spi = "bscan_spi_xc7a100t.bit" if "xc7a100t" in self.device else "bscan_spi_xc7a35t.bit" + return OpenOCD("openocd_xilinx_xc7.cfg", bscan_spi) + + def do_finalize(self, fragment): + XilinxPlatform.do_finalize(self, fragment) + self.add_period_constraint(self.lookup_request("clk100", loose=True), 1e9/100e6) diff --git a/litex/boards/platforms/avalanche.py b/litex/boards/platforms/avalanche.py index 5de18cde7..ac5f568b3 100644 --- a/litex/boards/platforms/avalanche.py +++ b/litex/boards/platforms/avalanche.py @@ -92,3 +92,8 @@ class Platform(MicrosemiPlatform): def __init__(self): MicrosemiPlatform.__init__(self, "MPF300TS_ES-FCG484-1", _io) + + def do_finalize(self, fragment): + MicrosemiPlatform.do_finalize(self, fragment) + self.add_period_constraint(self.lookup_request("clk50", 0, loose=True), 1e9/50e6) + self.add_period_constraint(self.lookup_request("clk50", 1, loose=True), 1e9/50e6) diff --git a/litex/boards/platforms/de0nano.py b/litex/boards/platforms/de0nano.py index 042a543e5..819a47eb3 100644 --- a/litex/boards/platforms/de0nano.py +++ b/litex/boards/platforms/de0nano.py @@ -114,3 +114,7 @@ class Platform(AlteraPlatform): def create_programmer(self): return USBBlaster() + + def do_finalize(self, fragment): + AlteraPlatform.do_finalize(self, fragment) + self.add_period_constraint(self.lookup_request("clk50", loose=True), 1e9/50e6) diff --git a/litex/boards/platforms/genesys2.py b/litex/boards/platforms/genesys2.py index 523aa92b9..7e5ebc43c 100644 --- a/litex/boards/platforms/genesys2.py +++ b/litex/boards/platforms/genesys2.py @@ -3,6 +3,7 @@ from litex.build.generic_platform import * from litex.build.xilinx import XilinxPlatform, VivadoProgrammer +from litex.build.openocd import OpenOCD # IOs ---------------------------------------------------------------------------------------------- @@ -116,11 +117,9 @@ class Platform(XilinxPlatform): XilinxPlatform.__init__(self, "xc7k325t-ffg900-2", _io, _connectors, toolchain="vivado") def create_programmer(self): - return VivadoProgrammer() + return OpenOCD("openocd_xilinx_xc7.cfg", "bscan_spi_xc7a325t.bit") def do_finalize(self, fragment): XilinxPlatform.do_finalize(self, fragment) - try: - self.add_period_constraint(self.lookup_request("eth_clocks").rx, 1e9/125e6) - except ConstraintError: - pass + self.add_period_constraint(self.lookup_request("clk200", loose=True), 1e9/200e6) + self.add_period_constraint(self.lookup_request("eth_clocks:rx", loose=True), 1e9/125e6) diff --git a/litex/boards/platforms/icebreaker.py b/litex/boards/platforms/icebreaker.py index a46651ef3..1525ba6be 100644 --- a/litex/boards/platforms/icebreaker.py +++ b/litex/boards/platforms/icebreaker.py @@ -86,3 +86,7 @@ class Platform(LatticePlatform): def create_programmer(self): return IceStormProgrammer() + + def do_finalize(self, fragment): + LatticePlatform.do_finalize(self, fragment) + self.add_period_constraint(self.lookup_request("clk12", loose=True), 1e9/12e6) diff --git a/litex/boards/platforms/kc705.py b/litex/boards/platforms/kc705.py index d1f02a505..394e58675 100644 --- a/litex/boards/platforms/kc705.py +++ b/litex/boards/platforms/kc705.py @@ -3,7 +3,8 @@ # This file is Copyright (c) 2015 Yann Sionneau from litex.build.generic_platform import * -from litex.build.xilinx import XilinxPlatform, VivadoProgrammer +from litex.build.xilinx import XilinxPlatform +from litex.build.openocd import OpenOCD # IOs ---------------------------------------------------------------------------------------------- @@ -548,20 +549,11 @@ set_property CONFIG_VOLTAGE 2.5 [current_design] self.toolchain.additional_commands = ["write_cfgmem -force -format bin -interface spix4 -size 16 -loadbit \"up 0x0 {build_name}.bit\" -file {build_name}.bin"] def create_programmer(self): - return VivadoProgrammer() + return OpenOCD("openocd_xilinx_xc7.cfg", "bscan_spi_xc7a325t.bit") def do_finalize(self, fragment): XilinxPlatform.do_finalize(self, fragment) - try: - self.add_period_constraint(self.lookup_request("clk200").p, 1e9/200e6) - except ConstraintError: - pass - try: - self.add_period_constraint(self.lookup_request("eth_clocks").rx, 1e9/125e6) - except ConstraintError: - pass - try: - self.add_period_constraint(self.lookup_request("eth_clocks").tx, 1e9/125e6) - except ConstraintError: - pass + self.add_period_constraint(self.lookup_request("clk200", loose=True), 1e9/200e6) + self.add_period_constraint(self.lookup_request("eth_clocks:rx", loose=True), 1e9/125e6) + self.add_period_constraint(self.lookup_request("eth_clocks:tx", loose=True), 1e9/125e6) self.add_platform_command("set_property DCI_CASCADE {{32 34}} [get_iobanks 33]") diff --git a/litex/boards/platforms/kcu105.py b/litex/boards/platforms/kcu105.py index 038df0fbc..1230011de 100644 --- a/litex/boards/platforms/kcu105.py +++ b/litex/boards/platforms/kcu105.py @@ -498,6 +498,8 @@ class Platform(XilinxPlatform): def do_finalize(self, fragment): XilinxPlatform.do_finalize(self, fragment) + self.add_period_constraint(self.lookup_request("clk125", loose=True), 1e9/125e6) + self.add_period_constraint(self.lookup_request("clk300", loose=True), 1e9/300e6) self.add_platform_command("set_property INTERNAL_VREF 0.84 [get_iobanks 44]") self.add_platform_command("set_property INTERNAL_VREF 0.84 [get_iobanks 45]") self.add_platform_command("set_property INTERNAL_VREF 0.84 [get_iobanks 46]") diff --git a/litex/boards/platforms/machxo3.py b/litex/boards/platforms/machxo3.py index ebf72d6a1..d47242f41 100644 --- a/litex/boards/platforms/machxo3.py +++ b/litex/boards/platforms/machxo3.py @@ -92,3 +92,7 @@ class Platform(LatticePlatform): """ return LatticeProgrammer(_xcf_template) + + def do_finalize(self, fragment): + LatticePlatform.do_finalize(self, fragment) + self.add_period_constraint(self.lookup_request("clk12", loose=True), 1e9/12e6) diff --git a/litex/boards/platforms/minispartan6.py b/litex/boards/platforms/minispartan6.py index 046ee16b3..0ad7e0799 100644 --- a/litex/boards/platforms/minispartan6.py +++ b/litex/boards/platforms/minispartan6.py @@ -3,7 +3,7 @@ from litex.build.generic_platform import * from litex.build.xilinx import XilinxPlatform -from litex.build.xilinx.programmer import FpgaProg +from litex.build.xilinx.programmer import XC3SProg # IOs ---------------------------------------------------------------------------------------------- @@ -136,4 +136,9 @@ class Platform(XilinxPlatform): XilinxPlatform.__init__(self, device+"-3-ftg256", _io, _connectors) def create_programmer(self): - return FpgaProg() + return XC3SProg(cable="ftdi") + + def do_finalize(self, fragment): + XilinxPlatform.do_finalize(self, fragment) + self.add_period_constraint(self.lookup_request("clk32", loose=True), 1e9/32e6) + self.add_period_constraint(self.lookup_request("clk50", loose=True), 1e9/50e6) diff --git a/litex/boards/platforms/netv2.py b/litex/boards/platforms/netv2.py index f3e8abc8e..c201b07f4 100644 --- a/litex/boards/platforms/netv2.py +++ b/litex/boards/platforms/netv2.py @@ -2,7 +2,8 @@ # License: BSD from litex.build.generic_platform import * -from litex.build.xilinx import XilinxPlatform, VivadoProgrammer +from litex.build.xilinx import XilinxPlatform +from litex.build.openocd import OpenOCD # IOs ---------------------------------------------------------------------------------------------- @@ -191,3 +192,12 @@ class Platform(XilinxPlatform): def __init__(self, device="xc7a35t"): assert device in ["xc7a35t", "xc7a100t"] XilinxPlatform.__init__(self, device + "-fgg484-2", _io, toolchain="vivado") + + def create_programmer(self): + bscan_spi = "bscan_spi_xc7a100t.bit" if "xc7a100t" in self.device else "bscan_spi_xc7a35t.bit" + return OpenOCD("openocd_netv2_rpi.cfg", bscan_spi) + + def do_finalize(self, fragment): + XilinxPlatform.do_finalize(self, fragment) + self.add_period_constraint(self.lookup_request("clk50", loose=True), 1e9/50e6) + self.add_period_constraint(self.lookup_request("eth_clocks", loose=True), 1e9/50e6) diff --git a/litex/boards/platforms/nexys4ddr.py b/litex/boards/platforms/nexys4ddr.py index b52ca6491..e112ca621 100644 --- a/litex/boards/platforms/nexys4ddr.py +++ b/litex/boards/platforms/nexys4ddr.py @@ -3,6 +3,7 @@ from litex.build.generic_platform import * from litex.build.xilinx import XilinxPlatform, VivadoProgrammer +from litex.build.openocd import OpenOCD # IOs ---------------------------------------------------------------------------------------------- @@ -131,4 +132,9 @@ class Platform(XilinxPlatform): self.add_platform_command("set_property INTERNAL_VREF 0.750 [get_iobanks 34]") def create_programmer(self): - return VivadoProgrammer() + return OpenOCD("openocd_xilinx_xc7.cfg", "bscan_spi_xc7a100t.bit") + + def do_finalize(self, fragment): + XilinxPlatform.do_finalize(self, fragment) + self.add_period_constraint(self.lookup_request("clk100", loose=True), 1e9/100e6) + self.add_period_constraint(self.lookup_request("eth_clocks:ref_clk", loose=True), 1e9/50e6) diff --git a/litex/boards/platforms/nexys_video.py b/litex/boards/platforms/nexys_video.py index dad949b8f..e4a58ac82 100644 --- a/litex/boards/platforms/nexys_video.py +++ b/litex/boards/platforms/nexys_video.py @@ -3,6 +3,7 @@ from litex.build.generic_platform import * from litex.build.xilinx import XilinxPlatform, VivadoProgrammer +from litex.build.openocd import OpenOCD # IOs ---------------------------------------------------------------------------------------------- @@ -230,9 +231,8 @@ class Platform(XilinxPlatform): "-loadbit \"up 0x0 {build_name}.bit\" -file {build_name}.bin"] self.add_platform_command("set_property INTERNAL_VREF 0.750 [get_iobanks 35]") - def create_programmer(self): - return VivadoProgrammer(flash_part="n25q128-3.3v-spi-x1_x2_x4") + return OpenOCD("openocd_xilinx_xc7.cfg", "bscan_spi_xc7a200t.bit") def do_finalize(self, fragment): XilinxPlatform.do_finalize(self, fragment) @@ -240,3 +240,8 @@ class Platform(XilinxPlatform): self.add_period_constraint(self.lookup_request("eth_clocks").rx, 1e9/125e6) except ConstraintError: pass + + def do_finalize(self, fragment): + XilinxPlatform.do_finalize(self, fragment) + self.add_period_constraint(self.lookup_request("clk100", loose=True), 1e9/100e6) + self.add_period_constraint(self.lookup_request("eth_clocks", loose=True), 1e9/125e6) diff --git a/litex/boards/platforms/tinyfpga_bx.py b/litex/boards/platforms/tinyfpga_bx.py index 4cfe96382..a1bfd5e52 100644 --- a/litex/boards/platforms/tinyfpga_bx.py +++ b/litex/boards/platforms/tinyfpga_bx.py @@ -67,3 +67,7 @@ class Platform(LatticePlatform): def create_programmer(self): return TinyProgProgrammer() + + def do_finalize(self, fragment): + LatticePlatform.do_finalize(self, fragment) + self.add_period_constraint(self.lookup_request("clk16", loose=True), 1e9/16e6) diff --git a/litex/boards/platforms/ulx3s.py b/litex/boards/platforms/ulx3s.py index 20640fc38..f2859cba0 100644 --- a/litex/boards/platforms/ulx3s.py +++ b/litex/boards/platforms/ulx3s.py @@ -3,6 +3,7 @@ from litex.build.generic_platform import * from litex.build.lattice import LatticePlatform +from litex.build.lattice.programmer import UJProg # IOs ---------------------------------------------------------------------------------------------- @@ -84,6 +85,13 @@ _io = [ Subsignal("n", Pins("C10")), IOStandard("LVCMOS33") ), + + ("usb", 0, + Subsignal("d_p", Pins("D15")), + Subsignal("d_n", Pins("E15")), + Subsignal("pullup", Pins("B12 C12")), + IOStandard("LVCMOS33") + ), ] # Platform ----------------------------------------------------------------------------------------- @@ -94,3 +102,10 @@ class Platform(LatticePlatform): def __init__(self, device="LFE5U-45F", **kwargs): LatticePlatform.__init__(self, device + "-6BG381C", _io, **kwargs) + + def create_programmer(self): + return UJProg() + + def do_finalize(self, fragment): + LatticePlatform.do_finalize(self, fragment) + self.add_period_constraint(self.lookup_request("clk25", loose=True), 1e9/25e6) diff --git a/litex/boards/platforms/versa_ecp5.py b/litex/boards/platforms/versa_ecp5.py index e3b40b418..4ea3df466 100644 --- a/litex/boards/platforms/versa_ecp5.py +++ b/litex/boards/platforms/versa_ecp5.py @@ -4,7 +4,7 @@ from litex.build.generic_platform import * from litex.build.lattice import LatticePlatform -from litex.build.lattice.programmer import LatticeProgrammer +from litex.build.lattice.programmer import OpenOCDJTAGProgrammer # IOs ---------------------------------------------------------------------------------------------- @@ -224,12 +224,10 @@ class Platform(LatticePlatform): def __init__(self, **kwargs): LatticePlatform.__init__(self, "LFE5UM5G-45F-8BG381C", _io, _connectors, **kwargs) + def create_programmer(self): + return OpenOCDJTAGProgrammer("openocd_versa_ecp5.cfg") + def do_finalize(self, fragment): - try: - self.add_period_constraint(self.lookup_request("eth_clocks", 0).rx, 1e9/125e6) - except ConstraintError: - pass - try: - self.add_period_constraint(self.lookup_request("eth_clocks", 1).rx, 1e9/125e6) - except ConstraintError: - pass + self.add_period_constraint(self.lookup_request("clk100", loose=True), 1e9/100e6) + self.add_period_constraint(self.lookup_request("eth_clocks:rx", 0, loose=True), 1e9/125e6) + self.add_period_constraint(self.lookup_request("eth_clocks:rx", 1, loose=True), 1e9/125e6) diff --git a/litex/boards/targets/arty.py b/litex/boards/targets/arty.py index 8f3368389..29e33bc3e 100755 --- a/litex/boards/targets/arty.py +++ b/litex/boards/targets/arty.py @@ -3,6 +3,7 @@ # This file is Copyright (c) 2015-2019 Florent Kermarrec # License: BSD +import os import argparse from migen import * @@ -96,20 +97,25 @@ class BaseSoC(SoCCore): # Build -------------------------------------------------------------------------------------------- def main(): - parser = argparse.ArgumentParser(description="LiteX SoC on Arty") + parser = argparse.ArgumentParser(description="LiteX SoC on Arty A7") + parser.add_argument("--build", action="store_true", help="Build bitstream") + parser.add_argument("--load", action="store_true", help="Load bitstream") builder_args(parser) soc_sdram_args(parser) vivado_build_args(parser) - parser.add_argument("--with-ethernet", action="store_true", help="enable Ethernet support") - parser.add_argument("--with-etherbone", action="store_true", help="enable Etherbone support") + parser.add_argument("--with-ethernet", action="store_true", help="Enable Ethernet support") + parser.add_argument("--with-etherbone", action="store_true", help="Enable Etherbone support") args = parser.parse_args() assert not (args.with_ethernet and args.with_etherbone) soc = BaseSoC(with_ethernet=args.with_ethernet, with_etherbone=args.with_etherbone, **soc_sdram_argdict(args)) builder = Builder(soc, **builder_argdict(args)) - builder.build(**vivado_build_argdict(args)) + builder.build(**vivado_build_argdict(args), run=args.build) + if args.load: + prog = soc.platform.create_programmer() + prog.load_bitstream(os.path.join(builder.gateware_dir, "top.bit")) if __name__ == "__main__": main() diff --git a/litex/boards/targets/de0nano.py b/litex/boards/targets/de0nano.py index 5830f35e8..960dc48ec 100755 --- a/litex/boards/targets/de0nano.py +++ b/litex/boards/targets/de0nano.py @@ -3,6 +3,7 @@ # This file is Copyright (c) 2015-2020 Florent Kermarrec # License: BSD +import os import argparse from migen import * @@ -31,7 +32,6 @@ class _CRG(Module): # Clk / Rst clk50 = platform.request("clk50") - platform.add_period_constraint(clk50, 1e9/50e6) # PLL self.submodules.pll = pll = CycloneIVPLL(speedgrade="-6") @@ -71,14 +71,19 @@ class BaseSoC(SoCCore): def main(): parser = argparse.ArgumentParser(description="LiteX SoC on DE0 Nano") + parser.add_argument("--build", action="store_true", help="Build bitstream") + parser.add_argument("--load", action="store_true", help="Load bitstream") builder_args(parser) soc_sdram_args(parser) args = parser.parse_args() soc = BaseSoC(**soc_sdram_argdict(args)) builder = Builder(soc, **builder_argdict(args)) - builder.build() + builder.build(run=args.build) + if args.load: + prog = soc.platform.create_programmer() + prog.load_bitstream(os.path.join(builder.gateware_dir, "top.sof")) if __name__ == "__main__": main() diff --git a/litex/boards/targets/genesys2.py b/litex/boards/targets/genesys2.py index d97b68a36..8557c0c52 100755 --- a/litex/boards/targets/genesys2.py +++ b/litex/boards/targets/genesys2.py @@ -3,6 +3,7 @@ # This file is Copyright (c) 2019 Florent Kermarrec # License: BSD +import os import argparse from migen import * @@ -87,6 +88,8 @@ class BaseSoC(SoCCore): def main(): parser = argparse.ArgumentParser(description="LiteX SoC on Genesys2") + parser.add_argument("--build", action="store_true", help="Build bitstream") + parser.add_argument("--load", action="store_true", help="Load bitstream") builder_args(parser) soc_sdram_args(parser) parser.add_argument("--with-ethernet", action="store_true", help="enable Ethernet support") @@ -97,8 +100,11 @@ def main(): soc = BaseSoC(with_ethernet=args.with_ethernet, with_etherbone=args.with_etherbone, **soc_sdram_argdict(args)) builder = Builder(soc, **builder_argdict(args)) - builder.build() + builder.build(run=args.build) + if args.load: + prog = soc.platform.create_programmer() + prog.load_bitstream(os.path.join(builder.gateware_dir, "top.bit")) if __name__ == "__main__": main() diff --git a/litex/boards/targets/icebreaker.py b/litex/boards/targets/icebreaker.py index 938281798..ae1363b92 100755 --- a/litex/boards/targets/icebreaker.py +++ b/litex/boards/targets/icebreaker.py @@ -14,6 +14,7 @@ # with more features, examples to run C/Rust code on the RISC-V CPU and documentation can be found # at: https://github.com/icebreaker-fpga/icebreaker-litex-examples +import os import argparse from migen import * @@ -115,18 +116,24 @@ def flash(bios_flash_offset): def main(): parser = argparse.ArgumentParser(description="LiteX SoC on iCEBreaker") - parser.add_argument("--bios-flash-offset", default=0x40000, help="BIOS offset in SPI Flash") - parser.add_argument("--flash", action="store_true", help="Load Bitstream") + parser.add_argument("--build", action="store_true", help="Build bitstream") + parser.add_argument("--load", action="store_true", help="Load bitstream") + parser.add_argument("--bios-flash-offset", default=0x40000, help="BIOS offset in SPI Flash") + parser.add_argument("--flash", action="store_true", help="Flash Bitstream") builder_args(parser) soc_core_args(parser) args = parser.parse_args() + soc = BaseSoC(args.bios_flash_offset, **soc_core_argdict(args)) + builder = Builder(soc, **builder_argdict(args)) + builder.build(run=args.build) + + if args.load: + prog = soc.platform.create_programmer() + prog.load_bitstream(os.path.join(builder.gateware_dir, "top.bin")) + if args.flash: flash(args.bios_flash_offset) - soc = BaseSoC(args.bios_flash_offset, **soc_core_argdict(args)) - builder = Builder(soc, **builder_argdict(args)) - builder.build() - if __name__ == "__main__": main() diff --git a/litex/boards/targets/kc705.py b/litex/boards/targets/kc705.py index 87290e477..9bca15823 100755 --- a/litex/boards/targets/kc705.py +++ b/litex/boards/targets/kc705.py @@ -5,6 +5,7 @@ # This file is Copyright (c) 2014-2015 Yann Sionneau # License: BSD +import os import argparse from migen import * @@ -83,16 +84,20 @@ class BaseSoC(SoCCore): def main(): parser = argparse.ArgumentParser(description="LiteX SoC on KC705") + parser.add_argument("--build", action="store_true", help="Build bitstream") + parser.add_argument("--load", action="store_true", help="Load bitstream") builder_args(parser) soc_sdram_args(parser) - parser.add_argument("--with-ethernet", action="store_true", - help="enable Ethernet support") + parser.add_argument("--with-ethernet", action="store_true", help="Enable Ethernet support") args = parser.parse_args() soc = BaseSoC(with_ethernet=args.with_ethernet, **soc_sdram_argdict(args)) builder = Builder(soc, **builder_argdict(args)) - builder.build() + builder.build(run=args.build) + if args.load: + prog = soc.platform.create_programmer() + prog.load_bitstream(os.path.join(builder.gateware_dir, "top.bit")) if __name__ == "__main__": main() diff --git a/litex/boards/targets/kcu105.py b/litex/boards/targets/kcu105.py index b632b16cc..a0c98f862 100755 --- a/litex/boards/targets/kcu105.py +++ b/litex/boards/targets/kcu105.py @@ -3,6 +3,7 @@ # This file is Copyright (c) 2018-2019 Florent Kermarrec # License: BSD +import os import argparse from migen import * @@ -92,16 +93,20 @@ class BaseSoC(SoCCore): def main(): parser = argparse.ArgumentParser(description="LiteX SoC on KCU105") + parser.add_argument("--build", action="store_true", help="Build bitstream") + parser.add_argument("--load", action="store_true", help="Load bitstream") builder_args(parser) soc_sdram_args(parser) - parser.add_argument("--with-ethernet", action="store_true", - help="enable Ethernet support") + parser.add_argument("--with-ethernet", action="store_true", help="Enable Ethernet support") args = parser.parse_args() soc = BaseSoC(with_ethernet=args.with_ethernet, **soc_sdram_argdict(args)) builder = Builder(soc, **builder_argdict(args)) - builder.build() + builder.build(run=args.build) + if args.load: + prog = soc.platform.create_programmer() + prog.load_bitstream(os.path.join(builder.gateware_dir, "top.bit")) if __name__ == "__main__": main() diff --git a/litex/boards/targets/minispartan6.py b/litex/boards/targets/minispartan6.py index 638d28d18..641e11192 100755 --- a/litex/boards/targets/minispartan6.py +++ b/litex/boards/targets/minispartan6.py @@ -5,6 +5,7 @@ # This file is Copyright (c) 2014 Yann Sionneau # License: BSD +import os import argparse from fractions import Fraction @@ -69,14 +70,19 @@ class BaseSoC(SoCCore): def main(): parser = argparse.ArgumentParser(description="LiteX SoC on MiniSpartan6") + parser.add_argument("--build", action="store_true", help="Build bitstream") + parser.add_argument("--load", action="store_true", help="Load bitstream") builder_args(parser) soc_sdram_args(parser) args = parser.parse_args() soc = BaseSoC(**soc_sdram_argdict(args)) builder = Builder(soc, **builder_argdict(args)) - builder.build() + builder.build(run=args.build) + if args.load: + prog = soc.platform.create_programmer() + prog.load_bitstream(os.path.join(builder.gateware_dir, "top.bit")) if __name__ == "__main__": main() diff --git a/litex/boards/targets/netv2.py b/litex/boards/targets/netv2.py index cb4270489..7535bc3c6 100755 --- a/litex/boards/targets/netv2.py +++ b/litex/boards/targets/netv2.py @@ -3,6 +3,7 @@ # This file is Copyright (c) 2018-2019 Florent Kermarrec # License: BSD +import os import argparse from migen import * @@ -95,18 +96,21 @@ class BaseSoC(SoCCore): def main(): parser = argparse.ArgumentParser(description="LiteX SoC on NeTV2") + parser.add_argument("--build", action="store_true", help="Build bitstream") + parser.add_argument("--load", action="store_true", help="Load bitstream") builder_args(parser) soc_sdram_args(parser) - parser.add_argument("--with-ethernet", action="store_true", - help="enable Ethernet support") - parser.add_argument("--with-spi-xip", action="store_true", - help="enable SPI XIP support") + parser.add_argument("--with-ethernet", action="store_true", help="Enable Ethernet support") + parser.add_argument("--with-spi-xip", action="store_true", help="Enable SPI XIP support") args = parser.parse_args() soc = BaseSoC(with_ethernet=args.with_ethernet, with_spi_xip=args.with_spi_xip, **soc_sdram_argdict(args)) builder = Builder(soc, **builder_argdict(args)) - builder.build() + builder.build(run=args.build) + if args.load: + prog = soc.platform.create_programmer() + prog.load_bitstream(os.path.join(builder.gateware_dir, "top.bit")) if __name__ == "__main__": main() diff --git a/litex/boards/targets/nexys4ddr.py b/litex/boards/targets/nexys4ddr.py index a4b617df8..e608963fb 100755 --- a/litex/boards/targets/nexys4ddr.py +++ b/litex/boards/targets/nexys4ddr.py @@ -3,6 +3,7 @@ # This file is Copyright (c) 2018-2019 Florent Kermarrec # License: BSD +import os import argparse from migen import * @@ -117,16 +118,14 @@ class BaseSoC(SoCCore): def main(): parser = argparse.ArgumentParser(description="LiteX SoC on Nexys4DDR") + parser.add_argument("--build", action="store_true", help="Build bitstream") + parser.add_argument("--load", action="store_true", help="Load bitstream") builder_args(parser) soc_sdram_args(parser) - parser.add_argument("--sys-clk-freq", default=75e6, - help="system clock frequency (default=75MHz)") - parser.add_argument("--with-ethernet", action="store_true", - help="enable Ethernet support") - parser.add_argument("--with-spi-sdcard", action="store_true", - help="enable SPI-mode SDCard support") - parser.add_argument("--with-sdcard", action="store_true", - help="enable SDCard support") + parser.add_argument("--sys-clk-freq", default=75e6, help="System clock frequency (default=75MHz)") + parser.add_argument("--with-ethernet", action="store_true", help="Enable Ethernet support") + parser.add_argument("--with-spi-sdcard", action="store_true", help="enable SPI-mode SDCard support") + parser.add_argument("--with-sdcard", action="store_true", help="enable SDCard support") args = parser.parse_args() soc = BaseSoC(sys_clk_freq=int(float(args.sys_clk_freq)), @@ -139,8 +138,11 @@ def main(): raise ValueError("'--with-spi-sdcard' and '--with-sdcard' are mutually exclusive!") soc.add_sdcard() builder = Builder(soc, **builder_argdict(args)) - builder.build() + builder.build(run=args.build) + if args.load: + prog = soc.platform.create_programmer() + prog.load_bitstream(os.path.join(builder.gateware_dir, "top.bit")) if __name__ == "__main__": main() diff --git a/litex/boards/targets/nexys_video.py b/litex/boards/targets/nexys_video.py index 677a20f05..f53a0bfa0 100755 --- a/litex/boards/targets/nexys_video.py +++ b/litex/boards/targets/nexys_video.py @@ -3,6 +3,7 @@ # This file is Copyright (c) 2015-2019 Florent Kermarrec # License: BSD +import os import argparse from migen import * @@ -83,16 +84,20 @@ class BaseSoC(SoCCore): def main(): parser = argparse.ArgumentParser(description="LiteX SoC on Nexys Video") + parser.add_argument("--build", action="store_true", help="Build bitstream") + parser.add_argument("--load", action="store_true", help="Load bitstream") builder_args(parser) soc_sdram_args(parser) - parser.add_argument("--with-ethernet", action="store_true", - help="enable Ethernet support") + parser.add_argument("--with-ethernet", action="store_true", help="Enable Ethernet support") args = parser.parse_args() soc = BaseSoC(with_ethernet=args.with_ethernet, **soc_sdram_argdict(args)) builder = Builder(soc, **builder_argdict(args)) - builder.build() + builder.build(run=args.build) + if args.load: + prog = soc.platform.create_programmer() + prog.load_bitstream(os.path.join(builder.gateware_dir, "top.bit")) if __name__ == "__main__": main() diff --git a/litex/boards/targets/simple.py b/litex/boards/targets/simple.py index b208544fb..70872bb0c 100755 --- a/litex/boards/targets/simple.py +++ b/litex/boards/targets/simple.py @@ -4,6 +4,7 @@ # This file is Copyright (c) 2013-2014 Sebastien Bourdeauducq # License: BSD +import os import argparse import importlib @@ -41,14 +42,12 @@ class BaseSoC(SoCCore): def main(): parser = argparse.ArgumentParser(description="Generic LiteX SoC") + parser.add_argument("--build", action="store_true", help="Build bitstream") builder_args(parser) soc_core_args(parser) - parser.add_argument("--with-ethernet", action="store_true", - help="enable Ethernet support") - parser.add_argument("platform", - help="module name of the platform to build for") - parser.add_argument("--gateware-toolchain", default=None, - help="FPGA gateware toolchain used for build") + parser.add_argument("--with-ethernet", action="store_true", help="Enable Ethernet support") + parser.add_argument("platform", help="Module name of the platform to build for") + parser.add_argument("--gateware-toolchain", default=None, help="FPGA gateware toolchain used for build") args = parser.parse_args() platform_module = importlib.import_module(args.platform) @@ -58,7 +57,7 @@ def main(): platform = platform_module.Platform() soc = BaseSoC(platform, with_ethernet=args.with_ethernet, **soc_core_argdict(args)) builder = Builder(soc, **builder_argdict(args)) - builder.build() + builder.build(run=args.build) if __name__ == "__main__": diff --git a/litex/boards/targets/ulx3s.py b/litex/boards/targets/ulx3s.py index a7668e3a9..9802266ca 100755 --- a/litex/boards/targets/ulx3s.py +++ b/litex/boards/targets/ulx3s.py @@ -4,6 +4,7 @@ # This file is Copyright (c) 2018 David Shah # License: BSD +import os import argparse import sys @@ -27,7 +28,7 @@ from litedram.phy import GENSDRPHY # CRG ---------------------------------------------------------------------------------------------- class _CRG(Module): - def __init__(self, platform, sys_clk_freq): + def __init__(self, platform, sys_clk_freq, with_usb_pll=False): self.clock_domains.cd_sys = ClockDomain() self.clock_domains.cd_sys_ps = ClockDomain(reset_less=True) @@ -36,7 +37,6 @@ class _CRG(Module): # Clk / Rst clk25 = platform.request("clk25") rst = platform.request("rst") - platform.add_period_constraint(clk25, 1e9/25e6) # PLL self.submodules.pll = pll = ECP5PLL() @@ -46,6 +46,15 @@ class _CRG(Module): pll.create_clkout(self.cd_sys_ps, sys_clk_freq, phase=90) self.specials += AsyncResetSynchronizer(self.cd_sys, ~pll.locked | rst) + # USB PLL + if with_usb_pll: + self.submodules.usb_pll = usb_pll = ECP5PLL() + usb_pll.register_clkin(clk25, 25e6) + self.clock_domains.cd_usb_12 = ClockDomain() + self.clock_domains.cd_usb_48 = ClockDomain() + usb_pll.create_clkout(self.cd_usb_12, 12e6, margin=0) + usb_pll.create_clkout(self.cd_usb_48, 48e6, margin=0) + # SDRAM clock self.specials += DDROutput(1, 0, platform.request("sdram_clock"), ClockSignal("sys_ps")) @@ -64,7 +73,8 @@ class BaseSoC(SoCCore): SoCCore.__init__(self, platform, clk_freq=sys_clk_freq, **kwargs) # CRG -------------------------------------------------------------------------------------- - self.submodules.crg = _CRG(platform, sys_clk_freq) + with_usb_pll = kwargs.get("uart_name", None) == "usb_acm" + self.submodules.crg = _CRG(platform, sys_clk_freq, with_usb_pll) # SDR SDRAM -------------------------------------------------------------------------------- if not self.integrated_main_ram_size: @@ -83,14 +93,12 @@ class BaseSoC(SoCCore): def main(): parser = argparse.ArgumentParser(description="LiteX SoC on ULX3S") - parser.add_argument("--gateware-toolchain", dest="toolchain", default="trellis", - help="gateware toolchain to use, trellis (default) or diamond") - parser.add_argument("--device", dest="device", default="LFE5U-45F", - help="FPGA device, ULX3S can be populated with LFE5U-12F, LFE5U-25F, LFE5U-45F (default) or LFE5U-85F") - parser.add_argument("--sys-clk-freq", default=50e6, - help="system clock frequency (default=50MHz)") - parser.add_argument("--sdram-module", default="MT48LC16M16", - help="SDRAM module: MT48LC16M16, AS4C32M16 or AS4C16M16 (default=MT48LC16M16)") + parser.add_argument("--build", action="store_true", help="Build bitstream") + parser.add_argument("--load", action="store_true", help="Load bitstream") + parser.add_argument("--gateware-toolchain", dest="toolchain", default="trellis", help="Gateware toolchain to use, trellis (default) or diamond") + parser.add_argument("--device", dest="device", default="LFE5U-45F", help="FPGA device, ULX3S can be populated with LFE5U-45F (default) or LFE5U-85F") + parser.add_argument("--sys-clk-freq", default=50e6, help="System clock frequency (default=50MHz)") + parser.add_argument("--sdram-module", default="MT48LC16M16", help="SDRAM module: MT48LC16M16, AS4C32M16 or AS4C16M16 (default=MT48LC16M16)") builder_args(parser) soc_sdram_args(parser) trellis_args(parser) @@ -102,7 +110,11 @@ def main(): **soc_sdram_argdict(args)) builder = Builder(soc, **builder_argdict(args)) builder_kargs = trellis_argdict(args) if args.toolchain == "trellis" else {} - builder.build(**builder_kargs) + builder.build(**builder_kargs, run=args.build) + + if args.load: + prog = soc.platform.create_programmer() + prog.load_bitstream(os.path.join(builder.gateware_dir, "top.svf")) if __name__ == "__main__": main() diff --git a/litex/boards/targets/versa_ecp5.py b/litex/boards/targets/versa_ecp5.py index 49d8a6517..e390575f5 100755 --- a/litex/boards/targets/versa_ecp5.py +++ b/litex/boards/targets/versa_ecp5.py @@ -4,6 +4,7 @@ # This file is Copyright (c) 2018-2019 David Shah # License: BSD +import os import argparse from migen import * @@ -40,7 +41,6 @@ class _CRG(Module): # Clk / Rst clk100 = platform.request("clk100") rst_n = platform.request("rst_n") - platform.add_period_constraint(clk100, 1e9/100e6) # Power on reset por_count = Signal(16, reset=2**16-1) @@ -110,21 +110,24 @@ class BaseSoC(SoCCore): def main(): parser = argparse.ArgumentParser(description="LiteX SoC on Versa ECP5") - parser.add_argument("--gateware-toolchain", dest="toolchain", default="trellis", - help="gateware toolchain to use, trellis (default) or diamond") + parser.add_argument("--build", action="store_true", help="Build bitstream") + parser.add_argument("--load", action="store_true", help="Load bitstream") + parser.add_argument("--gateware-toolchain", dest="toolchain", default="trellis", help="Gateware toolchain to use, trellis (default) or diamond") builder_args(parser) soc_sdram_args(parser) trellis_args(parser) - parser.add_argument("--sys-clk-freq", default=75e6, - help="system clock frequency (default=75MHz)") - parser.add_argument("--with-ethernet", action="store_true", - help="enable Ethernet support") + parser.add_argument("--sys-clk-freq", default=75e6, help="System clock frequency (default=75MHz)") + parser.add_argument("--with-ethernet", action="store_true", help="Enable Ethernet support") args = parser.parse_args() soc = BaseSoC(sys_clk_freq=int(float(args.sys_clk_freq)), with_ethernet=args.with_ethernet, toolchain=args.toolchain, **soc_sdram_argdict(args)) builder = Builder(soc, **builder_argdict(args)) builder_kargs = trellis_argdict(args) if args.toolchain == "trellis" else {} - builder.build(**builder_kargs) + builder.build(**builder_kargs, run=args.build) + + if args.load: + prog = soc.platform.create_programmer() + prog.load_bitstream(os.path.join(builder.gateware_dir, "top.svf")) if __name__ == "__main__": main()