diff --git a/litex/tools/litex_sim.py b/litex/tools/litex_sim.py
index a819edeb2..196c3f0fd 100755
--- a/litex/tools/litex_sim.py
+++ b/litex/tools/litex_sim.py
@@ -223,13 +223,10 @@ class SimSoC(SoCCore):
                 self.add_constant("MEMTEST_DATA_SIZE", 8*1024)
                 self.add_constant("MEMTEST_ADDR_SIZE", 8*1024)
 
-        #assert not (with_ethernet and with_etherbone)
-
         if with_ethernet and with_etherbone:
             etherbone_ip_address = convert_ip(etherbone_ip_address)
             # Ethernet PHY
             self.submodules.ethphy = LiteEthPHYModel(self.platform.request("eth", 0))
-            self.add_csr("ethphy")
             # Ethernet MAC
             self.submodules.ethmac = LiteEthMAC(phy=self.ethphy, dw=8,
                 interface  = "hybrid",
@@ -239,7 +236,6 @@ class SimSoC(SoCCore):
             # SoftCPU
             self.add_memory_region("ethmac", self.mem_map["ethmac"], 0x2000, type="io")
             self.add_wb_slave(self.mem_regions["ethmac"].origin, self.ethmac.bus, 0x2000)
-            self.add_csr("ethmac")
             if self.irq.enabled:
                 self.irq.add("ethmac", use_loc_if_exists=True)
             # HW ethernet
@@ -255,7 +251,6 @@ class SimSoC(SoCCore):
         elif with_ethernet:
             # Ethernet PHY
             self.submodules.ethphy = LiteEthPHYModel(self.platform.request("eth", 0))
-            self.add_csr("ethphy")
             # Ethernet MAC
             ethmac = LiteEthMAC(phy=self.ethphy, dw=32,
                 interface  = "wishbone",
@@ -265,7 +260,6 @@ class SimSoC(SoCCore):
             self.submodules.ethmac = ethmac
             self.add_memory_region("ethmac", self.mem_map["ethmac"], 0x2000, type="io")
             self.add_wb_slave(self.mem_regions["ethmac"].origin, self.ethmac.bus, 0x2000)
-            self.add_csr("ethmac")
             if self.irq.enabled:
                 self.irq.add("ethmac", use_loc_if_exists=True)
 
@@ -273,7 +267,6 @@ class SimSoC(SoCCore):
         elif with_etherbone:
             # Ethernet PHY
             self.submodules.ethphy = LiteEthPHYModel(self.platform.request("eth", 0)) # FIXME
-            self.add_csr("ethphy")
             # Ethernet Core
             ethcore = LiteEthUDPIPCore(self.ethphy,
                 mac_address = etherbone_mac_address,
@@ -310,13 +303,11 @@ class SimSoC(SoCCore):
                 depth        = 512,
                 clock_domain = "sys",
                 csr_csv      = "analyzer.csv")
-            self.add_csr("analyzer")
 
         # I2C --------------------------------------------------------------------------------------
         if with_i2c:
             pads = platform.request("i2c", 0)
             self.submodules.i2c = I2CMasterSim(pads)
-            self.add_csr("i2c")
 
         # SDCard -----------------------------------------------------------------------------------
         if with_sdcard: