From 23175190d859e6d8fd7303cc78c43cf0e3b51326 Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Mon, 13 Jan 2020 10:14:38 +0100 Subject: [PATCH] cores/uart: add UARTCrossover --- litex/soc/cores/uart.py | 15 +++++++++++++++ litex/soc/integration/soc_core.py | 2 ++ 2 files changed, 17 insertions(+) diff --git a/litex/soc/cores/uart.py b/litex/soc/cores/uart.py index d9c0ea7ea..a3d7122dd 100644 --- a/litex/soc/cores/uart.py +++ b/litex/soc/cores/uart.py @@ -264,3 +264,18 @@ class UARTMultiplexer(Module): uarts[n].rx.eq(uart.rx) ] self.comb += Case(self.sel, cases) + +# UART Crossover ----------------------------------------------------------------------------------- + +class UARTCrossover(UART): + """ + UART crossover trough Wishbone bridge. + + Creates a fully compatible UART that can be used by the CPU as a regular UART and adds a second + UART, cross-connected to the main one to allow terminal emulation over a Wishbone bridge. + """ + def __init__(self, **kwargs): + assert kwargs.get("phy", None) == None + UART.__init__(self, **kwargs) + self.submodules.xover = UART(tx_fifo_depth=2, rx_fifo_depth=2) + self.comb += self.connect(self.xover) diff --git a/litex/soc/integration/soc_core.py b/litex/soc/integration/soc_core.py index 898ccb31c..6592e1a27 100644 --- a/litex/soc/integration/soc_core.py +++ b/litex/soc/integration/soc_core.py @@ -243,6 +243,8 @@ class SoCCore(Module): self.submodules.uart = uart.UART() if uart_name == "stub": self.comb += uart.sink.ready.eq(1) + elif uart_name == "crossover": + self.submodules.uart = uart.UARTCrossover() else: if uart_name == "jtag_atlantic": from litex.soc.cores.jtag import JTAGAtlantic