From 245bed719559bb93960e910ec0f98ff63288bbad Mon Sep 17 00:00:00 2001 From: Gwenhael Goavec-Merou Date: Thu, 25 Jan 2024 17:39:12 +0100 Subject: [PATCH] soc/cores/clock/efinix: fix input clock code for trion when the input clock comes from another PLL --- litex/soc/cores/clock/efinix.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/litex/soc/cores/clock/efinix.py b/litex/soc/cores/clock/efinix.py index d71197107..63cca6839 100644 --- a/litex/soc/cores/clock/efinix.py +++ b/litex/soc/cores/clock/efinix.py @@ -88,7 +88,7 @@ class EFINIXPLL(LiteXModule): self.logger.info("Clock source: {}, using EXT_CLK{}".format(block["input_clock"], clock_no)) self.platform.get_pll_resource(pll_res) else: - block["input_clock"] = "INTERNAL" + block["input_clock"] = "INTERNAL" if self.type == "TITANIUMPLL" else "CORE" block["resource"] = self.platform.get_free_pll_resource() block["input_signal"] = name self.logger.info("Clock source: {}".format(block["input_clock"]))