From 2470ef50969e950d8166560d1eb47ff68cecb398 Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Wed, 8 Apr 2020 08:33:57 +0200 Subject: [PATCH] soc/cores/clock: add Cyclone10LPPLL. --- litex/soc/cores/clock.py | 28 ++++++++++++++++++++++++++++ 1 file changed, 28 insertions(+) diff --git a/litex/soc/cores/clock.py b/litex/soc/cores/clock.py index 1a56abac3..4b6addab2 100644 --- a/litex/soc/cores/clock.py +++ b/litex/soc/cores/clock.py @@ -856,3 +856,31 @@ class CycloneVPLL(IntelClocking): "-C8" : (0e6, 460e6), "-A7" : (0e6, 460e6), }[speedgrade] + +# Intel / Cyclone10LP ------------------------------------------------------------------------------ + +class Cyclone10LPPLL(IntelClocking): + nclkouts_max = 5 + n_div_range = (1, 512+1) + m_div_range = (1, 512+1) + c_div_range = (1, 512+1) + clkin_pfd_freq_range = (5e6, 325e6) # FIXME: use + vco_freq_range = (600e6, 1300e6) + def __init__(self, speedgrade="-C6"): + self.logger = logging.getLogger("Cyclone10LPPLL") + self.logger.info("Creating Cyclone10LPPLL, {}.".format(colorer("speedgrade {}".format(speedgrade)))) + IntelClocking.__init__(self) + self.clkin_freq_range = { + "-C6" : (5e6, 472.5e6), + "-C8" : (5e6, 472.5e6), + "-I7" : (5e6, 472.5e6), + "-A7" : (5e6, 472.5e6), + "-I8" : (5e6, 362e6), + }[speedgrade] + self.clko_freq_range = { + "-C6" : (0e6, 472.5e6), + "-C8" : (0e6, 402.5e6), + "-I7" : (0e6, 450e6), + "-A7" : (0e6, 450e6), + "-I8" : (0e6, 362e6), + }[speedgrade]