From 9691d205b7c75e05863eaaf5481c03bbefe5d20f Mon Sep 17 00:00:00 2001 From: Andrew E Wilson Date: Tue, 7 Jun 2022 00:45:27 -0600 Subject: [PATCH] adding JTAG support for the xcau, Xilinx Artix UltraScale+ --- litex/soc/cores/jtag.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/litex/soc/cores/jtag.py b/litex/soc/cores/jtag.py index 74e5928c0..97b827ad6 100644 --- a/litex/soc/cores/jtag.py +++ b/litex/soc/cores/jtag.py @@ -307,7 +307,7 @@ class XilinxJTAG(Module): prim_dict = { # Primitive Name Ðevice (startswith) "BSCAN_SPARTAN6" : ["xc6"], - "BSCANE2" : ["xc7a", "xc7k", "xc7v", "xc7z"] + ["xcku", "xcvu", "xczu"], + "BSCANE2" : ["xc7a", "xc7k", "xc7v", "xc7z"] + ["xcau", "xcku", "xcvu", "xczu"], } for prim, prim_devs in prim_dict.items(): for prim_dev in prim_devs: