From 2520ab480b0b622c52a48d4220e312b8075bf357 Mon Sep 17 00:00:00 2001
From: Sebastien Bourdeauducq <sb@m-labs.hk>
Date: Tue, 3 Nov 2015 10:37:31 +0800
Subject: [PATCH] wishbone: add read/write simulation methods

---
 misoc/interconnect/wishbone.py | 24 ++++++++++++++++++++++++
 1 file changed, 24 insertions(+)

diff --git a/misoc/interconnect/wishbone.py b/misoc/interconnect/wishbone.py
index f549135e9..990908ddc 100644
--- a/misoc/interconnect/wishbone.py
+++ b/misoc/interconnect/wishbone.py
@@ -33,6 +33,30 @@ class Interface(Record):
             data_width=data_width,
             sel_width=data_width//8))
 
+    def _do_transaction(self):
+        yield self.cyc.eq(1)
+        yield self.stb.eq(1)
+        yield
+        while not (yield self.ack):
+            yield
+        yield self.cyc.eq(0)
+        yield self.stb.eq(0)
+
+    def write(self, adr, dat, sel=None):
+        if sel is None:
+            sel = 2**len(self.sel) - 1
+        yield self.adr.eq(adr)
+        yield self.dat_w.eq(dat)
+        yield self.sel.eq(sel)
+        yield self.we.eq(1)
+        yield from self._do_transaction()
+
+    def read(self, adr):
+        yield self.adr.eq(adr)
+        yield self.we.eq(0)
+        yield from self._do_transaction()
+        return (yield self.dat_r)
+
 
 class InterconnectPointToPoint(Module):
     def __init__(self, master, slave):