From 2538b2c300f363e0639778422d20af5202b3d012 Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Tue, 1 Sep 2020 11:50:08 +0200 Subject: [PATCH] soc/cores/clock: add with_reset parameter to create_clkout on iCE40PLL/ECP5PLL (similar to others PLLs). Avoid instantiating the AsyncResetSynchronizer manually. --- litex/soc/cores/clock.py | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) diff --git a/litex/soc/cores/clock.py b/litex/soc/cores/clock.py index 10dcca243..083e44a31 100644 --- a/litex/soc/cores/clock.py +++ b/litex/soc/cores/clock.py @@ -584,13 +584,15 @@ class iCE40PLL(Module): self.clkin_freq = freq register_clkin_log(self.logger, clkin, freq) - def create_clkout(self, cd, freq, margin=1e-2): + def create_clkout(self, cd, freq, margin=1e-2, with_reset=True): (clko_freq_min, clko_freq_max) = self.clko_freq_range assert freq >= clko_freq_min assert freq <= clko_freq_max assert self.nclkouts < self.nclkouts_max clkout = Signal() self.clkouts[self.nclkouts] = (clkout, freq, 0, margin) + if with_reset: + self.specials += AsyncResetSynchronizer(cd, ~self.locked | self.reset) self.comb += cd.clk.eq(clkout) create_clkout_log(self.logger, cd.name, freq, margin, self.nclkouts) self.nclkouts += 1 @@ -684,13 +686,15 @@ class ECP5PLL(Module): self.clkin_freq = freq register_clkin_log(self.logger, clkin, freq) - def create_clkout(self, cd, freq, phase=0, margin=1e-2): + def create_clkout(self, cd, freq, phase=0, margin=1e-2, with_reset=True): (clko_freq_min, clko_freq_max) = self.clko_freq_range assert freq >= clko_freq_min assert freq <= clko_freq_max assert self.nclkouts < self.nclkouts_max clkout = Signal() self.clkouts[self.nclkouts] = (clkout, freq, phase, margin) + if with_reset: + self.specials += AsyncResetSynchronizer(cd, ~self.locked | self.reset) self.comb += cd.clk.eq(clkout) create_clkout_log(self.logger, cd.name, freq, margin, self.nclkouts) self.nclkouts += 1