From 2567a0ae1d9400cf52acd195a29c4d15dd913d3d Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Sun, 1 Dec 2019 21:26:37 +0100 Subject: [PATCH] soc/cores/gpio: add GPIO Tristate --- litex/soc/cores/gpio.py | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/litex/soc/cores/gpio.py b/litex/soc/cores/gpio.py index 210288982..a2541072f 100644 --- a/litex/soc/cores/gpio.py +++ b/litex/soc/cores/gpio.py @@ -29,3 +29,17 @@ class GPIOInOut(Module): def get_csrs(self): return self.gpio_in.get_csrs() + self.gpio_out.get_csrs() + +# GPIO Tristate ------------------------------------------------------------------------------------ + +class GPIOTristate(Module, AutoCSR): + def __init__(self, pads): + self._oe = CSRStorage(len(pads)) + self._in = CSRStatus(len(pads)) + self._out = CSRStorage(len(pads)) + + t = TSTriple(len(pads)) + self.specials += t.get_tristate(pads) + self.comb += t.oe.eq(self._oe.storage) + self.comb += t.o.eq(self._out.storage) + self.specials += MultiReg(t.i, self._in.status)