From 25acf17312b29e7b9d9c9c6f5eea28e3b9d05d6c Mon Sep 17 00:00:00 2001 From: Sebastien Bourdeauducq Date: Tue, 28 Jan 2014 13:50:01 +0100 Subject: [PATCH] Refresh testbenches and convert to new API --- misoclib/dvisampler/chansync.py | 41 +++++ misoclib/framebuffer/dvi.py | 18 +- .../lasmicon/test}/bankmachine.py | 31 ++-- .../lasmicon/test}/common.py | 16 +- .../lasmicon/test}/lasmicon.py | 13 +- .../lasmicon/test}/lasmicon_df.py | 14 +- .../lasmicon/test}/lasmicon_wb.py | 13 +- .../lasmicon/test}/refresher.py | 20 +-- misoclib/memtest/__init__.py | 36 ++-- misoclib/spiflash/__init__.py | 26 +-- misoclib/videostream/downscaler.py | 10 +- tb/dvisampler/chansync.py | 46 ----- tb/framebuffer/framebuffer.py | 37 ---- tb/s6ddrphy/Makefile | 25 --- tb/s6ddrphy/gtkwave.sav | 45 ----- tb/s6ddrphy/tb_s6ddrphy.v | 169 ------------------ 16 files changed, 119 insertions(+), 441 deletions(-) rename {tb/lasmicon => misoclib/lasmicon/test}/bankmachine.py (55%) rename {tb/lasmicon => misoclib/lasmicon/test}/common.py (87%) rename {tb/lasmicon => misoclib/lasmicon/test}/lasmicon.py (80%) rename {tb/lasmicon => misoclib/lasmicon/test}/lasmicon_df.py (81%) rename {tb/lasmicon => misoclib/lasmicon/test}/lasmicon_wb.py (81%) rename {tb/lasmicon => misoclib/lasmicon/test}/refresher.py (76%) delete mode 100644 tb/dvisampler/chansync.py delete mode 100644 tb/framebuffer/framebuffer.py delete mode 100644 tb/s6ddrphy/Makefile delete mode 100644 tb/s6ddrphy/gtkwave.sav delete mode 100644 tb/s6ddrphy/tb_s6ddrphy.v diff --git a/misoclib/dvisampler/chansync.py b/misoclib/dvisampler/chansync.py index 270ef40e8..c8475608b 100644 --- a/misoclib/dvisampler/chansync.py +++ b/misoclib/dvisampler/chansync.py @@ -86,3 +86,44 @@ class ChanSync(Module, AutoCSR): ) ) self.specials += MultiReg(self.chan_synced, self._r_channels_synced.status) + +class _TB(Module): + def __init__(self, test_seq_it): + self.test_seq_it = test_seq_it + + self.submodules.chansync = RenameClockDomains(ChanSync(), {"pix": "sys"}) + self.comb += self.chansync.valid_i.eq(1) + + def do_simulation(self, selfp): + try: + de0, de1, de2 = next(self.test_seq_it) + except StopIteration: + raise StopSimulation + + selfp.chansync.data_in0.de = de0 + selfp.chansync.data_in1.de = de1 + selfp.chansync.data_in2.de = de2 + selfp.chansync.data_in0.d = selfp.simulator.cycle_counter + selfp.chansync.data_in1.d = selfp.simulator.cycle_counter + selfp.chansync.data_in2.d = selfp.simulator.cycle_counter + + out0 = selfp.chansync.data_out0.d + out1 = selfp.chansync.data_out1.d + out2 = selfp.chansync.data_out2.d + + print("{0:5} {1:5} {2:5}".format(out0, out1, out2)) + +if __name__ == "__main__": + from migen.sim.generic import run_simulation + + test_seq = [ + (1, 1, 1), + (1, 1, 0), + (0, 0, 0), + (0, 0, 0), + (0, 0, 1), + (1, 1, 1), + (1, 1, 1), + ] + tb = _TB(iter(test_seq*2)) + run_simulation(tb) diff --git a/misoclib/framebuffer/dvi.py b/misoclib/framebuffer/dvi.py index 9c085079c..d0b92e4b3 100644 --- a/misoclib/framebuffer/dvi.py +++ b/misoclib/framebuffer/dvi.py @@ -164,18 +164,18 @@ class _EncoderTB(Module): self.submodules.dut = Encoder() self.comb += self.dut.de.eq(1) - def do_simulation(self, s): + def do_simulation(self, selfp): if self._end_cycle is None: try: nv = next(self._iter_inputs) except StopIteration: - self._end_cycle = s.cycle_counter + 4 + self._end_cycle = selfp.simulator.cycle_counter + 4 else: - s.wr(self.dut.d, nv) - if s.cycle_counter == self._end_cycle: - s.interrupt = True - if s.cycle_counter > 4: - self.outs.append(s.rd(self.dut.out)) + selfp.dut.d = nv + if selfp.simulator.cycle_counter == self._end_cycle: + raise StopSimulation + if selfp.simulator.cycle_counter > 4: + self.outs.append(selfp.dut.out) def _bit(i, n): return (i >> n) & 1 @@ -197,13 +197,13 @@ def _decode_tmds(b): return de, hsync, vsync, value if __name__ == "__main__": - from migen.sim.generic import Simulator + from migen.sim.generic import run_simulation from random import Random rng = Random(788) test_list = [rng.randrange(256) for i in range(500)] tb = _EncoderTB(test_list) - Simulator(tb).run() + run_simulation(tb) check = [_decode_tmds(out)[3] for out in tb.outs] assert(check == test_list) diff --git a/tb/lasmicon/bankmachine.py b/misoclib/lasmicon/test/bankmachine.py similarity index 55% rename from tb/lasmicon/bankmachine.py rename to misoclib/lasmicon/test/bankmachine.py index 3a45daee8..d446fb0f8 100644 --- a/tb/lasmicon/bankmachine.py +++ b/misoclib/lasmicon/test/bankmachine.py @@ -1,10 +1,10 @@ from migen.fhdl.std import * from migen.bus.lasmibus import * -from migen.sim.generic import Simulator, TopLevel +from migen.sim.generic import run_simulation from misoclib.lasmicon.bankmachine import * -from common import sdram_geom, sdram_timing, CommandLogger +from common import sdram_phy, sdram_geom, sdram_timing, CommandLogger def my_generator(): for x in range(10): @@ -15,30 +15,27 @@ def my_generator(): class TB(Module): def __init__(self): self.req = Interface(32, 32, 1, - sdram_timing.req_queue_size, sdram_timing.read_latency, sdram_timing.write_latency) + sdram_timing.req_queue_size, sdram_phy.read_latency, sdram_phy.write_latency) self.submodules.dut = BankMachine(sdram_geom, sdram_timing, 2, 0, self.req) self.submodules.logger = CommandLogger(self.dut.cmd, True) self.generator = my_generator() self.dat_ack_cnt = 0 - def do_simulation(self, s): - if s.rd(self.req.dat_ack): + def do_simulation(self, selfp): + if selfp.req.dat_ack: self.dat_ack_cnt += 1 - if s.rd(self.req.req_ack): + if selfp.req.req_ack: try: we, adr = next(self.generator) except StopIteration: - s.wr(self.req.stb, 0) - if not s.rd(self.req.lock): - s.interrupt = True + selfp.req.stb = 0 + if not selfp.req.lock: print("data ack count: {0}".format(self.dat_ack_cnt)) + raise StopSimulation return - s.wr(self.req.adr, adr) - s.wr(self.req.we, we) - s.wr(self.req.stb, 1) + selfp.req.adr = adr + selfp.req.we = we + selfp.req.stb = 1 -def main(): - sim = Simulator(TB(), TopLevel("my.vcd")) - sim.run() - -main() +if __name__ == "__main__": + run_simulation(TB(), vcd_name="my.vcd") diff --git a/tb/lasmicon/common.py b/misoclib/lasmicon/test/common.py similarity index 87% rename from tb/lasmicon/common.py rename to misoclib/lasmicon/test/common.py index 74bf579a5..a84b0018d 100644 --- a/tb/lasmicon/common.py +++ b/misoclib/lasmicon/test/common.py @@ -2,7 +2,6 @@ from fractions import Fraction from math import ceil from migen.fhdl.std import * -from migen.sim.generic import Proxy from misoclib import lasmicon @@ -80,22 +79,23 @@ class CommandLogger(Module): if rw: self.comb += self.cmd.ack.eq(1) - def do_simulation(self, s): - elts = ["@" + str(s.cycle_counter)] - cmdp = Proxy(s, self.cmd) + def do_simulation(self, selfp): + elts = ["@" + str(selfp.simulator.cycle_counter)] + cmdp = selfp.cmd elts += decode_sdram(cmdp.ras_n, cmdp.cas_n, cmdp.we_n, cmdp.ba, cmdp.a) if len(elts) > 1: print("\t".join(elts)) + do_simulation.passive = True class DFILogger(Module): def __init__(self, dfi): self.dfi = dfi - def do_simulation(self, s): - dfip = Proxy(s, self.dfi) - + def do_simulation(self, selfp): + dfip = selfp.dfi for i, p in enumerate(dfip.phases): - elts = ["@" + str(s.cycle_counter) + ":" + str(i)] + elts = ["@" + str(selfp.simulator.cycle_counter) + ":" + str(i)] elts += decode_sdram(p.ras_n, p.cas_n, p.we_n, p.bank, p.address) if len(elts) > 1: print("\t".join(elts)) + do_simulation.passive = True diff --git a/tb/lasmicon/lasmicon.py b/misoclib/lasmicon/test/lasmicon.py similarity index 80% rename from tb/lasmicon/lasmicon.py rename to misoclib/lasmicon/test/lasmicon.py index 7ce009a05..05466d445 100644 --- a/tb/lasmicon/lasmicon.py +++ b/misoclib/lasmicon/test/lasmicon.py @@ -1,6 +1,6 @@ from migen.fhdl.std import * from migen.bus.lasmibus import * -from migen.sim.generic import Simulator, TopLevel +from migen.sim.generic import run_simulation from misoclib.lasmicon import * @@ -35,12 +35,5 @@ class TB(Module): for n, master in enumerate(masters)] self.submodules += self.initiators - def do_simulation(self, s): - s.interrupt = all(initiator.done for initiator in self.initiators) - - -def main(): - sim = Simulator(TB(), TopLevel("my.vcd")) - sim.run() - -main() +if __name__ == "__main__": + run_simulation(TB(), vcd_name="my.vcd") diff --git a/tb/lasmicon/lasmicon_df.py b/misoclib/lasmicon/test/lasmicon_df.py similarity index 81% rename from tb/lasmicon/lasmicon_df.py rename to misoclib/lasmicon/test/lasmicon_df.py index 512c94249..b5380df5b 100644 --- a/tb/lasmicon/lasmicon_df.py +++ b/misoclib/lasmicon/test/lasmicon_df.py @@ -1,7 +1,7 @@ from migen.fhdl.std import * from migen.bus import lasmibus from migen.actorlib import dma_lasmi -from migen.sim.generic import Simulator, TopLevel, Proxy +from migen.sim.generic import run_simulation from misoclib.lasmicon import * @@ -11,7 +11,6 @@ class TB(Module): def __init__(self): self.submodules.ctler = LASMIcon(sdram_phy, sdram_geom, sdram_timing) self.submodules.xbar = lasmibus.Crossbar([self.ctler.lasmic], self.ctler.nrowbits) - self.xbar.get_master() # FIXME: remove dummy master self.submodules.logger = DFILogger(self.ctler.dfi) self.submodules.writer = dma_lasmi.Writer(self.xbar.get_master()) @@ -25,8 +24,8 @@ class TB(Module): ) self.open_row = None - def do_simulation(self, s): - dfip = Proxy(s, self.ctler.dfi) + def do_simulation(self, selfp): + dfip = selfp.ctler.dfi for p in dfip.phases: if p.ras_n and not p.cas_n and not p.we_n: # write d = dfip.phases[0].wrdata | (dfip.phases[1].wrdata << 64) @@ -36,8 +35,5 @@ class TB(Module): elif not p.ras_n and p.cas_n and p.we_n: # activate self.open_row = p.address -def main(): - sim = Simulator(TB(), TopLevel("my.vcd")) - sim.run(3500) - -main() +if __name__ == "__main__": + run_simulation(TB(), ncycles=3500, vcd_name="my.vcd") diff --git a/tb/lasmicon/lasmicon_wb.py b/misoclib/lasmicon/test/lasmicon_wb.py similarity index 81% rename from tb/lasmicon/lasmicon_wb.py rename to misoclib/lasmicon/test/lasmicon_wb.py index 89b5fa334..1a385ed9b 100644 --- a/tb/lasmicon/lasmicon_wb.py +++ b/misoclib/lasmicon/test/lasmicon_wb.py @@ -1,7 +1,7 @@ from migen.fhdl.std import * from migen.bus import wishbone, wishbone2lasmi, lasmibus from migen.bus.transactions import * -from migen.sim.generic import Simulator, TopLevel +from migen.sim.generic import run_simulation from misoclib.lasmicon import * @@ -27,17 +27,10 @@ class TB(Module): def __init__(self): self.submodules.ctler = LASMIcon(sdram_phy, sdram_geom, sdram_timing) self.submodules.xbar = lasmibus.Crossbar([self.ctler.lasmic], self.ctler.nrowbits) - self.xbar.get_master() # FIXME: remove dummy master self.submodules.logger = DFILogger(self.ctler.dfi) self.submodules.bridge = wishbone2lasmi.WB2LASMI(l2_size//4, self.xbar.get_master()) self.submodules.initiator = wishbone.Initiator(my_generator()) self.submodules.conn = wishbone.InterconnectPointToPoint(self.initiator.bus, self.bridge.wishbone) - def do_simulation(self, s): - s.interrupt = self.initiator.done - -def main(): - sim = Simulator(TB(), TopLevel("my.vcd")) - sim.run() - -main() +if __name__ == "__main__": + run_simulation(TB(), vcd_name="my.vcd") diff --git a/tb/lasmicon/refresher.py b/misoclib/lasmicon/test/refresher.py similarity index 76% rename from tb/lasmicon/refresher.py rename to misoclib/lasmicon/test/refresher.py index daa865307..57b954a32 100644 --- a/tb/lasmicon/refresher.py +++ b/misoclib/lasmicon/test/refresher.py @@ -1,7 +1,7 @@ from random import Random from migen.fhdl.std import * -from migen.sim.generic import Simulator, TopLevel +from migen.sim.generic import run_simulation from misoclib.lasmicon.refresher import * @@ -14,22 +14,22 @@ class Granter(Module): self.state = 0 self.prng = Random(92837) - def do_simulation(self, s): - elts = ["@" + str(s.cycle_counter)] + def do_simulation(self, selfp): + elts = ["@" + str(selfp.simulator.cycle_counter)] if self.state == 0: - if s.rd(self.req): + if selfp.req: elts.append("Refresher requested access") self.state = 1 elif self.state == 1: if self.prng.randrange(0, 5) == 0: elts.append("Granted access to refresher") - s.wr(self.ack, 1) + selfp.ack = 1 self.state = 2 elif self.state == 2: - if not s.rd(self.req): + if not selfp.req: elts.append("Refresher released access") - s.wr(self.ack, 0) + selfp.ack = 0 self.state = 0 if len(elts) > 1: @@ -41,7 +41,5 @@ class TB(Module): self.submodules.logger = CommandLogger(self.dut.cmd) self.submodules.granter = Granter(self.dut.req, self.dut.ack) -def main(): - Simulator(TB()).run(400) - -main() +if __name__ == "__main__": + run_simulation(TB(), ncycles=400) diff --git a/misoclib/memtest/__init__.py b/misoclib/memtest/__init__.py index 92522295e..46d14b0ce 100644 --- a/misoclib/memtest/__init__.py +++ b/misoclib/memtest/__init__.py @@ -25,25 +25,6 @@ class LFSR(Module): self.o.eq(Cat(*curval)) ] -def _print_lfsr_code(): - from migen.fhdl import verilog - dut = LFSR(3, 4, [3, 2]) - print(verilog.convert(dut, ios={dut.ce, dut.reset, dut.o})) - -class _LFSRTB(Module): - def __init__(self, *args, **kwargs): - self.submodules.lfsr = LFSR(*args, **kwargs) - self.comb += self.lfsr.ce.eq(1) - - def do_simulation(self, s): - print("{0:032x}".format(s.rd(self.lfsr.o))) - -def _sim_lfsr(): - from migen.sim.generic import Simulator - tb = _LFSRTB(128) - sim = Simulator(tb) - sim.run(20) - memtest_magic = 0x361f class MemtestWriter(Module): @@ -113,6 +94,19 @@ class MemtestReader(Module): def get_csrs(self): return [self._r_magic, self._r_reset, self._r_error_count] + self._dma.get_csrs() +class _LFSRTB(Module): + def __init__(self, *args, **kwargs): + self.submodules.dut = LFSR(*args, **kwargs) + self.comb += self.dut.ce.eq(1) + + def do_simulation(self, selfp): + print("{0:032x}".format(selfp.dut.o)) + if __name__ == "__main__": - _print_lfsr_code() - _sim_lfsr() + from migen.fhdl import verilog + from migen.sim.generic import run_simulation + + lfsr = LFSR(3, 4, [3, 2]) + print(verilog.convert(lfsr, ios={lfsr.ce, lfsr.reset, lfsr.o})) + + run_simulation(_LFSRTB(128), ncycles=20) diff --git a/misoclib/spiflash/__init__.py b/misoclib/spiflash/__init__.py index 6dcfefbf3..115ff167f 100644 --- a/misoclib/spiflash/__init__.py +++ b/misoclib/spiflash/__init__.py @@ -4,7 +4,6 @@ from migen.bus import wishbone from migen.genlib.misc import timeline from migen.genlib.record import Record - class SpiFlash(Module): def __init__(self, pads, cmd=0xfffefeff, cmd_width=32, addr_width=24, dummy=15, div=2): @@ -85,8 +84,6 @@ class SpiFlash(Module): self.sync += timeline(bus.cyc & bus.stb & (i == div - 1), tseq) - - class SpiFlashTB(Module): def __init__(self): self.submodules.master = wishbone.Initiator(self.gen_reads()) @@ -103,18 +100,17 @@ class SpiFlashTB(Module): yield t print("read {} in {} cycles(s)".format(t.data, t.latency)) - def do_simulation(self, s): - if s.rd(self.pads.cs_n): + def do_simulation(self, selfp): + if selfp.pads.cs_n: self.cycle = 0 else: self.cycle += 1 - if not s.rd(self.slave.dq.oe): - s.wr(self.slave.dq.i, self.cycle & 0xf) - s.interrupt = self.master.done + if not selfp.slave.dq.oe: + selfp.slave.dq.i = self.cycle & 0xf + do_simulation.passive = True - -def _main(): - from migen.sim.generic import Simulator, TopLevel +if __name__ == "__main__": + from migen.sim.generic import run_simulation from migen.fhdl import verilog pads = Record([("cs_n", 1), ("clk", 1), ("dq", 4)]) @@ -122,10 +118,4 @@ def _main(): print(verilog.convert(s, ios={pads.clk, pads.cs_n, pads.dq, s.bus.adr, s.bus.dat_r, s.bus.cyc, s.bus.ack, s.bus.stb})) - tb = SpiFlashTB() - sim = Simulator(tb, TopLevel("spiflash.vcd")) - sim.run() - - -if __name__ == "__main__": - _main() + run_simulation(SpiFlashTB(), vcd_name="spiflash.vcd") diff --git a/misoclib/videostream/downscaler.py b/misoclib/videostream/downscaler.py index cda3b9bb5..e508839b1 100644 --- a/misoclib/videostream/downscaler.py +++ b/misoclib/videostream/downscaler.py @@ -1,5 +1,6 @@ from migen.fhdl.std import * from migen.genlib.fsm import * +from migen.sim.generic import run_simulation class Chopper(Module): def __init__(self, N, frac_bits): @@ -104,9 +105,8 @@ class _ChopperTB(Module): def __init__(self): self.submodules.dut = Chopper(4, 16) - def gen_simulation(self, s): - from migen.sim.generic import Proxy - dut = Proxy(s, self.dut) + def gen_simulation(self, selfp): + dut = selfp.dut dut.init = 1 dut.p = 320 @@ -130,6 +130,4 @@ class _ChopperTB(Module): print("Ones: {} (expected: {})".format(ones, dut.p*niter*4//dut.q)) if __name__ == "__main__": - from migen.sim.generic import Simulator - with Simulator(_ChopperTB()) as s: - s.run(1000) + run_simulation(_ChopperTB()) diff --git a/tb/dvisampler/chansync.py b/tb/dvisampler/chansync.py deleted file mode 100644 index 4327d2d38..000000000 --- a/tb/dvisampler/chansync.py +++ /dev/null @@ -1,46 +0,0 @@ -from migen.fhdl.std import * -from migen.sim.generic import * - -from misoclib.dvisampler.chansync import ChanSync - -class TB(Module): - def __init__(self, test_seq_it): - self.test_seq_it = test_seq_it - - self.submodules.chansync = RenameClockDomains(ChanSync(), {"pix": "sys"}) - self.comb += self.chansync.valid_i.eq(1) - - def do_simulation(self, s): - try: - de0, de1, de2 = next(self.test_seq_it) - except StopIteration: - s.interrupt = True - return - - s.wr(self.chansync.data_in0.de, de0) - s.wr(self.chansync.data_in1.de, de1) - s.wr(self.chansync.data_in2.de, de2) - s.wr(self.chansync.data_in0.d, s.cycle_counter) - s.wr(self.chansync.data_in1.d, s.cycle_counter) - s.wr(self.chansync.data_in2.d, s.cycle_counter) - - out0 = s.rd(self.chansync.data_out0.d) - out1 = s.rd(self.chansync.data_out1.d) - out2 = s.rd(self.chansync.data_out2.d) - - print("{0:5} {1:5} {2:5}".format(out0, out1, out2)) - -def main(): - test_seq = [ - (1, 1, 1), - (1, 1, 0), - (0, 0, 0), - (0, 0, 0), - (0, 0, 1), - (1, 1, 1), - (1, 1, 1), - ] - tb = TB(iter(test_seq*2)) - Simulator(tb).run() - -main() diff --git a/tb/framebuffer/framebuffer.py b/tb/framebuffer/framebuffer.py deleted file mode 100644 index 9d8d1da14..000000000 --- a/tb/framebuffer/framebuffer.py +++ /dev/null @@ -1,37 +0,0 @@ -from migen.fhdl.std import * -from migen.bus import asmibus -from migen.sim.generic import Simulator - -from misoclib.framebuffer import * - -def main(): - hub = asmibus.Hub(16, 128) - port = hub.get_port() - hub.finalize() - - dut = Framebuffer(1, port, True) - - fragment = hub.get_fragment() + dut.get_fragment() - sim = Simulator(fragment) - - sim.run(1) - def csr_w(addr, d): - sim.wr(dut.bank.description[addr].field.storage, d) - - hres = 4 - vres = 4 - - csr_w(1, hres) # hres - csr_w(2, hres+3) # hsync_start - csr_w(3, hres+5) # hsync_stop - csr_w(4, hres+10) # hscan - csr_w(5, vres) # vres - csr_w(6, vres+3) # vsync_start - csr_w(7, vres+5) # vsync_stop - csr_w(8, vres+10) # vscan - csr_w(10, hres*vres*4) # length - csr_w(0, 1) # enable - - sim.run(1000) - -main() diff --git a/tb/s6ddrphy/Makefile b/tb/s6ddrphy/Makefile deleted file mode 100644 index 0cc56433a..000000000 --- a/tb/s6ddrphy/Makefile +++ /dev/null @@ -1,25 +0,0 @@ -SOURCES=tb_s6ddrphy.v ../../verilog/s6ddrphy/s6ddrphy.v \ - $(XILINX)/verilog/src/unisims/ODDR2.v \ - $(XILINX)/verilog/src/unisims/OSERDES2.v \ - $(XILINX)/verilog/src/unisims/ISERDES2.v \ - $(XILINX)/verilog/src/unisims/IOBUF.v \ - $(XILINX)/verilog/src/unisims/OBUFT.v \ - $(XILINX)/verilog/src/unisims/BUFPLL.v - -RM ?= rm -f - -all: tb_s6ddrphy - -isim: tb_s6ddrphy - ./tb_s6ddrphy - -cversim: $(SOURCES) - cver $(SOURCES) - -clean: - $(RM) tb_s6ddrphy verilog.log s6ddrphy.vcd - -tb_s6ddrphy: $(SOURCES) - iverilog -o tb_s6ddrphy $(SOURCES) - -.PHONY: all clean isim cversim diff --git a/tb/s6ddrphy/gtkwave.sav b/tb/s6ddrphy/gtkwave.sav deleted file mode 100644 index ec6349735..000000000 --- a/tb/s6ddrphy/gtkwave.sav +++ /dev/null @@ -1,45 +0,0 @@ -[timestart] 0 -[size] 1741 771 -[pos] -1 -1 -*-14.000000 0 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -[treeopen] tb_s6ddrphy. -[treeopen] tb_s6ddrphy.dut. -[treeopen] tb_s6ddrphy.dut.gen_dq[0]. -@28 -tb_s6ddrphy.dut.sys_clk -tb_s6ddrphy.dut.clk2x_270 -tb_s6ddrphy.dut.clk4x_wr -tb_s6ddrphy.dut.clk4x_wr_strb -@22 -tb_s6ddrphy.dut.dfi_address_p0[12:0] -tb_s6ddrphy.dut.dfi_address_p1[12:0] -@200 -- -@22 -tb_s6ddrphy.dut.sd_a[12:0] -@28 -tb_s6ddrphy.dut.sd_clk_out_p -@22 -tb_s6ddrphy.dut.sd_dm[3:0] -tb_s6ddrphy.dut.sd_dq[31:0] -tb_s6ddrphy.dut.sd_dqs[3:0] -@200 -- -@28 -tb_s6ddrphy.dut.dfi_wrdata_en_p1 -@22 -tb_s6ddrphy.dut.dfi_wrdata_mask_p0[7:0] -tb_s6ddrphy.dut.dfi_wrdata_mask_p1[7:0] -tb_s6ddrphy.dut.dfi_wrdata_p0[63:0] -tb_s6ddrphy.dut.dfi_wrdata_p1[63:0] -@200 -- -@29 -tb_s6ddrphy.dut.dfi_rddata_en_p0 -@22 -tb_s6ddrphy.dut.dfi_rddata_w0[63:0] -tb_s6ddrphy.dut.dfi_rddata_w1[63:0] -@28 -tb_s6ddrphy.dut.dfi_rddata_valid_w0 -[pattern_trace] 1 -[pattern_trace] 0 diff --git a/tb/s6ddrphy/tb_s6ddrphy.v b/tb/s6ddrphy/tb_s6ddrphy.v deleted file mode 100644 index 13c41e792..000000000 --- a/tb/s6ddrphy/tb_s6ddrphy.v +++ /dev/null @@ -1,169 +0,0 @@ -`timescale 1ns / 1ps - -module tb_s6ddrphy(); - -reg sys_clk = 1'b0; -reg clk2x_270 = 1'b0; -reg clk4x_wr = 1'b0; -wire clk4x_wr_strb; -wire clk4x_rd = clk4x_wr; -wire clk4x_rd_strb = clk4x_wr_strb; - -initial begin - while(1) begin - sys_clk <= 1'b1; - #6; - sys_clk <= 1'b0; - #6; - end -end - -initial begin - #4.5; - while(1) begin - clk2x_270 <= 1'b1; - #3; - clk2x_270 <= 1'b0; - #3; - end -end - -initial begin - while(1) begin - clk4x_wr <= 1'b1; - #1.5; - clk4x_wr <= 1'b0; - #1.5; - end -end - -BUFPLL #( - .DIVIDE(4) -) bufpll ( - .PLLIN(clk4x_wr), - .GCLK(sys_clk), - .LOCKED(1'b1), - .IOCLK(), - .LOCK(), - .SERDESSTROBE(clk4x_wr_strb) -); - -reg [12:0] dfi_address_p0 = 0; -reg [12:0] dfi_address_p1 = 0; - -reg dfi_wrdata_en_p0 = 0; -reg [7:0] dfi_wrdata_mask_p0 = 0; -reg [63:0] dfi_wrdata_p0 = 0; -reg dfi_wrdata_en_p1 = 0; -reg [7:0] dfi_wrdata_mask_p1 = 0; -reg [63:0] dfi_wrdata_p1 = 0; - -reg dfi_rddata_en_p0 = 0; -reg dfi_rddata_en_p1 = 0; - -wire [31:0] sd_dq; -reg [31:0] dq_tb = 32'hzzzzzzzz; -assign sd_dq = dq_tb; - -s6ddrphy #( - .NUM_AD(13), - .NUM_BA(2), - .NUM_D(64) -) dut ( - .sys_clk(sys_clk), - .clk2x_270(clk2x_270), - .clk4x_wr(clk4x_wr), - .clk4x_wr_strb(clk4x_wr_strb), - .clk4x_rd(clk4x_rd), - .clk4x_rd_strb(clk4x_rd_strb), - - .sd_clk_out_p(), - .sd_clk_out_n(), - - .dfi_address_p0(dfi_address_p0), - .dfi_address_p1(dfi_address_p1), - .sd_a(), - - .dfi_wrdata_en_p0(dfi_wrdata_en_p0), - .dfi_wrdata_mask_p0(dfi_wrdata_mask_p0), - .dfi_wrdata_p0(dfi_wrdata_p0), - .dfi_wrdata_en_p1(dfi_wrdata_en_p1), - .dfi_wrdata_mask_p1(dfi_wrdata_mask_p1), - .dfi_wrdata_p1(dfi_wrdata_p1), - .sd_dq(sd_dq), - .sd_dm(), - .sd_dqs(), - - .dfi_rddata_en_p0(dfi_rddata_en_p0), - .dfi_rddata_en_p1(dfi_rddata_en_p1), - .dfi_rddata_w0(), - .dfi_rddata_w1(), - .dfi_rddata_valid_w0(), - .dfi_rddata_valid_w1() -); - -`define TEST_SIMPLE_CMD -`define TEST_WRITE -`define TEST_READ - -initial begin - $dumpfile("s6ddrphy.vcd"); - $dumpvars(3, dut); - -`ifdef TEST_SIMPLE_CMD - #13; - dfi_address_p0 <= 13'h1aba; - dfi_address_p1 <= 13'h1234; - #12; - dfi_address_p0 <= 0; - dfi_address_p1 <= 0; - #59; -`endif - -`ifdef TEST_WRITE - #13; - dfi_address_p1 <= 13'h0dbe; - dfi_wrdata_en_p1 <= 1; - dfi_wrdata_mask_p0 <= 8'h12; - dfi_wrdata_mask_p1 <= 8'h34; - dfi_wrdata_p0 <= 64'hcafebabeabadface; - dfi_wrdata_p1 <= 64'h0123456789abcdef; - #12; - dfi_address_p1 <= 0; - dfi_wrdata_en_p1 <= 0; - dfi_wrdata_mask_p0 <= 0; - dfi_wrdata_mask_p1 <= 0; - dfi_wrdata_p0 <= 64'd0; - dfi_wrdata_p1 <= 64'd0; - #59; -`endif - -`ifdef TEST_READ - #13; - dfi_address_p0 <= 13'h1234; - dfi_rddata_en_p0 <= 1; - #12; - dfi_address_p0 <= 0; - dfi_rddata_en_p0 <= 0; - #15.5; - dq_tb <= 32'h12345678; - #3; - dq_tb <= 32'hdeadbeef; - #3; - dq_tb <= 32'hcafebabe; - #3; - dq_tb <= 32'habadface; - #3; - dq_tb <= 32'hzzzzzzzz; - #60; -`endif - - $finish; -end - -endmodule - -module glbl(); -wire GSR = 1'b0; -wire GTS = 1'b0; -endmodule