From 25e4d2a2db43ed8e62aa6b3dffc5e3e5ff14aeb3 Mon Sep 17 00:00:00 2001
From: Robert Jordens <jordens@gmail.com>
Date: Sun, 5 Apr 2015 03:49:07 -0600
Subject: [PATCH] decorators: remove deprecated semantics

---
 examples/basic/two_dividers.py |  4 ++--
 migen/genlib/fifo.py           |  6 +++---
 migen/genlib/misc.py           | 12 ++++++------
 3 files changed, 11 insertions(+), 11 deletions(-)

diff --git a/examples/basic/two_dividers.py b/examples/basic/two_dividers.py
index 723522042..79519d4a3 100644
--- a/examples/basic/two_dividers.py
+++ b/examples/basic/two_dividers.py
@@ -2,8 +2,8 @@ from migen.fhdl.std import *
 from migen.fhdl import verilog
 from migen.genlib import divider
 
-@DecorateModule(InsertReset)
-@DecorateModule(InsertCE)
+@ResetInserter()
+@CEInserter()
 class Example(Module):
 	def __init__(self, width):
 		d1 = divider.Divider(width)
diff --git a/migen/genlib/fifo.py b/migen/genlib/fifo.py
index 4a044b8f2..548c3add9 100644
--- a/migen/genlib/fifo.py
+++ b/migen/genlib/fifo.py
@@ -158,7 +158,7 @@ class AsyncFIFO(Module, _FIFOInterface):
 	"""Asynchronous FIFO (first in, first out)
 
 	Read and write interfaces are accessed from different clock domains,
-	named `read` and `write`. Use `RenameClockDomains` to rename to
+	named `read` and `write`. Use `ClockDomainsRenamer` to rename to
 	other names.
 
 	{interface}
@@ -172,8 +172,8 @@ class AsyncFIFO(Module, _FIFOInterface):
 
 		depth_bits = log2_int(depth, True)
 
-		produce = RenameClockDomains(GrayCounter(depth_bits+1), "write")
-		consume = RenameClockDomains(GrayCounter(depth_bits+1), "read")
+		produce = ClockDomainsRenamer("write")(GrayCounter(depth_bits+1))
+		consume = ClockDomainsRenamer("read")(GrayCounter(depth_bits+1))
 		self.submodules += produce, consume
 		self.comb += [
 			produce.ce.eq(self.writable & self.we),
diff --git a/migen/genlib/misc.py b/migen/genlib/misc.py
index 8942ab0ba..b505032e8 100644
--- a/migen/genlib/misc.py
+++ b/migen/genlib/misc.py
@@ -86,24 +86,24 @@ def timeline(trigger, events):
 	sync.append(counterlogic)
 	return sync
 
-@DecorateModule(InsertReset)
-@DecorateModule(InsertCE)
+@ResetInserter()
+@CEInserter()
 class FlipFlop(Module):
 	def __init__(self, *args, **kwargs):
 		self.d = Signal(*args, **kwargs)
 		self.q = Signal(*args, **kwargs)
 		self.sync += self.q.eq(self.d)
 
-@DecorateModule(InsertReset)
-@DecorateModule(InsertCE)
+@ResetInserter()
+@CEInserter()
 class Counter(Module):
 	def __init__(self, *args, increment=1, **kwargs):
 		self.value = Signal(*args, **kwargs)
 		self.width = flen(self.value)
 		self.sync += self.value.eq(self.value+increment)
 
-@DecorateModule(InsertReset)
-@DecorateModule(InsertCE)
+@ResetInserter()
+@CEInserter()
 class Timeout(Module):
 	def __init__(self, length):
 		self.reached = Signal()