From 25ead1ad693d88b0af362c112998531549e01da6 Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Tue, 8 Jun 2021 18:58:08 +0200 Subject: [PATCH] interconnect/stream: Add Gate. --- litex/soc/interconnect/stream.py | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) diff --git a/litex/soc/interconnect/stream.py b/litex/soc/interconnect/stream.py index 559c38e9d..a11ab191d 100644 --- a/litex/soc/interconnect/stream.py +++ b/litex/soc/interconnect/stream.py @@ -293,6 +293,25 @@ class Demultiplexer(Module): cases[i] = self.sink.connect(source) self.comb += Case(self.sel, cases) + +# Gate --------------------------------------------------------------------------------------------- + +class Gate(Module): + def __init__(self, layout, sink_ready_when_disabled=False): + self.sink = Endpoint(layout) + self.source = Endpoint(layout) + self.enable = Signal() + + # # # + + self.comb += [ + If(self.enable, + self.sink.connect(self.source) + ).Else( + self.sink.ready.eq(int(sink_ready_when_disabled)) + ) + ] + # Converter ---------------------------------------------------------------------------------------- class _UpConverter(Module):