From 260577cae8c299adb9923fc1d33dc0311859cce5 Mon Sep 17 00:00:00 2001
From: Jevin Sweval <jevinsweval@gmail.com>
Date: Thu, 2 Jun 2022 16:04:58 -0700
Subject: [PATCH] Add litex.gen.fhdl.verilog.VerilogTime to emit $time

---
 litex/gen/fhdl/verilog.py | 14 ++++++++++++++
 1 file changed, 14 insertions(+)

diff --git a/litex/gen/fhdl/verilog.py b/litex/gen/fhdl/verilog.py
index c2a3a3ca9..ea223140c 100644
--- a/litex/gen/fhdl/verilog.py
+++ b/litex/gen/fhdl/verilog.py
@@ -133,6 +133,18 @@ _ieee_1800_2017_verilog_reserved_keywords = {
 #                                       EXPRESSIONS                                                #
 # ------------------------------------------------------------------------------------------------ #
 
+# Stub for $time in Display() args -----------------------------------------------------------------
+
+class VerilogTime:
+    """Expression for $time in Display() statements
+    
+    Example:
+    self.sync += If(state != old_state,
+        Display("time=%t old_state: %d state: %d", VerilogTime(), old_state, state)
+    )
+    """
+    pass
+
 # Print Constant -----------------------------------------------------------------------------------
 
 def _print_constant(node):
@@ -322,6 +334,8 @@ def _print_node(ns, at, level, node, target_filter=None):
             s += ", "
             if isinstance(arg, Signal):
                 s += ns.get_name(arg)
+            elif isinstance(arg, VerilogTime):
+                s += "$time"
             else:
                 s += str(arg)
         return "\t"*level + "$display(" + s + ");\n"