From 2665a83288b695592b1e4c14b0af75eea8c6f91c Mon Sep 17 00:00:00 2001
From: Florent Kermarrec <florent@enjoy-digital.fr>
Date: Mon, 30 Oct 2017 22:56:09 +0100
Subject: [PATCH] soc/interconnect/stream: expose depth on SyncFIFO

---
 litex/soc/interconnect/stream.py | 1 +
 1 file changed, 1 insertion(+)

diff --git a/litex/soc/interconnect/stream.py b/litex/soc/interconnect/stream.py
index 4c56b06ef..bc6793cac 100644
--- a/litex/soc/interconnect/stream.py
+++ b/litex/soc/interconnect/stream.py
@@ -99,6 +99,7 @@ class SyncFIFO(_FIFOWrapper):
             self,
             fifo.SyncFIFOBuffered if buffered else fifo.SyncFIFO,
             layout, depth)
+        self.depth = self.fifo.depth
         self.level = self.fifo.level