diff --git a/litex/gen/fhdl/memory.py b/litex/build/efinix/memory.py
similarity index 100%
rename from litex/gen/fhdl/memory.py
rename to litex/build/efinix/memory.py
diff --git a/litex/soc/interconnect/wishbone.py b/litex/soc/interconnect/wishbone.py
index 88d0bb79a..a127525a7 100644
--- a/litex/soc/interconnect/wishbone.py
+++ b/litex/soc/interconnect/wishbone.py
@@ -339,7 +339,8 @@ class SRAM(Module):
             self.mem = mem_or_size
         else:
             if no_we:
-                from litex.gen.fhdl.memory import Memory as NoWeMemory
+                # FIXME: Cleanup/Improve integration.
+                from litex.build.efinix.memory import Memory as NoWeMemory
                 self.mem = NoWeMemory(bus_data_width, mem_or_size//(bus_data_width//8), init=init)
             else:
                 self.mem = Memory(bus_data_width, mem_or_size//(bus_data_width//8), init=init)