diff --git a/litex/soc/integration/soc.py b/litex/soc/integration/soc.py
index 430acbe9e..9f36c0d8f 100644
--- a/litex/soc/integration/soc.py
+++ b/litex/soc/integration/soc.py
@@ -1732,8 +1732,8 @@ class LiteXSoC(SoC):
         uart_cdc = stream.ClockDomainCrossing([("data", 8)], cd_from="sys", cd_to=clock_domain)
         setattr(self.submodules, f"{name}_uart_cdc", uart_cdc)
         self.comb += [
-            uart_cdc.sink.valid.eq(self.uart.source.valid & self.uart.source.ready),
-            uart_cdc.sink.data.eq(self.uart.source.data),
+            uart_cdc.sink.valid.eq(self.uart.tx_fifo.source.valid & self.uart.tx_fifo.source.ready),
+            uart_cdc.sink.data.eq(self.uart.tx_fifo.source.data),
             uart_cdc.source.connect(vt.uart_sink),
         ]