From 26db10701acdfaf1d3533769b7c5020e0c0d6fc7 Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Fri, 28 May 2021 11:11:19 +0200 Subject: [PATCH] integration/soc/add_video_terminal: Connect UART to TX FIFO instead of Source. Allow UART to be displayed on terminal with Auto TX flush. --- litex/soc/integration/soc.py | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/litex/soc/integration/soc.py b/litex/soc/integration/soc.py index 430acbe9e..9f36c0d8f 100644 --- a/litex/soc/integration/soc.py +++ b/litex/soc/integration/soc.py @@ -1732,8 +1732,8 @@ class LiteXSoC(SoC): uart_cdc = stream.ClockDomainCrossing([("data", 8)], cd_from="sys", cd_to=clock_domain) setattr(self.submodules, f"{name}_uart_cdc", uart_cdc) self.comb += [ - uart_cdc.sink.valid.eq(self.uart.source.valid & self.uart.source.ready), - uart_cdc.sink.data.eq(self.uart.source.data), + uart_cdc.sink.valid.eq(self.uart.tx_fifo.source.valid & self.uart.tx_fifo.source.ready), + uart_cdc.sink.data.eq(self.uart.tx_fifo.source.data), uart_cdc.source.connect(vt.uart_sink), ]