From 2740dd34e71382fff09486f50a969010d684b1e0 Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Fri, 5 Nov 2021 16:27:38 +0100 Subject: [PATCH] sim/verilator: Revert regular_comb change and just pass it to get_verilog as before. --- litex/build/sim/verilator.py | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/litex/build/sim/verilator.py b/litex/build/sim/verilator.py index 65204b7d1..aef7082d5 100644 --- a/litex/build/sim/verilator.py +++ b/litex/build/sim/verilator.py @@ -204,11 +204,11 @@ class SimVerilatorToolchain: fragment = fragment.get_fragment() platform.finalize(fragment) - if regular_comb: - raise ValueError("SimVerilatorToolchain disallows regular_comb=True") - # Generate verilog - v_output = platform.get_verilog(fragment, name=build_name) + v_output = platform.get_verilog(fragment, + name = build_name, + regular_comb = regular_comb + ) named_sc, named_pc = platform.resolve_signals(v_output.ns) v_file = build_name + ".v" v_output.write(v_file)