From 27b23836070e1394fc0f42331237b1f1cc6fe26e Mon Sep 17 00:00:00 2001 From: Sebastien Bourdeauducq Date: Sat, 26 Sep 2015 21:51:22 +0800 Subject: [PATCH] sdram working on PPro --- misoc/cores/dfii.py | 4 ++-- misoc/cores/lasmicon/__init__.py | 1 + misoc/cores/sdram_phy/gensdrphy.py | 1 + misoc/integration/soc_sdram.py | 14 +++++++------- 4 files changed, 11 insertions(+), 9 deletions(-) diff --git a/misoc/cores/dfii.py b/misoc/cores/dfii.py index 1900f2980..745e3342d 100644 --- a/misoc/cores/dfii.py +++ b/misoc/cores/dfii.py @@ -1,7 +1,7 @@ from migen import * -from migen.bank.description import * -from misoc.mem.sdram.phy import dfi +from misoc.interconnect import dfi +from misoc.interconnect.csr import * class PhaseInjector(Module, AutoCSR): diff --git a/misoc/cores/lasmicon/__init__.py b/misoc/cores/lasmicon/__init__.py index e69de29bb..ad28bfcbf 100644 --- a/misoc/cores/lasmicon/__init__.py +++ b/misoc/cores/lasmicon/__init__.py @@ -0,0 +1 @@ +from misoc.cores.lasmicon.core import LASMIcon diff --git a/misoc/cores/sdram_phy/gensdrphy.py b/misoc/cores/sdram_phy/gensdrphy.py index 174e38aeb..9fc9cce7e 100644 --- a/misoc/cores/sdram_phy/gensdrphy.py +++ b/misoc/cores/sdram_phy/gensdrphy.py @@ -23,6 +23,7 @@ from migen import * from migen.genlib.record import * +from migen.fhdl.specials import Tristate from misoc.interconnect.dfi import * from misoc.cores import sdram_settings diff --git a/misoc/integration/soc_sdram.py b/misoc/integration/soc_sdram.py index d0ee1308a..64dac5344 100644 --- a/misoc/integration/soc_sdram.py +++ b/misoc/integration/soc_sdram.py @@ -1,9 +1,9 @@ from migen import * from migen.genlib.record import * -from misoc.interconnect import wishbone, wishbone2lasmi +from misoc.interconnect import wishbone, wishbone2lasmi, lasmi_bus from misoc.interconnect.csr import AutoCSR -from misoc.cores import sdram_tester +from misoc.cores import sdram_tester, dfii, minicon, lasmicon from misoc.integration.soc_core import SoCCore # TODO: cleanup @@ -19,7 +19,7 @@ class SDRAMCore(Module, AutoCSR): self.comb += Record.connect(self.dfii.master, phy.dfi) # LASMICON - if isinstance(controller_settings, lasmicon.LASMIconSettings): + if isinstance(controller_settings, LASMIconSettings): self.submodules.controller = controller = lasmicon.LASMIcon(phy.settings, geom_settings, timing_settings, @@ -27,11 +27,11 @@ class SDRAMCore(Module, AutoCSR): **kwargs) self.comb += Record.connect(controller.dfi, self.dfii.slave) - self.submodules.crossbar = lasmixbar.LASMIxbar([controller.lasmic], + self.submodules.crossbar = lasmi_bus.LASMIxbar([controller.lasmic], controller.nrowbits) # MINICON - elif isinstance(controller_settings, minicon.MiniconSettings): + elif isinstance(controller_settings, MiniconSettings): self.submodules.controller = controller = minicon.Minicon(phy.settings, geom_settings, timing_settings) @@ -107,7 +107,7 @@ class SoCSDRAM(SoCCore): # XXX Vivado ->2015.1 workaround, Vivado is not able to map correctly our L2 cache. # Issue is reported to Xilinx and should be fixed in next releases (2015.2?). # Remove this workaround when fixed by Xilinx. - from mibuild.xilinx.vivado import XilinxVivadoToolchain + from migen.build.xilinx.vivado import XilinxVivadoToolchain if isinstance(self.platform.toolchain, XilinxVivadoToolchain): from migen.fhdl.simplify import FullMemoryWE self.submodules.l2_cache = FullMemoryWE()(l2_cache) @@ -122,7 +122,7 @@ class SoCSDRAM(SoCCore): # XXX Vivado ->2015.1 workaround, Vivado is not able to map correctly our L2 cache. # Issue is reported to Xilinx and should be fixed in next releases (2015.2?). # Remove this workaround when fixed by Xilinx. - from mibuild.xilinx.vivado import XilinxVivadoToolchain + from migen.build.xilinx.vivado import XilinxVivadoToolchain if isinstance(self.platform.toolchain, XilinxVivadoToolchain): from migen.fhdl.simplify import FullMemoryWE self.submodules.l2_cache = FullMemoryWE()(l2_cache)