diff --git a/migen/fhdl/structure.py b/migen/fhdl/structure.py
index 04bcdae7e..791d47f55 100644
--- a/migen/fhdl/structure.py
+++ b/migen/fhdl/structure.py
@@ -335,6 +335,8 @@ class Memory(HUID):
 	def get_port(self, write_capable=False, async_read=False,
 	  has_re=False, we_granularity=0, mode=WRITE_FIRST,
 	  clock_domain="sys"):
+		if we_granularity >= self.width:
+			we_granularity = 0
 		adr = Signal(BV(bits_for(self.depth-1)))
 		dat_r = Signal(BV(self.width))
 		if write_capable: