From 282ae9635465fca96f0c85da3eaa9a6f29197350 Mon Sep 17 00:00:00 2001
From: Florent Kermarrec <florent@enjoy-digital.fr>
Date: Fri, 5 Jul 2019 19:38:58 +0200
Subject: [PATCH] cores: add simple PWM (Pulse Width Modulation) module

---
 litex/soc/cores/pwm.py | 57 ++++++++++++++++++++++++++++++++++++++++++
 1 file changed, 57 insertions(+)
 create mode 100644 litex/soc/cores/pwm.py

diff --git a/litex/soc/cores/pwm.py b/litex/soc/cores/pwm.py
new file mode 100644
index 000000000..6c3697117
--- /dev/null
+++ b/litex/soc/cores/pwm.py
@@ -0,0 +1,57 @@
+# This file is Copyright (c) 2015 Florent Kermarrec <florent@enjoy-digital.fr>
+# License: BSD
+
+from migen import *
+from migen.genlib.cdc import MultiReg
+
+from litex.soc.interconnect.csr import *
+
+# Pulse Width Modulation ---------------------------------------------------------------------------
+
+class PWM(Module, AutoCSR):
+    """Pulse Width Modulation
+
+    Provides the minimal hardware to do Pulse Width Modulation.
+
+    Pulse Width Modulation can be useful for various purposes: dim leds, regulate a fan, control
+    an oscillator. Software can configure the PWM width and period and enable/disable it.
+    """
+    def __init__(self, pwm=None, clock_domain="sys"):
+        if pwm is None:
+            self.pwm = pwm = Signal()
+        self._enable = CSRStorage(reset=1)
+        self._width  = CSRStorage(32, reset=2**19)
+        self._period = CSRStorage(32, reset=2**20)
+
+        # # #
+
+        counter = Signal(32)
+        enable  = Signal()
+        width   = Signal(32)
+        period  = Signal(32)
+
+        # Resynchronize to clock_domain ------------------------------------------------------------
+        self.specials += [
+            MultiReg(self._enable.storage, enable, clock_domain),
+            MultiReg(self._width.storage,  width,  clock_domain),
+            MultiReg(self._period.storage, period, clock_domain),
+        ]
+
+        # PWM generation  --------------------------------------------------------------------------
+        sync = getattr(self.sync, clock_domain)
+        sync += \
+            If(enable,
+                If(counter < width,
+                    pwm.eq(1)
+                ).Else(
+                    pwm.eq(0)
+                ),
+                If(counter == period-1,
+                    counter.eq(0)
+                ).Else(
+                    counter.eq(counter+1)
+                )
+            ).Else(
+                counter.eq(0),
+                pwm.eq(0)
+            )