From 282f22f09ee4796d5600787d55faea4cc9e16815 Mon Sep 17 00:00:00 2001 From: bunnie Date: Wed, 27 Dec 2017 22:40:39 +0800 Subject: [PATCH] Add tracelength report generation by default to help with board layout --- litex/build/xilinx/vivado.py | 1 + 1 file changed, 1 insertion(+) diff --git a/litex/build/xilinx/vivado.py b/litex/build/xilinx/vivado.py index b94b7b52a..b626328ed 100644 --- a/litex/build/xilinx/vivado.py +++ b/litex/build/xilinx/vivado.py @@ -119,6 +119,7 @@ class XilinxVivadoToolchain: tcl.append("report_utilization -hierarchical -file {}_utilization_hierarchical_place.rpt".format(build_name)) tcl.append("report_utilization -file {}_utilization_place.rpt".format(build_name)) tcl.append("report_io -file {}_io.rpt".format(build_name)) + tcl.append("write_csv -force {}_tracelength.csv".format(build_name)) tcl.append("report_control_sets -verbose -file {}_control_sets.rpt".format(build_name)) tcl.append("report_clock_utilization -file {}_clock_utilization.rpt".format(build_name)) tcl.append("route_design")