From 284b16e2c10ad631ec0f8692e628a1c3ec1b4a78 Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Sun, 3 Dec 2017 23:06:22 +0100 Subject: [PATCH] soc/integration/soc_core: make nmi interrupt optional --- litex/soc/integration/soc_core.py | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/litex/soc/integration/soc_core.py b/litex/soc/integration/soc_core.py index 512d105ca..1e050c0fc 100644 --- a/litex/soc/integration/soc_core.py +++ b/litex/soc/integration/soc_core.py @@ -50,7 +50,6 @@ class SoCCore(Module): } interrupt_map = {} soc_interrupt_map = { - "nmi": 0, # Reserve zero for "non-maskable interrupt" "timer0": 1, # LiteX Timer "uart": 2, # LiteX UART (IRQ 2 for UART matches mor1k standard config). } @@ -69,6 +68,7 @@ class SoCCore(Module): csr_data_width=8, csr_address_width=14, with_uart=True, uart_baudrate=115200, uart_stub=False, ident="", ident_version=False, + reserve_nmi_interrupt=True, with_timer=True): self.config = dict() @@ -132,6 +132,9 @@ class SoCCore(Module): self.add_constant("CSR_DATA_WIDTH", csr_data_width) self.register_mem("csr", self.mem_map["csr"], self.wishbone2csr.wishbone) + if reserve_nmi_interrupt: + self.soc_interrupt_map["nmi"] = 0 # Reserve zero for "non-maskable interrupt" + if with_uart: if uart_stub: self.submodules.uart = uart.UARTStub()