From 2886fe170160d8481b77a53c11132d881b7bfa48 Mon Sep 17 00:00:00 2001 From: Navaneeth Bhardwaj Date: Sun, 24 Oct 2021 15:38:58 +0530 Subject: [PATCH] Add bios test mode for CI (#1076) * Add bios test mode for CI This enables to test the booting of each CPU configurations with the bios in Verilator simulation. --- .github/workflows/ci.yml | 7 ++++- test/test_boot.py | 60 ++++++++++++++++++++++++++++++++++++++++ 2 files changed, 66 insertions(+), 1 deletion(-) create mode 100644 test/test_boot.py diff --git a/.github/workflows/ci.yml b/.github/workflows/ci.yml index 46c49a3f6..176ebf7ec 100644 --- a/.github/workflows/ci.yml +++ b/.github/workflows/ci.yml @@ -3,7 +3,7 @@ name: ci on: [push, pull_request] jobs: - build: + regression-test: runs-on: ubuntu-18.04 steps: # Checkout Repository @@ -14,9 +14,13 @@ jobs: - name: Install Tools run: | sudo apt-get install wget build-essential python3 + sudo apt-get install verilator libevent-dev libjson-c-dev pip3 install setuptools pip3 install requests pip3 install meson + pip3 install ninja + pip3 install nmigen-yosys + pip3 install pexpect # Install (n)Migen / LiteX / Cores - name: Install LiteX @@ -41,4 +45,5 @@ jobs: - name: Run Tests run: | export GITHUB_ACTIONS=1 + export PATH=$PATH:$(echo $PWD/../riscv64-*/bin/) python3 setup.py test diff --git a/test/test_boot.py b/test/test_boot.py new file mode 100644 index 000000000..9588c43a7 --- /dev/null +++ b/test/test_boot.py @@ -0,0 +1,60 @@ +# +# This file is part of LiteX. +# +# Copyright (c) 2021 Navaneeth Bhardwaj +# SPDX-License-Identifier: BSD-2-Clause + +import unittest +import pexpect +import sys + +class TestCPU(unittest.TestCase): + def boot_test(self, cpu_type): + cmd = f'lxsim --cpu-type={cpu_type}' + litex_prompt = [b'\033\[[0-9;]+mlitex\033\[[0-9;]+m>'] + is_success = True + with open("/tmp/test_boot_log", "wb") as result_file: + p = pexpect.spawn(cmd, timeout=None, logfile=result_file) + try: + match_id = p.expect(litex_prompt, timeout=1200) + except pexpect.EOF: + print('\n*** Premature termination') + is_success = False + except pexpect.TIMEOUT: + print('\n*** Timeout ') + is_success = False + + if not is_success: + print(f'*** {cpu_type} Boot Failure') + with open("/tmp/test_boot_log", "r") as result_file: + print(result_file.read()) + else: + p.terminate(force=True) + print(f'*** {cpu_type} Boot Success') + + return is_success + + def test_vexriscv(self): + self.assertTrue(self.boot_test("vexriscv")) + + def test_vexriscv_smp(self): + self.assertTrue(self.boot_test("vexriscv_smp")) + + def test_cv32e40p(self): + self.assertTrue(self.boot_test("cv32e40p")) + + def test_ibex(self): + self.assertTrue(self.boot_test("ibex")) + + def test_serv(self): + self.assertTrue(self.boot_test("serv")) + + def test_femtorv(self): + self.assertTrue(self.boot_test("femtorv")) + + def test_picorv32(self): + self.assertTrue(self.boot_test("picorv32")) + + def test_minerva(self): + self.assertTrue(self.boot_test("minerva")) +