From 28d4aff10f09b0835297f4bf3d26364dcc8850f3 Mon Sep 17 00:00:00 2001 From: Dolu1990 Date: Thu, 13 Jun 2024 23:20:25 +0200 Subject: [PATCH] vexii non coherent config write bandwidth improvment --- litex/soc/cores/cpu/vexiiriscv/core.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/litex/soc/cores/cpu/vexiiriscv/core.py b/litex/soc/cores/cpu/vexiiriscv/core.py index 1a1b37cc1..297e8362b 100755 --- a/litex/soc/cores/cpu/vexiiriscv/core.py +++ b/litex/soc/cores/cpu/vexiiriscv/core.py @@ -148,7 +148,7 @@ class VexiiRiscv(CPU): vdir = get_data_mod("cpu", "vexiiriscv").data_location ndir = os.path.join(vdir, "ext", "VexiiRiscv") - NaxRiscv.git_setup("VexiiRiscv", ndir, "https://github.com/SpinalHDL/VexiiRiscv.git", "dev", "66974d1e", args.update_repo) + NaxRiscv.git_setup("VexiiRiscv", ndir, "https://github.com/SpinalHDL/VexiiRiscv.git", "dev", "e991b315", args.update_repo) if not args.cpu_variant: args.cpu_variant = "standard"