From 296688b2d8720d0cedfb4974d5b13c268c38273c Mon Sep 17 00:00:00 2001
From: Florent Kermarrec <florent@enjoy-digital.fr>
Date: Wed, 27 Oct 2021 11:01:09 +0200
Subject: [PATCH] cores/jtag/ECP5JTAG: Fix LUT4's INIT to create a buffer
 instead of inverter, thanks @gregdavill.

Avoid restriction to even number for tck_delay_luts.
---
 litex/soc/cores/jtag.py | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/litex/soc/cores/jtag.py b/litex/soc/cores/jtag.py
index e12de1ec9..a585cea9a 100644
--- a/litex/soc/cores/jtag.py
+++ b/litex/soc/cores/jtag.py
@@ -128,7 +128,7 @@ class ECP5JTAG(Module):
             new_tck = Signal()
             self.specials += Instance("LUT4",
                 attr   = {"keep"},
-                p_INIT = 1,
+                p_INIT = 2,
                 i_A = tck,
                 i_B = 0,
                 i_C = 0,