From 29f7b94e37cc4fb0affe62258efe10d3ceb1db29 Mon Sep 17 00:00:00 2001 From: Sebastien Bourdeauducq Date: Sun, 24 Nov 2013 23:43:14 +0100 Subject: [PATCH] bus/wishbone/sram: expose memory component --- migen/bus/wishbone.py | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/migen/bus/wishbone.py b/migen/bus/wishbone.py index fec23a18d..6dd2a0664 100644 --- a/migen/bus/wishbone.py +++ b/migen/bus/wishbone.py @@ -288,20 +288,20 @@ class SRAM(Module): bus_data_width = flen(self.bus.dat_r) if isinstance(mem_or_size, Memory): assert(mem_or_size.width <= bus_data_width) - mem = mem_or_size + self.mem = mem_or_size else: - mem = Memory(bus_data_width, mem_or_size//(bus_data_width//8), init=init) + self.mem = Memory(bus_data_width, mem_or_size//(bus_data_width//8), init=init) if read_only is None: - if hasattr(mem, "bus_read_only"): - read_only = mem.bus_read_only + if hasattr(self.mem, "bus_read_only"): + read_only = self.mem.bus_read_only else: read_only = False ### # memory - port = mem.get_port(write_capable=not read_only, we_granularity=8) - self.specials += mem, port + port = self.mem.get_port(write_capable=not read_only, we_granularity=8) + self.specials += self.mem, port # generate write enable signal if not read_only: self.comb += [port.we[i].eq(self.bus.cyc & self.bus.stb & self.bus.we & self.bus.sel[i])