From 2a15ab554a44c144e9ea907614d35844c9a65747 Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Wed, 19 Oct 2022 10:53:26 +0200 Subject: [PATCH] cores/spi/spi_bone: Remove some duplicated code between 2 and 3 wires cases. --- litex/soc/cores/spi/spi_bone.py | 15 +++++---------- 1 file changed, 5 insertions(+), 10 deletions(-) diff --git a/litex/soc/cores/spi/spi_bone.py b/litex/soc/cores/spi/spi_bone.py index 75eb39e3b..687c68193 100644 --- a/litex/soc/cores/spi/spi_bone.py +++ b/litex/soc/cores/spi/spi_bone.py @@ -167,21 +167,16 @@ class SPIBone(Module, ModuleDoc, AutoDoc): sync_byte = Signal(8) self.specials += MultiReg(pads.clk, clk) - if wires == 2: + if wires in [2, 3]: io = TSTriple() self.specials += io.get_tristate(pads.mosi) self.specials += MultiReg(io.i, mosi) self.comb += io.o.eq(miso) self.comb += io.oe.eq(miso_en) - if wires == 3: - self.specials += MultiReg(pads.cs_n, cs_n), - io = TSTriple() - self.specials += io.get_tristate(pads.mosi) - self.specials += MultiReg(io.i, mosi) - self.comb += io.o.eq(miso) - self.comb += io.oe.eq(miso_en) - if wires == 4: - self.specials += MultiReg(pads.cs_n, cs_n), + if wires == 2: + self.specials += MultiReg(pads.cs_n, cs_n) + if wires in [4]: + self.specials += MultiReg(pads.cs_n, cs_n) self.specials += MultiReg(pads.mosi, mosi) if with_tristate: self.specials += Tristate(pads.miso, miso, ~cs_n)