From 682e4e0b7d9629974307d04df028e5fc8b2ee05f Mon Sep 17 00:00:00 2001 From: Ilia Sergachev Date: Wed, 19 Jan 2022 02:46:49 +0100 Subject: [PATCH 1/3] cpu/zynq7000: add boot helper --- litex/soc/cores/cpu/zynq7000/boot-helper.S | 3 --- litex/soc/cores/cpu/zynq7000/boot-helper.c | 5 +++++ 2 files changed, 5 insertions(+), 3 deletions(-) delete mode 100644 litex/soc/cores/cpu/zynq7000/boot-helper.S create mode 100644 litex/soc/cores/cpu/zynq7000/boot-helper.c diff --git a/litex/soc/cores/cpu/zynq7000/boot-helper.S b/litex/soc/cores/cpu/zynq7000/boot-helper.S deleted file mode 100644 index 4a0248f93..000000000 --- a/litex/soc/cores/cpu/zynq7000/boot-helper.S +++ /dev/null @@ -1,3 +0,0 @@ -.global boot_helper -boot_helper: - nop // FIXME diff --git a/litex/soc/cores/cpu/zynq7000/boot-helper.c b/litex/soc/cores/cpu/zynq7000/boot-helper.c new file mode 100644 index 000000000..4dd8ae2d3 --- /dev/null +++ b/litex/soc/cores/cpu/zynq7000/boot-helper.c @@ -0,0 +1,5 @@ +void boot_helper(unsigned long r1, unsigned long r2, unsigned long r3, unsigned long addr); + +void boot_helper(unsigned long r1, unsigned long r2, unsigned long r3, unsigned long addr) { + goto *addr; +} From 2bc1c3ac9907c1d8913fec7894334028848456cf Mon Sep 17 00:00:00 2001 From: Ilia Sergachev Date: Wed, 19 Jan 2022 02:47:18 +0100 Subject: [PATCH 2/3] cpu/zynq7000: enable software compilation --- litex/soc/integration/soc.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/litex/soc/integration/soc.py b/litex/soc/integration/soc.py index b5034d0ff..46f2c87ac 100644 --- a/litex/soc/integration/soc.py +++ b/litex/soc/integration/soc.py @@ -935,7 +935,7 @@ class SoC(Module): self.mem_map.update(self.cpu.mem_map) # Add Bus Masters/CSR/IRQs. - if not isinstance(self.cpu, (cpu.CPUNone, cpu.Zynq7000)): + if not isinstance(self.cpu, cpu.CPUNone): if hasattr(self.cpu, "set_reset_address"): if reset_address is None: reset_address = self.mem_map["rom"] From 6a395fa49263c0a78e2a907a9c2835d7f7cd4153 Mon Sep 17 00:00:00 2001 From: Ilia Sergachev Date: Wed, 19 Jan 2022 02:48:13 +0100 Subject: [PATCH 3/3] cpu/zynq7000: correct address map --- litex/soc/cores/cpu/zynq7000/core.py | 9 ++++++--- 1 file changed, 6 insertions(+), 3 deletions(-) diff --git a/litex/soc/cores/cpu/zynq7000/core.py b/litex/soc/cores/cpu/zynq7000/core.py index 309733de3..f5295e32f 100644 --- a/litex/soc/cores/cpu/zynq7000/core.py +++ b/litex/soc/cores/cpu/zynq7000/core.py @@ -23,17 +23,20 @@ class Zynq7000(CPU): human_name = "Zynq7000" data_width = 32 endianness = "little" - reset_address = 0x00000000 + reset_address = 0xfc00_0000 gcc_triple = "arm-none-eabi" gcc_flags = "-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard" linker_output_format = "elf32-littlearm" nop = "nop" - io_regions = {0x00000000: 0x100000000} # Origin, Length. + io_regions = {0x4000_0000: 0xbc00_0000} # Origin, Length. # Memory Mapping. @property def mem_map(self): - return {"csr": 0x00000000} + return { + "sram": 0x10_0000, # DDR in fact + "rom": 0xfc00_0000, + } def __init__(self, platform, variant, *args, **kwargs): super().__init__(*args, **kwargs)