From d5a21a7522daf4978c344490983157efd65b3a2e Mon Sep 17 00:00:00 2001
From: Tim 'mithro' Ansell <me@mith.ro>
Date: Sun, 23 Feb 2020 06:54:48 -0800
Subject: [PATCH 01/95] Converting litex to use Python modules.

---
 litex/data/__init__.py                  |  2 ++
 litex/data/find.py                      | 13 +++++++++++++
 litex/soc/cores/cpu/blackparrot/core.py |  3 ++-
 litex/soc/cores/cpu/lm32/core.py        |  8 ++++----
 litex/soc/cores/cpu/microwatt/core.py   |  3 ++-
 litex/soc/cores/cpu/mor1kx/core.py      |  1 +
 litex/soc/cores/cpu/picorv32/core.py    |  4 ++--
 litex/soc/cores/cpu/rocket/core.py      |  4 ++--
 litex/soc/cores/cpu/vexriscv/core.py    |  3 ++-
 litex_setup.py                          | 12 +++++++++++-
 10 files changed, 41 insertions(+), 12 deletions(-)
 create mode 100644 litex/data/__init__.py
 create mode 100644 litex/data/find.py

diff --git a/litex/data/__init__.py b/litex/data/__init__.py
new file mode 100644
index 000000000..c9b5ae908
--- /dev/null
+++ b/litex/data/__init__.py
@@ -0,0 +1,2 @@
+# https://packaging.python.org/guides/packaging-namespace-packages/#pkgutil-style-namespace-packages
+__path__ = __import__('pkgutil').extend_path(__path__, __name__)
diff --git a/litex/data/find.py b/litex/data/find.py
new file mode 100644
index 000000000..da7ed9819
--- /dev/null
+++ b/litex/data/find.py
@@ -0,0 +1,13 @@
+def find_data(data_type, data_name):
+    imp = "from litex.data.{} import {} as dm".format(data_type, data_name)
+    try:
+        exec(imp)
+        return dm.data_location
+    except ImportError as e:
+        raise ImportError("""\
+litex-data-{dt}-{dn} module not install! Unable to use {dn} {dt}.
+{e}
+
+You can install this by running;
+ pip install git+https://github.com/litex-hub/litex-data-{dt}-{dn}.git
+""".format(dt=data_type, dn=data_name, e=e))
diff --git a/litex/soc/cores/cpu/blackparrot/core.py b/litex/soc/cores/cpu/blackparrot/core.py
index 897664892..e55e6252b 100644
--- a/litex/soc/cores/cpu/blackparrot/core.py
+++ b/litex/soc/cores/cpu/blackparrot/core.py
@@ -32,6 +32,7 @@ import os
 
 from migen import *
 
+from litex.data.find import find_data
 from litex.soc.interconnect import axi
 from litex.soc.interconnect import wishbone
 from litex.soc.cores.cpu import CPU
@@ -115,7 +116,7 @@ class BlackParrotRV64(CPU):
 
     @staticmethod
     def add_sources(platform, variant="standard"):
-        filename = os.path.join(os.path.abspath(os.path.dirname(__file__)), "flist_litex.verilator")
+        filename = os.path.join(find_data("cpu", "blackparrot"), "flist_litex.verilator")
         with open(filename) as openfileobject:
             for line in openfileobject:
                 temp = line
diff --git a/litex/soc/cores/cpu/lm32/core.py b/litex/soc/cores/cpu/lm32/core.py
index 9ef8333b9..75e7ba8cb 100644
--- a/litex/soc/cores/cpu/lm32/core.py
+++ b/litex/soc/cores/cpu/lm32/core.py
@@ -9,6 +9,7 @@ import os
 
 from migen import *
 
+from litex.data.find import find_data
 from litex.soc.interconnect import wishbone
 from litex.soc.cores.cpu import CPU
 
@@ -96,9 +97,8 @@ class LM32(CPU):
 
     @staticmethod
     def add_sources(platform, variant):
-        vdir = os.path.join(
-            os.path.abspath(os.path.dirname(__file__)), "verilog")
-        platform.add_sources(os.path.join(vdir, "submodule", "rtl"),
+        vdir = find_data("cpu", "lm32")
+        platform.add_sources(os.path.join(vdir, "rtl"),
             "lm32_cpu.v",
             "lm32_instruction_unit.v",
             "lm32_decoder.v",
@@ -117,7 +117,7 @@ class LM32(CPU):
             "lm32_debug.v",
             "lm32_itlb.v",
             "lm32_dtlb.v")
-        platform.add_verilog_include_path(os.path.join(vdir, "submodule", "rtl"))
+        platform.add_verilog_include_path(os.path.join(vdir, "rtl"))
         if variant == "minimal":
             platform.add_verilog_include_path(os.path.join(vdir, "config_minimal"))
         elif variant == "lite":
diff --git a/litex/soc/cores/cpu/microwatt/core.py b/litex/soc/cores/cpu/microwatt/core.py
index 584ad4450..aa00ee172 100644
--- a/litex/soc/cores/cpu/microwatt/core.py
+++ b/litex/soc/cores/cpu/microwatt/core.py
@@ -6,6 +6,7 @@ import os
 
 from migen import *
 
+from litex.data.find import find_data
 from litex.soc.interconnect import wishbone
 from litex.soc.cores.cpu import CPU
 
@@ -98,7 +99,7 @@ class Microwatt(CPU):
 
     @staticmethod
     def add_sources(platform):
-        sdir = os.path.join(os.path.abspath(os.path.dirname(__file__)), "sources")
+        sdir = os.path.join(find_data("cpu", "microwatt"), "sources")
         platform.add_sources(sdir,
             # Common / Types / Helpers
             "decode_types.vhdl",
diff --git a/litex/soc/cores/cpu/mor1kx/core.py b/litex/soc/cores/cpu/mor1kx/core.py
index c82b6e55d..4fe41b36c 100644
--- a/litex/soc/cores/cpu/mor1kx/core.py
+++ b/litex/soc/cores/cpu/mor1kx/core.py
@@ -8,6 +8,7 @@ import os
 
 from migen import *
 
+from litex.data.find import find_data
 from litex.soc.interconnect import wishbone
 from litex.soc.cores.cpu import CPU
 
diff --git a/litex/soc/cores/cpu/picorv32/core.py b/litex/soc/cores/cpu/picorv32/core.py
index 304f6c14d..47017ac6b 100644
--- a/litex/soc/cores/cpu/picorv32/core.py
+++ b/litex/soc/cores/cpu/picorv32/core.py
@@ -11,6 +11,7 @@ import os
 
 from migen import *
 
+from litex.data.find import find_data
 from litex.soc.interconnect import wishbone
 from litex.soc.cores.cpu import CPU
 
@@ -179,8 +180,7 @@ class PicoRV32(CPU):
 
     @staticmethod
     def add_sources(platform):
-        vdir = os.path.join(
-            os.path.abspath(os.path.dirname(__file__)), "verilog")
+        vdir = find_data("cpu", "picorv32")
         platform.add_source(os.path.join(vdir, "picorv32.v"))
 
     def do_finalize(self):
diff --git a/litex/soc/cores/cpu/rocket/core.py b/litex/soc/cores/cpu/rocket/core.py
index 14bab0f41..dff3fe707 100644
--- a/litex/soc/cores/cpu/rocket/core.py
+++ b/litex/soc/cores/cpu/rocket/core.py
@@ -33,6 +33,7 @@ import os
 
 from migen import *
 
+from litex.data.find import find_data
 from litex.soc.interconnect import axi
 from litex.soc.interconnect import wishbone
 from litex.soc.cores.cpu import CPU
@@ -238,8 +239,7 @@ class RocketRV64(CPU):
 
     @staticmethod
     def add_sources(platform, variant="standard"):
-        vdir = os.path.join(
-            os.path.abspath(os.path.dirname(__file__)), "verilog")
+        vdir = find_data("cpu", "rocket")
         platform.add_sources(
             os.path.join(vdir, "generated-src"),
             CPU_VARIANTS[variant] + ".v",
diff --git a/litex/soc/cores/cpu/vexriscv/core.py b/litex/soc/cores/cpu/vexriscv/core.py
index 4e0bbc0a0..42328d199 100644
--- a/litex/soc/cores/cpu/vexriscv/core.py
+++ b/litex/soc/cores/cpu/vexriscv/core.py
@@ -12,6 +12,7 @@ import os
 
 from migen import *
 
+from litex.data.find import find_data
 from litex.soc.interconnect import wishbone
 from litex.soc.interconnect.csr import *
 from litex.soc.cores.cpu import CPU
@@ -246,7 +247,7 @@ class VexRiscv(CPU, AutoCSR):
     @staticmethod
     def add_sources(platform, variant="standard"):
         cpu_filename = CPU_VARIANTS[variant] + ".v"
-        vdir = os.path.join(os.path.abspath(os.path.dirname(__file__)), "verilog")
+        vdir = find_data("cpu", "vexriscv")
         platform.add_source(os.path.join(vdir, cpu_filename))
 
     def use_external_variant(self, variant_filename):
diff --git a/litex_setup.py b/litex_setup.py
index 60582955e..ca1d4f49e 100755
--- a/litex_setup.py
+++ b/litex_setup.py
@@ -18,7 +18,8 @@ repos = [
     ("migen",        ("https://github.com/m-labs/",        True,  True)),
 
     # LiteX SoC builder
-    ("litex",        ("https://github.com/enjoy-digital/", True,  True)),
+    ('litex-data-software-compiler_rt', ("https://github.com/litex-hub/", False, True))
+    ("litex",        ("https://github.com/enjoy-digital/", False,  True)),
 
     # LiteX cores ecosystem
     ("liteeth",      ("https://github.com/enjoy-digital/", False, True)),
@@ -34,6 +35,15 @@ repos = [
 
     # LiteX boards support
     ("litex-boards", ("https://github.com/litex-hub/",     False, True)),
+
+    # Optional LiteX data
+    ('litex-data-cpu-blackparrot', ("https://github.com/litex-hub/", False, True))
+    ('litex-data-cpu-mor1kx',      ("https://github.com/litex-hub/", False, True))
+    ('litex-data-cpu-lm32',        ("https://github.com/litex-hub/", False, True))
+    ('litex-data-cpu-microwatt',   ("https://github.com/litex-hub/", False, True))
+    ('litex-data-cpu-picorv32',    ("https://github.com/litex-hub/", False, True))
+    ('litex-data-cpu-rocket',      ("https://github.com/litex-hub/", False, True))
+    ('litex-data-misc-tapcfg',     ("https://github.com/litex-hub/", False, True))
 ]
 repos = OrderedDict(repos)
 

From 3964565e1572a859be55da17599d0f1b6edba2a0 Mon Sep 17 00:00:00 2001
From: Tim 'mithro' Ansell <me@mith.ro>
Date: Sun, 23 Feb 2020 13:38:05 -0800
Subject: [PATCH 02/95] Fixed quotes in `litex_setup.py`

---
 litex_setup.py | 14 +++++++-------
 1 file changed, 7 insertions(+), 7 deletions(-)

diff --git a/litex_setup.py b/litex_setup.py
index ca1d4f49e..9de1e7494 100755
--- a/litex_setup.py
+++ b/litex_setup.py
@@ -37,13 +37,13 @@ repos = [
     ("litex-boards", ("https://github.com/litex-hub/",     False, True)),
 
     # Optional LiteX data
-    ('litex-data-cpu-blackparrot', ("https://github.com/litex-hub/", False, True))
-    ('litex-data-cpu-mor1kx',      ("https://github.com/litex-hub/", False, True))
-    ('litex-data-cpu-lm32',        ("https://github.com/litex-hub/", False, True))
-    ('litex-data-cpu-microwatt',   ("https://github.com/litex-hub/", False, True))
-    ('litex-data-cpu-picorv32',    ("https://github.com/litex-hub/", False, True))
-    ('litex-data-cpu-rocket',      ("https://github.com/litex-hub/", False, True))
-    ('litex-data-misc-tapcfg',     ("https://github.com/litex-hub/", False, True))
+    ("litex-data-cpu-blackparrot", ("https://github.com/litex-hub/", False, True))
+    ("litex-data-cpu-mor1kx",      ("https://github.com/litex-hub/", False, True))
+    ("litex-data-cpu-lm32",        ("https://github.com/litex-hub/", False, True))
+    ("litex-data-cpu-microwatt",   ("https://github.com/litex-hub/", False, True))
+    ("litex-data-cpu-picorv32",    ("https://github.com/litex-hub/", False, True))
+    ("litex-data-cpu-rocket",      ("https://github.com/litex-hub/", False, True))
+    ("litex-data-misc-tapcfg",     ("https://github.com/litex-hub/", False, True))
 ]
 repos = OrderedDict(repos)
 

From 3df6c0c8a21e7ff62724b444f19372970940a619 Mon Sep 17 00:00:00 2001
From: Tim 'mithro' Ansell <me@mith.ro>
Date: Sun, 23 Feb 2020 13:39:45 -0800
Subject: [PATCH 03/95] Adding litex-data-software-compiler_rt as a required
 package.

---
 setup.py | 13 ++++++++++++-
 1 file changed, 12 insertions(+), 1 deletion(-)

diff --git a/setup.py b/setup.py
index 46f8b6eeb..84824a9ad 100755
--- a/setup.py
+++ b/setup.py
@@ -14,9 +14,20 @@ setup(
     test_suite="test",
     license="BSD",
     python_requires="~=3.6",
-    install_requires=["migen", "pyserial"],
+    install_requires=["migen", "pyserial", "litex-data-software-compiler_rt"],
     packages=find_packages(exclude=("test*", "sim*", "doc*")),
     include_package_data=True,
+    platforms=["Any"],
+    keywords="HDL ASIC FPGA hardware design",
+    classifiers=[
+        "Topic :: Scientific/Engineering :: Electronic Design Automation (EDA)",
+        "Environment :: Console",
+        "Development Status :: Alpha",
+        "Intended Audience :: Developers",
+        "License :: OSI Approved :: BSD License",
+        "Operating System :: OS Independent",
+        "Programming Language :: Python",
+    ],
     entry_points={
         "console_scripts": [
             # full names

From ac3fd794f922061653ace78c59fdeccb4327e178 Mon Sep 17 00:00:00 2001
From: Tim 'mithro' Ansell <me@mith.ro>
Date: Sun, 23 Feb 2020 14:19:12 -0800
Subject: [PATCH 04/95] Adding missing comma.

---
 litex_setup.py | 16 ++++++++--------
 setup.py       |  6 +++++-
 2 files changed, 13 insertions(+), 9 deletions(-)

diff --git a/litex_setup.py b/litex_setup.py
index 9de1e7494..ffd8fd76f 100755
--- a/litex_setup.py
+++ b/litex_setup.py
@@ -18,7 +18,7 @@ repos = [
     ("migen",        ("https://github.com/m-labs/",        True,  True)),
 
     # LiteX SoC builder
-    ('litex-data-software-compiler_rt', ("https://github.com/litex-hub/", False, True))
+    ('litex-data-software-compiler_rt', ("https://github.com/litex-hub/", False, True)),
     ("litex",        ("https://github.com/enjoy-digital/", False,  True)),
 
     # LiteX cores ecosystem
@@ -37,13 +37,13 @@ repos = [
     ("litex-boards", ("https://github.com/litex-hub/",     False, True)),
 
     # Optional LiteX data
-    ("litex-data-cpu-blackparrot", ("https://github.com/litex-hub/", False, True))
-    ("litex-data-cpu-mor1kx",      ("https://github.com/litex-hub/", False, True))
-    ("litex-data-cpu-lm32",        ("https://github.com/litex-hub/", False, True))
-    ("litex-data-cpu-microwatt",   ("https://github.com/litex-hub/", False, True))
-    ("litex-data-cpu-picorv32",    ("https://github.com/litex-hub/", False, True))
-    ("litex-data-cpu-rocket",      ("https://github.com/litex-hub/", False, True))
-    ("litex-data-misc-tapcfg",     ("https://github.com/litex-hub/", False, True))
+    ("litex-data-cpu-blackparrot", ("https://github.com/litex-hub/", False, True)),
+    ("litex-data-cpu-mor1kx",      ("https://github.com/litex-hub/", False, True)),
+    ("litex-data-cpu-lm32",        ("https://github.com/litex-hub/", False, True)),
+    ("litex-data-cpu-microwatt",   ("https://github.com/litex-hub/", False, True)),
+    ("litex-data-cpu-picorv32",    ("https://github.com/litex-hub/", False, True)),
+    ("litex-data-cpu-rocket",      ("https://github.com/litex-hub/", False, True)),
+    ("litex-data-misc-tapcfg",     ("https://github.com/litex-hub/", False, True)),
 ]
 repos = OrderedDict(repos)
 
diff --git a/setup.py b/setup.py
index 84824a9ad..9c7444270 100755
--- a/setup.py
+++ b/setup.py
@@ -14,7 +14,11 @@ setup(
     test_suite="test",
     license="BSD",
     python_requires="~=3.6",
-    install_requires=["migen", "pyserial", "litex-data-software-compiler_rt"],
+    install_requires=[
+        "migen",
+        "pyserial",
+        "litex-data-software-compiler_rt",
+    ],
     packages=find_packages(exclude=("test*", "sim*", "doc*")),
     include_package_data=True,
     platforms=["Any"],

From 3ae4f8f2de7494411e5278b11dd7db1c0ae7389f Mon Sep 17 00:00:00 2001
From: Tim 'mithro' Ansell <me@mith.ro>
Date: Sun, 23 Feb 2020 14:54:07 -0800
Subject: [PATCH 05/95] Adding missing vexriscv CPU.

---
 litex_setup.py | 1 +
 1 file changed, 1 insertion(+)

diff --git a/litex_setup.py b/litex_setup.py
index ffd8fd76f..ff2777bfa 100755
--- a/litex_setup.py
+++ b/litex_setup.py
@@ -43,6 +43,7 @@ repos = [
     ("litex-data-cpu-microwatt",   ("https://github.com/litex-hub/", False, True)),
     ("litex-data-cpu-picorv32",    ("https://github.com/litex-hub/", False, True)),
     ("litex-data-cpu-rocket",      ("https://github.com/litex-hub/", False, True)),
+    ("litex-data-cpu-vexriscv",    ("https://github.com/litex-hub/", False, True)),
     ("litex-data-misc-tapcfg",     ("https://github.com/litex-hub/", False, True)),
 ]
 repos = OrderedDict(repos)

From 69367f8d4efd07a9aae3e877746939a16e805127 Mon Sep 17 00:00:00 2001
From: Tim 'mithro' Ansell <me@mith.ro>
Date: Sun, 23 Feb 2020 14:56:51 -0800
Subject: [PATCH 06/95] Make litex a namespace.

---
 litex/__init__.py | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/litex/__init__.py b/litex/__init__.py
index ca1e6d75b..2454c0e79 100644
--- a/litex/__init__.py
+++ b/litex/__init__.py
@@ -1,3 +1,6 @@
+# https://packaging.python.org/guides/packaging-namespace-packages/#pkgutil-style-namespace-packages
+__path__ = __import__('pkgutil').extend_path(__path__, __name__)
+
 import sys
 
 # retro-compat 2019-09-30

From 119985f3532081b82796459cedb685ce9bcd8230 Mon Sep 17 00:00:00 2001
From: Tim 'mithro' Ansell <me@mith.ro>
Date: Sun, 23 Feb 2020 14:58:45 -0800
Subject: [PATCH 07/95] Use the current directory you are running.

---
 litex_setup.py | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/litex_setup.py b/litex_setup.py
index ff2777bfa..c6389ad66 100755
--- a/litex_setup.py
+++ b/litex_setup.py
@@ -8,7 +8,8 @@ from collections import OrderedDict
 
 import urllib.request
 
-current_path = os.path.dirname(os.path.realpath(__file__))
+current_path = os.path.abspath(os.curdir)
+
 
 # Repositories -------------------------------------------------------------------------------------
 

From c96d1e667277809891f0edffbf7c8ff0a3f38848 Mon Sep 17 00:00:00 2001
From: Tim 'mithro' Ansell <me@mith.ro>
Date: Sun, 23 Feb 2020 15:29:46 -0800
Subject: [PATCH 08/95] Fix import for data.

---
 litex/data/find.py | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/litex/data/find.py b/litex/data/find.py
index da7ed9819..1a143b1dc 100644
--- a/litex/data/find.py
+++ b/litex/data/find.py
@@ -1,7 +1,9 @@
 def find_data(data_type, data_name):
     imp = "from litex.data.{} import {} as dm".format(data_type, data_name)
     try:
-        exec(imp)
+        l = {}
+        exec(imp, {}, l)
+        dm = l['dm']
         return dm.data_location
     except ImportError as e:
         raise ImportError("""\

From 1c1c5bcbda88e5d3ca93e8a7de1dcb3c05b4aa8b Mon Sep 17 00:00:00 2001
From: Tim 'mithro' Ansell <me@mith.ro>
Date: Sun, 23 Feb 2020 16:06:51 -0800
Subject: [PATCH 09/95] Remove submodules.

---
 .gitmodules                                   | 30 -------------------
 litex/build/sim/core/modules/ethernet/tapcfg  |  1 -
 .../cores/cpu/blackparrot/pre-alpha-release   |  1 -
 litex/soc/cores/cpu/lm32/verilog/submodule    |  1 -
 litex/soc/cores/cpu/microwatt/sources         |  1 -
 litex/soc/cores/cpu/minerva/verilog           |  1 -
 litex/soc/cores/cpu/mor1kx/verilog            |  1 -
 litex/soc/cores/cpu/picorv32/verilog          |  1 -
 litex/soc/cores/cpu/rocket/verilog            |  1 -
 litex/soc/cores/cpu/vexriscv/verilog          |  1 -
 litex/soc/software/compiler_rt                |  1 -
 11 files changed, 40 deletions(-)
 delete mode 100644 .gitmodules
 delete mode 160000 litex/build/sim/core/modules/ethernet/tapcfg
 delete mode 160000 litex/soc/cores/cpu/blackparrot/pre-alpha-release
 delete mode 160000 litex/soc/cores/cpu/lm32/verilog/submodule
 delete mode 160000 litex/soc/cores/cpu/microwatt/sources
 delete mode 160000 litex/soc/cores/cpu/minerva/verilog
 delete mode 160000 litex/soc/cores/cpu/mor1kx/verilog
 delete mode 160000 litex/soc/cores/cpu/picorv32/verilog
 delete mode 160000 litex/soc/cores/cpu/rocket/verilog
 delete mode 160000 litex/soc/cores/cpu/vexriscv/verilog
 delete mode 160000 litex/soc/software/compiler_rt

diff --git a/.gitmodules b/.gitmodules
deleted file mode 100644
index a683f7367..000000000
--- a/.gitmodules
+++ /dev/null
@@ -1,30 +0,0 @@
-[submodule "litex/soc/cores/cpu/lm32/verilog/submodule"]
-	path = litex/soc/cores/cpu/lm32/verilog/submodule
-	url = https://github.com/m-labs/lm32.git
-[submodule "litex/soc/cores/cpu/mor1kx/verilog"]
-	path = litex/soc/cores/cpu/mor1kx/verilog
-	url = https://github.com/openrisc/mor1kx.git
-[submodule "litex/soc/software/compiler_rt"]
-	path = litex/soc/software/compiler_rt
-	url = https://github.com/llvm-mirror/compiler-rt
-[submodule "litex/soc/cores/cpu/picorv32/verilog"]
-	path = litex/soc/cores/cpu/picorv32/verilog
-	url = https://github.com/cliffordwolf/picorv32
-[submodule "litex/build/sim/core/modules/ethernet/tapcfg"]
-	path = litex/build/sim/core/modules/ethernet/tapcfg
-	url = https://github.com/enjoy-digital/tapcfg
-[submodule "litex/soc/cores/cpu/vexriscv/verilog"]
-	path = litex/soc/cores/cpu/vexriscv/verilog
-	url = https://github.com/enjoy-digital/VexRiscv-verilog.git
-[submodule "litex/soc/cores/cpu/minerva/verilog"]
-	path = litex/soc/cores/cpu/minerva/verilog
-	url = https://github.com/lambdaconcept/minerva
-[submodule "litex/soc/cores/cpu/rocket/verilog"]
-	path = litex/soc/cores/cpu/rocket/verilog
-	url = https://github.com/enjoy-digital/rocket-litex-verilog
-[submodule "litex/soc/cores/cpu/microwatt/sources"]
-	path = litex/soc/cores/cpu/microwatt/sources
-	url = https://github.com/antonblanchard/microwatt
-[submodule "litex/soc/cores/cpu/blackparrot/pre-alpha-release"]
-	path = litex/soc/cores/cpu/blackparrot/pre-alpha-release
-	url = https://github.com/enjoy-digital/black-parrot.git
diff --git a/litex/build/sim/core/modules/ethernet/tapcfg b/litex/build/sim/core/modules/ethernet/tapcfg
deleted file mode 160000
index bd557ff00..000000000
--- a/litex/build/sim/core/modules/ethernet/tapcfg
+++ /dev/null
@@ -1 +0,0 @@
-Subproject commit bd557ff00d8fe2473fcf346e36c96d004e94b8ca
diff --git a/litex/soc/cores/cpu/blackparrot/pre-alpha-release b/litex/soc/cores/cpu/blackparrot/pre-alpha-release
deleted file mode 160000
index dbb13f313..000000000
--- a/litex/soc/cores/cpu/blackparrot/pre-alpha-release
+++ /dev/null
@@ -1 +0,0 @@
-Subproject commit dbb13f31370a743633dc94d3639d55c8c4d74e1d
diff --git a/litex/soc/cores/cpu/lm32/verilog/submodule b/litex/soc/cores/cpu/lm32/verilog/submodule
deleted file mode 160000
index 84b3e3ca0..000000000
--- a/litex/soc/cores/cpu/lm32/verilog/submodule
+++ /dev/null
@@ -1 +0,0 @@
-Subproject commit 84b3e3ca0ad9535acaef201c1482342871358b08
diff --git a/litex/soc/cores/cpu/microwatt/sources b/litex/soc/cores/cpu/microwatt/sources
deleted file mode 160000
index 1a826f077..000000000
--- a/litex/soc/cores/cpu/microwatt/sources
+++ /dev/null
@@ -1 +0,0 @@
-Subproject commit 1a826f077bb518bc3ffd799c47a6dd2852165f89
diff --git a/litex/soc/cores/cpu/minerva/verilog b/litex/soc/cores/cpu/minerva/verilog
deleted file mode 160000
index fb296e4e4..000000000
--- a/litex/soc/cores/cpu/minerva/verilog
+++ /dev/null
@@ -1 +0,0 @@
-Subproject commit fb296e4e48e5ced8dd05f2228d84b4bc18f54f75
diff --git a/litex/soc/cores/cpu/mor1kx/verilog b/litex/soc/cores/cpu/mor1kx/verilog
deleted file mode 160000
index 69b97fcb4..000000000
--- a/litex/soc/cores/cpu/mor1kx/verilog
+++ /dev/null
@@ -1 +0,0 @@
-Subproject commit 69b97fcb43b35d6c6639ecc68e63d912c09ee8da
diff --git a/litex/soc/cores/cpu/picorv32/verilog b/litex/soc/cores/cpu/picorv32/verilog
deleted file mode 160000
index a9e0ea54c..000000000
--- a/litex/soc/cores/cpu/picorv32/verilog
+++ /dev/null
@@ -1 +0,0 @@
-Subproject commit a9e0ea54cffa162cfe901ff8d30d8877a18c6d8e
diff --git a/litex/soc/cores/cpu/rocket/verilog b/litex/soc/cores/cpu/rocket/verilog
deleted file mode 160000
index fb31001d9..000000000
--- a/litex/soc/cores/cpu/rocket/verilog
+++ /dev/null
@@ -1 +0,0 @@
-Subproject commit fb31001d9655ebfb8ab25209e094939f68feb6a7
diff --git a/litex/soc/cores/cpu/vexriscv/verilog b/litex/soc/cores/cpu/vexriscv/verilog
deleted file mode 160000
index 8baad2198..000000000
--- a/litex/soc/cores/cpu/vexriscv/verilog
+++ /dev/null
@@ -1 +0,0 @@
-Subproject commit 8baad219885a47f65959a9cd4870691e84678db4
diff --git a/litex/soc/software/compiler_rt b/litex/soc/software/compiler_rt
deleted file mode 160000
index 81fb4f00c..000000000
--- a/litex/soc/software/compiler_rt
+++ /dev/null
@@ -1 +0,0 @@
-Subproject commit 81fb4f00c2cfe13814765968e09931ffa93b5138

From 83b25813311ce63edd8434500a0d3872967baca7 Mon Sep 17 00:00:00 2001
From: Tim 'mithro' Ansell <me@mith.ro>
Date: Sun, 23 Feb 2020 17:04:47 -0800
Subject: [PATCH 10/95] Fix the libcompiler_rt path.

---
 litex/soc/integration/builder.py           | 3 +++
 litex/soc/software/libcompiler_rt/Makefile | 2 +-
 2 files changed, 4 insertions(+), 1 deletion(-)

diff --git a/litex/soc/integration/builder.py b/litex/soc/integration/builder.py
index 6e995fa4c..80cc3753a 100644
--- a/litex/soc/integration/builder.py
+++ b/litex/soc/integration/builder.py
@@ -15,6 +15,7 @@ import struct
 import shutil
 
 from litex.build.tools import write_to_file
+from litex.data.find import find_data
 from litex.soc.integration import export, soc_core
 
 __all__ = ["soc_software_packages", "soc_directory",
@@ -100,6 +101,8 @@ class Builder:
                 exec_profiles["EXECUTE_IN_PLACE"] = "1"
             for k, v in exec_profiles.items():
                 define(k, v)
+            define(
+                "COMPILER_RT_DIRECTORY", find_data("software", "compiler_rt"))
             define("SOC_DIRECTORY", soc_directory)
             variables_contents.append("export BUILDINC_DIRECTORY\n")
             define("BUILDINC_DIRECTORY", self.include_dir)
diff --git a/litex/soc/software/libcompiler_rt/Makefile b/litex/soc/software/libcompiler_rt/Makefile
index 929616b3c..ef78cd569 100644
--- a/litex/soc/software/libcompiler_rt/Makefile
+++ b/litex/soc/software/libcompiler_rt/Makefile
@@ -23,7 +23,7 @@ libcompiler_rt.a: $(OBJECTS)
 mulsi3.o: $(SOC_DIRECTORY)/software/libcompiler_rt/mulsi3.c
 	$(compile)
 
-%.o: $(SOC_DIRECTORY)/software/compiler_rt/lib/builtins/%.c
+%.o: $(COMPILER_RT_DIRECTORY)/lib/builtins/%.c
 	$(compile)
 
 .PHONY: all clean

From 2e3b7f20c79b331072e2e6cca9dbf43cdcdaa93d Mon Sep 17 00:00:00 2001
From: Tim 'mithro' Ansell <me@mith.ro>
Date: Sun, 29 Mar 2020 17:28:20 -0700
Subject: [PATCH 11/95] Fix typo in error message.

---
 litex/data/find.py | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/litex/data/find.py b/litex/data/find.py
index 1a143b1dc..74c910992 100644
--- a/litex/data/find.py
+++ b/litex/data/find.py
@@ -7,7 +7,7 @@ def find_data(data_type, data_name):
         return dm.data_location
     except ImportError as e:
         raise ImportError("""\
-litex-data-{dt}-{dn} module not install! Unable to use {dn} {dt}.
+litex-data-{dt}-{dn} module not installed! Unable to use {dn} {dt}.
 {e}
 
 You can install this by running;

From e618d41ffb69000662693b1515b3e0a4549780b7 Mon Sep 17 00:00:00 2001
From: Tim 'mithro' Ansell <me@mith.ro>
Date: Sun, 29 Mar 2020 17:28:46 -0700
Subject: [PATCH 12/95] Fixing mor1kx data finding.

---
 litex/soc/cores/cpu/mor1kx/core.py | 3 +--
 1 file changed, 1 insertion(+), 2 deletions(-)

diff --git a/litex/soc/cores/cpu/mor1kx/core.py b/litex/soc/cores/cpu/mor1kx/core.py
index 4fe41b36c..a380e3faf 100644
--- a/litex/soc/cores/cpu/mor1kx/core.py
+++ b/litex/soc/cores/cpu/mor1kx/core.py
@@ -174,8 +174,7 @@ class MOR1KX(CPU):
     @staticmethod
     def add_sources(platform):
         vdir = os.path.join(
-            os.path.abspath(os.path.dirname(__file__)),
-            "verilog", "rtl", "verilog")
+            find_data("cpu", "mor1kx"), "rtl", "verilog")
         platform.add_source_dir(vdir)
         platform.add_verilog_include_path(vdir)
 

From a39a4ec2ed9657c6f34285f28e6dffd88ee49046 Mon Sep 17 00:00:00 2001
From: Tim 'mithro' Ansell <me@mith.ro>
Date: Sun, 29 Mar 2020 17:36:06 -0700
Subject: [PATCH 13/95] Only allow fast-forward pulls.

---
 litex_setup.py | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/litex_setup.py b/litex_setup.py
index c6389ad66..be9c3b432 100755
--- a/litex_setup.py
+++ b/litex_setup.py
@@ -136,7 +136,7 @@ if "update" in sys.argv[1:]:
         print("[updating " + name + "]...")
         os.chdir(os.path.join(current_path, name))
         subprocess.check_call(
-            "git pull",
+            "git pull --ff-only",
             shell=True)
         os.chdir(os.path.join(current_path))
 

From ebcb2a44064f5a09668c18d7f9d66ca4e85063b5 Mon Sep 17 00:00:00 2001
From: Tim 'mithro' Ansell <me@mith.ro>
Date: Mon, 6 Apr 2020 11:16:57 -0700
Subject: [PATCH 14/95] Rename litex-data-XXX-YYY to pythondata-XXX-YYY

---
 litex/__init__.py                       | 20 +++++++++++++++++---
 litex/data/__init__.py                  |  2 --
 litex/data/find.py                      | 15 ---------------
 litex/soc/cores/cpu/blackparrot/core.py |  5 +++--
 litex/soc/cores/cpu/lm32/core.py        |  4 ++--
 litex/soc/cores/cpu/microwatt/core.py   |  6 ++++--
 litex/soc/cores/cpu/mor1kx/core.py      |  5 +++--
 litex/soc/cores/cpu/picorv32/core.py    |  4 ++--
 litex/soc/cores/cpu/rocket/core.py      |  4 ++--
 litex/soc/cores/cpu/vexriscv/core.py    |  4 ++--
 litex/soc/integration/builder.py        |  5 +++--
 litex_setup.py                          | 18 +++++++++---------
 setup.py                                |  2 +-
 13 files changed, 48 insertions(+), 46 deletions(-)
 delete mode 100644 litex/data/__init__.py
 delete mode 100644 litex/data/find.py

diff --git a/litex/__init__.py b/litex/__init__.py
index 2454c0e79..0499e31a8 100644
--- a/litex/__init__.py
+++ b/litex/__init__.py
@@ -1,6 +1,3 @@
-# https://packaging.python.org/guides/packaging-namespace-packages/#pkgutil-style-namespace-packages
-__path__ = __import__('pkgutil').extend_path(__path__, __name__)
-
 import sys
 
 # retro-compat 2019-09-30
@@ -12,3 +9,20 @@ from litex.soc.integration import export
 sys.modules["litex.soc.integration.cpu_interface"] = export
 
 from litex.tools.litex_client import RemoteClient
+
+def get_data_mod(data_type, data_name):
+    """Get the pythondata-{}-{} module or raise a useful error message."""
+    imp = "import pythondata_{}_{} as dm".format(data_type, data_name)
+    try:
+        l = {}
+        exec(imp, {}, l)
+        dm = l['dm']
+        return dm
+    except ImportError as e:
+        raise ImportError("""\
+pythondata-{dt}-{dn} module not installed! Unable to use {dn} {dt}.
+{e}
+
+You can install this by running;
+ pip install git+https://github.com/litex-hub/pythondata-{dt}-{dn}.git
+""".format(dt=data_type, dn=data_name, e=e))
diff --git a/litex/data/__init__.py b/litex/data/__init__.py
deleted file mode 100644
index c9b5ae908..000000000
--- a/litex/data/__init__.py
+++ /dev/null
@@ -1,2 +0,0 @@
-# https://packaging.python.org/guides/packaging-namespace-packages/#pkgutil-style-namespace-packages
-__path__ = __import__('pkgutil').extend_path(__path__, __name__)
diff --git a/litex/data/find.py b/litex/data/find.py
deleted file mode 100644
index 74c910992..000000000
--- a/litex/data/find.py
+++ /dev/null
@@ -1,15 +0,0 @@
-def find_data(data_type, data_name):
-    imp = "from litex.data.{} import {} as dm".format(data_type, data_name)
-    try:
-        l = {}
-        exec(imp, {}, l)
-        dm = l['dm']
-        return dm.data_location
-    except ImportError as e:
-        raise ImportError("""\
-litex-data-{dt}-{dn} module not installed! Unable to use {dn} {dt}.
-{e}
-
-You can install this by running;
- pip install git+https://github.com/litex-hub/litex-data-{dt}-{dn}.git
-""".format(dt=data_type, dn=data_name, e=e))
diff --git a/litex/soc/cores/cpu/blackparrot/core.py b/litex/soc/cores/cpu/blackparrot/core.py
index e55e6252b..9f61c6c69 100644
--- a/litex/soc/cores/cpu/blackparrot/core.py
+++ b/litex/soc/cores/cpu/blackparrot/core.py
@@ -32,7 +32,7 @@ import os
 
 from migen import *
 
-from litex.data.find import find_data
+from litex import get_data_mod
 from litex.soc.interconnect import axi
 from litex.soc.interconnect import wishbone
 from litex.soc.cores.cpu import CPU
@@ -116,7 +116,8 @@ class BlackParrotRV64(CPU):
 
     @staticmethod
     def add_sources(platform, variant="standard"):
-        filename = os.path.join(find_data("cpu", "blackparrot"), "flist_litex.verilator")
+        filename = get_data_mod("cpu", "blackparrot").data_file(
+            "flist_litex.verilator")
         with open(filename) as openfileobject:
             for line in openfileobject:
                 temp = line
diff --git a/litex/soc/cores/cpu/lm32/core.py b/litex/soc/cores/cpu/lm32/core.py
index 75e7ba8cb..ffa910d01 100644
--- a/litex/soc/cores/cpu/lm32/core.py
+++ b/litex/soc/cores/cpu/lm32/core.py
@@ -9,7 +9,7 @@ import os
 
 from migen import *
 
-from litex.data.find import find_data
+from litex import get_data_mod
 from litex.soc.interconnect import wishbone
 from litex.soc.cores.cpu import CPU
 
@@ -97,7 +97,7 @@ class LM32(CPU):
 
     @staticmethod
     def add_sources(platform, variant):
-        vdir = find_data("cpu", "lm32")
+        vdir = get_data_mod("cpu", "lm32").data_location
         platform.add_sources(os.path.join(vdir, "rtl"),
             "lm32_cpu.v",
             "lm32_instruction_unit.v",
diff --git a/litex/soc/cores/cpu/microwatt/core.py b/litex/soc/cores/cpu/microwatt/core.py
index aa00ee172..d918d8b13 100644
--- a/litex/soc/cores/cpu/microwatt/core.py
+++ b/litex/soc/cores/cpu/microwatt/core.py
@@ -6,7 +6,7 @@ import os
 
 from migen import *
 
-from litex.data.find import find_data
+from litex import get_data_mod
 from litex.soc.interconnect import wishbone
 from litex.soc.cores.cpu import CPU
 
@@ -99,7 +99,9 @@ class Microwatt(CPU):
 
     @staticmethod
     def add_sources(platform):
-        sdir = os.path.join(find_data("cpu", "microwatt"), "sources")
+        sdir = os.path.join(
+            get_data_mod("cpu", "microwatt").data_location,
+            "sources")
         platform.add_sources(sdir,
             # Common / Types / Helpers
             "decode_types.vhdl",
diff --git a/litex/soc/cores/cpu/mor1kx/core.py b/litex/soc/cores/cpu/mor1kx/core.py
index a380e3faf..7c3d86a9b 100644
--- a/litex/soc/cores/cpu/mor1kx/core.py
+++ b/litex/soc/cores/cpu/mor1kx/core.py
@@ -8,7 +8,7 @@ import os
 
 from migen import *
 
-from litex.data.find import find_data
+from litex import get_data_mod
 from litex.soc.interconnect import wishbone
 from litex.soc.cores.cpu import CPU
 
@@ -174,7 +174,8 @@ class MOR1KX(CPU):
     @staticmethod
     def add_sources(platform):
         vdir = os.path.join(
-            find_data("cpu", "mor1kx"), "rtl", "verilog")
+            get_data_mod("cpu", "mor1kx").data_location,
+            "rtl", "verilog")
         platform.add_source_dir(vdir)
         platform.add_verilog_include_path(vdir)
 
diff --git a/litex/soc/cores/cpu/picorv32/core.py b/litex/soc/cores/cpu/picorv32/core.py
index 47017ac6b..b798e9dd7 100644
--- a/litex/soc/cores/cpu/picorv32/core.py
+++ b/litex/soc/cores/cpu/picorv32/core.py
@@ -11,7 +11,7 @@ import os
 
 from migen import *
 
-from litex.data.find import find_data
+from litex import get_data_mod
 from litex.soc.interconnect import wishbone
 from litex.soc.cores.cpu import CPU
 
@@ -180,7 +180,7 @@ class PicoRV32(CPU):
 
     @staticmethod
     def add_sources(platform):
-        vdir = find_data("cpu", "picorv32")
+        vdir = get_data_mod("cpu", "picorv32").data_location
         platform.add_source(os.path.join(vdir, "picorv32.v"))
 
     def do_finalize(self):
diff --git a/litex/soc/cores/cpu/rocket/core.py b/litex/soc/cores/cpu/rocket/core.py
index dff3fe707..c29a2796b 100644
--- a/litex/soc/cores/cpu/rocket/core.py
+++ b/litex/soc/cores/cpu/rocket/core.py
@@ -33,7 +33,7 @@ import os
 
 from migen import *
 
-from litex.data.find import find_data
+from litex import get_data_mod
 from litex.soc.interconnect import axi
 from litex.soc.interconnect import wishbone
 from litex.soc.cores.cpu import CPU
@@ -239,7 +239,7 @@ class RocketRV64(CPU):
 
     @staticmethod
     def add_sources(platform, variant="standard"):
-        vdir = find_data("cpu", "rocket")
+        vdir = get_data_mod("cpu", "rocket").data_location
         platform.add_sources(
             os.path.join(vdir, "generated-src"),
             CPU_VARIANTS[variant] + ".v",
diff --git a/litex/soc/cores/cpu/vexriscv/core.py b/litex/soc/cores/cpu/vexriscv/core.py
index 42328d199..157b948a3 100644
--- a/litex/soc/cores/cpu/vexriscv/core.py
+++ b/litex/soc/cores/cpu/vexriscv/core.py
@@ -12,7 +12,7 @@ import os
 
 from migen import *
 
-from litex.data.find import find_data
+from litex import get_data_mod
 from litex.soc.interconnect import wishbone
 from litex.soc.interconnect.csr import *
 from litex.soc.cores.cpu import CPU
@@ -247,7 +247,7 @@ class VexRiscv(CPU, AutoCSR):
     @staticmethod
     def add_sources(platform, variant="standard"):
         cpu_filename = CPU_VARIANTS[variant] + ".v"
-        vdir = find_data("cpu", "vexriscv")
+        vdir = get_data_mod("cpu", "vexriscv").data_location
         platform.add_source(os.path.join(vdir, cpu_filename))
 
     def use_external_variant(self, variant_filename):
diff --git a/litex/soc/integration/builder.py b/litex/soc/integration/builder.py
index 80cc3753a..745eb75e9 100644
--- a/litex/soc/integration/builder.py
+++ b/litex/soc/integration/builder.py
@@ -14,8 +14,8 @@ import subprocess
 import struct
 import shutil
 
+from litex import get_data_mod
 from litex.build.tools import write_to_file
-from litex.data.find import find_data
 from litex.soc.integration import export, soc_core
 
 __all__ = ["soc_software_packages", "soc_directory",
@@ -102,7 +102,8 @@ class Builder:
             for k, v in exec_profiles.items():
                 define(k, v)
             define(
-                "COMPILER_RT_DIRECTORY", find_data("software", "compiler_rt"))
+                "COMPILER_RT_DIRECTORY",
+                get_data_mod("software", "compiler_rt").data_location)
             define("SOC_DIRECTORY", soc_directory)
             variables_contents.append("export BUILDINC_DIRECTORY\n")
             define("BUILDINC_DIRECTORY", self.include_dir)
diff --git a/litex_setup.py b/litex_setup.py
index be9c3b432..82259f1a1 100755
--- a/litex_setup.py
+++ b/litex_setup.py
@@ -19,7 +19,7 @@ repos = [
     ("migen",        ("https://github.com/m-labs/",        True,  True)),
 
     # LiteX SoC builder
-    ('litex-data-software-compiler_rt', ("https://github.com/litex-hub/", False, True)),
+    ("pythondata-software-compiler_rt", ("https://github.com/litex-hub/", False, True)),
     ("litex",        ("https://github.com/enjoy-digital/", False,  True)),
 
     # LiteX cores ecosystem
@@ -38,14 +38,14 @@ repos = [
     ("litex-boards", ("https://github.com/litex-hub/",     False, True)),
 
     # Optional LiteX data
-    ("litex-data-cpu-blackparrot", ("https://github.com/litex-hub/", False, True)),
-    ("litex-data-cpu-mor1kx",      ("https://github.com/litex-hub/", False, True)),
-    ("litex-data-cpu-lm32",        ("https://github.com/litex-hub/", False, True)),
-    ("litex-data-cpu-microwatt",   ("https://github.com/litex-hub/", False, True)),
-    ("litex-data-cpu-picorv32",    ("https://github.com/litex-hub/", False, True)),
-    ("litex-data-cpu-rocket",      ("https://github.com/litex-hub/", False, True)),
-    ("litex-data-cpu-vexriscv",    ("https://github.com/litex-hub/", False, True)),
-    ("litex-data-misc-tapcfg",     ("https://github.com/litex-hub/", False, True)),
+    ("pythondata-cpu-blackparrot", ("https://github.com/litex-hub/", False, True)),
+    ("pythondata-cpu-mor1kx",      ("https://github.com/litex-hub/", False, True)),
+    ("pythondata-cpu-lm32",        ("https://github.com/litex-hub/", False, True)),
+    ("pythondata-cpu-microwatt",   ("https://github.com/litex-hub/", False, True)),
+    ("pythondata-cpu-picorv32",    ("https://github.com/litex-hub/", False, True)),
+    ("pythondata-cpu-rocket",      ("https://github.com/litex-hub/", False, True)),
+    ("pythondata-cpu-vexriscv",    ("https://github.com/litex-hub/", False, True)),
+    ("pythondata-misc-tapcfg",     ("https://github.com/litex-hub/", False, True)),
 ]
 repos = OrderedDict(repos)
 
diff --git a/setup.py b/setup.py
index 9c7444270..496c65d64 100755
--- a/setup.py
+++ b/setup.py
@@ -17,7 +17,7 @@ setup(
     install_requires=[
         "migen",
         "pyserial",
-        "litex-data-software-compiler_rt",
+        "pythondata-software-compiler_rt",
     ],
     packages=find_packages(exclude=("test*", "sim*", "doc*")),
     include_package_data=True,

From 3aee8a5227e20e37fef29936b3634360e48264ce Mon Sep 17 00:00:00 2001
From: Tim 'mithro' Ansell <me@mith.ro>
Date: Wed, 8 Apr 2020 23:17:41 -0700
Subject: [PATCH 15/95] Remove directories from submodules from MANIFEST.in
 file.

---
 MANIFEST.in | 7 -------
 1 file changed, 7 deletions(-)

diff --git a/MANIFEST.in b/MANIFEST.in
index a15c845d9..d64974bd3 100644
--- a/MANIFEST.in
+++ b/MANIFEST.in
@@ -1,8 +1 @@
 graft litex/build/sim
-graft litex/soc/software
-graft litex/soc/cores/cpu/lm32/verilog
-graft litex/soc/cores/cpu/minerva/verilog
-graft litex/soc/cores/cpu/mor1kx/verilog
-graft litex/soc/cores/cpu/picorv32/verilog
-graft litex/soc/cores/cpu/rocket/verilog
-graft litex/soc/cores/cpu/vexriscv/verilog

From 1f35669508ea1f5fce78e213e44db0ea3e2db805 Mon Sep 17 00:00:00 2001
From: Tim 'mithro' Ansell <me@mith.ro>
Date: Sat, 11 Apr 2020 18:34:29 -0700
Subject: [PATCH 16/95] litex_sim: Find tapcfg from pythondata module.

---
 litex/build/sim/core/modules/ethernet/Makefile       | 6 +++---
 litex/build/sim/core/modules/xgmii_ethernet/Makefile | 6 +++---
 litex/build/sim/core/modules/xgmii_ethernet/tapcfg   | 1 -
 litex/build/sim/verilator.py                         | 6 ++++--
 4 files changed, 10 insertions(+), 9 deletions(-)
 delete mode 120000 litex/build/sim/core/modules/xgmii_ethernet/tapcfg

diff --git a/litex/build/sim/core/modules/ethernet/Makefile b/litex/build/sim/core/modules/ethernet/Makefile
index 461ed86be..392ede182 100644
--- a/litex/build/sim/core/modules/ethernet/Makefile
+++ b/litex/build/sim/core/modules/ethernet/Makefile
@@ -3,7 +3,7 @@ UNAME_S := $(shell uname -s)
 
 include $(SRC_DIR)/modules/rules.mak
 
-CFLAGS += -I$(MOD_SRC_DIR)/tapcfg/src/include
+CFLAGS += -I$(TAPCFG_DIRECTORY)/src/include
 OBJS = $(MOD).o tapcfg.o taplog.o
 
 $(MOD).so: $(OBJS)
@@ -13,8 +13,8 @@ else
 	$(CC) $(LDFLAGS) -Wl,-soname,$@ -o $@ $^
 endif
 
-tapcfg.o: $(MOD_SRC_DIR)/tapcfg/src/lib/tapcfg.c
+tapcfg.o: $(TAPCFG_DIRECTORY)/src/lib/tapcfg.c
 	$(CC) $(CFLAGS) -c -o $@ $<
 
-taplog.o: $(MOD_SRC_DIR)/tapcfg/src/lib/taplog.c
+taplog.o: $(TAPCFG_DIRECTORY)/src/lib/taplog.c
 	$(CC) $(CFLAGS) -c -o $@ $<
diff --git a/litex/build/sim/core/modules/xgmii_ethernet/Makefile b/litex/build/sim/core/modules/xgmii_ethernet/Makefile
index 461ed86be..392ede182 100644
--- a/litex/build/sim/core/modules/xgmii_ethernet/Makefile
+++ b/litex/build/sim/core/modules/xgmii_ethernet/Makefile
@@ -3,7 +3,7 @@ UNAME_S := $(shell uname -s)
 
 include $(SRC_DIR)/modules/rules.mak
 
-CFLAGS += -I$(MOD_SRC_DIR)/tapcfg/src/include
+CFLAGS += -I$(TAPCFG_DIRECTORY)/src/include
 OBJS = $(MOD).o tapcfg.o taplog.o
 
 $(MOD).so: $(OBJS)
@@ -13,8 +13,8 @@ else
 	$(CC) $(LDFLAGS) -Wl,-soname,$@ -o $@ $^
 endif
 
-tapcfg.o: $(MOD_SRC_DIR)/tapcfg/src/lib/tapcfg.c
+tapcfg.o: $(TAPCFG_DIRECTORY)/src/lib/tapcfg.c
 	$(CC) $(CFLAGS) -c -o $@ $<
 
-taplog.o: $(MOD_SRC_DIR)/tapcfg/src/lib/taplog.c
+taplog.o: $(TAPCFG_DIRECTORY)/src/lib/taplog.c
 	$(CC) $(CFLAGS) -c -o $@ $<
diff --git a/litex/build/sim/core/modules/xgmii_ethernet/tapcfg b/litex/build/sim/core/modules/xgmii_ethernet/tapcfg
deleted file mode 120000
index d0b6901bd..000000000
--- a/litex/build/sim/core/modules/xgmii_ethernet/tapcfg
+++ /dev/null
@@ -1 +0,0 @@
-../ethernet/tapcfg/
\ No newline at end of file
diff --git a/litex/build/sim/verilator.py b/litex/build/sim/verilator.py
index f068d08d1..2fc251940 100644
--- a/litex/build/sim/verilator.py
+++ b/litex/build/sim/verilator.py
@@ -7,7 +7,7 @@ import sys
 import subprocess
 
 from migen.fhdl.structure import _Fragment
-
+from litex import get_data_mod
 from litex.build import tools
 from litex.build.generic_platform import *
 
@@ -102,13 +102,15 @@ extern "C" void litex_sim_init(void **out)
 
 
 def _generate_sim_variables(include_paths):
+    tapcfg_dir = get_data_mod("misc", "tapcfg").data_location
     include = ""
     for path in include_paths:
         include += "-I"+path+" "
     content = """\
 SRC_DIR = {}
 INC_DIR = {}
-""".format(core_directory, include)
+TAPCFG_DIRECTORY = {}
+""".format(core_directory, include, tapcfg_dir)
     tools.write_to_file("variables.mak", content)
 
 

From b0f8ee987667e4517574ff590f5baff336bfb9d7 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?J=C4=99drzej=20Boczar?= <yendreij@gmail.com>
Date: Fri, 17 Apr 2020 14:52:53 +0200
Subject: [PATCH 17/95] litex_sim: add option to create SDRAM module from SPD
 data

---
 litex/tools/litex_sim.py | 14 +++++++++++---
 1 file changed, 11 insertions(+), 3 deletions(-)

diff --git a/litex/tools/litex_sim.py b/litex/tools/litex_sim.py
index 8ac544fcb..7a526f83a 100755
--- a/litex/tools/litex_sim.py
+++ b/litex/tools/litex_sim.py
@@ -166,6 +166,7 @@ class SimSoC(SoCSDRAM):
         sdram_module          = "MT48LC16M16",
         sdram_init            = [],
         sdram_data_width      = 32,
+        sdram_spd_data        = None,
         sdram_verbosity       = 0,
         **kwargs):
         platform     = Platform()
@@ -182,9 +183,12 @@ class SimSoC(SoCSDRAM):
         # SDRAM ------------------------------------------------------------------------------------
         if with_sdram:
             sdram_clk_freq   = int(100e6) # FIXME: use 100MHz timings
-            sdram_module_cls = getattr(litedram_modules, sdram_module)
-            sdram_rate       = "1:{}".format(sdram_module_nphases[sdram_module_cls.memtype])
-            sdram_module     = sdram_module_cls(sdram_clk_freq, sdram_rate)
+            if sdram_spd_data is None:
+                sdram_module_cls = getattr(litedram_modules, sdram_module)
+                sdram_rate       = "1:{}".format(sdram_module_nphases[sdram_module_cls.memtype])
+                sdram_module     = sdram_module_cls(sdram_clk_freq, sdram_rate)
+            else:
+                sdram_module = litedram_modules.SDRAMModule.from_spd_data(sdram_spd_data, sdram_clk_freq)
             phy_settings     = get_sdram_phy_settings(
                 memtype    = sdram_module.memtype,
                 data_width = sdram_data_width,
@@ -285,6 +289,7 @@ def main():
     parser.add_argument("--sdram-module",         default="MT48LC16M16",   help="Select SDRAM chip")
     parser.add_argument("--sdram-data-width",     default=32,              help="Set SDRAM chip data width")
     parser.add_argument("--sdram-init",           default=None,            help="SDRAM init file")
+    parser.add_argument("--sdram-from-spd-data",  default=None,            help="Generate SDRAM module based on SPD data from file")
     parser.add_argument("--sdram-verbosity",      default=0,               help="Set SDRAM checker verbosity")
     parser.add_argument("--with-ethernet",        action="store_true",     help="Enable Ethernet support")
     parser.add_argument("--with-etherbone",       action="store_true",     help="Enable Etherbone support")
@@ -323,6 +328,9 @@ def main():
         soc_kwargs["sdram_module"]             = args.sdram_module
         soc_kwargs["sdram_data_width"]         = int(args.sdram_data_width)
         soc_kwargs["sdram_verbosity"]          = int(args.sdram_verbosity)
+        if args.sdram_from_spd_data:
+            with open(args.sdram_from_spd_data, "rb") as f:
+                soc_kwargs["sdram_spd_data"] = [int(b) for b in f.read()]
 
     if args.with_ethernet or args.with_etherbone:
         sim_config.add_module("ethernet", "eth", args={"interface": "tap0", "ip": args.remote_ip})

From 22c3923644e9804183217cf8de80c42721860fed Mon Sep 17 00:00:00 2001
From: Florent Kermarrec <florent@enjoy-digital.fr>
Date: Thu, 23 Apr 2020 08:04:04 +0200
Subject: [PATCH 18/95] initial SERV integration.

---
 litex/soc/cores/cpu/__init__.py            | 18 +++--
 litex/soc/cores/cpu/serv/__init__.py       |  1 +
 litex/soc/cores/cpu/serv/core.py           | 91 ++++++++++++++++++++++
 litex/soc/integration/soc_core.py          |  3 +
 litex/soc/software/bios/boot-helper-serv.S |  4 +
 litex/soc/software/bios/main.c             |  2 +
 litex/soc/software/bios/sdram.c            |  2 +
 litex/soc/software/include/base/irq.h      | 10 +++
 litex/soc/software/libbase/crt0-serv.S     | 63 +++++++++++++++
 litex/soc/software/libbase/system.c        |  4 +
 10 files changed, 190 insertions(+), 8 deletions(-)
 create mode 100644 litex/soc/cores/cpu/serv/__init__.py
 create mode 100644 litex/soc/cores/cpu/serv/core.py
 create mode 100644 litex/soc/software/bios/boot-helper-serv.S
 create mode 100644 litex/soc/software/libbase/crt0-serv.S

diff --git a/litex/soc/cores/cpu/__init__.py b/litex/soc/cores/cpu/__init__.py
index db9fdab7b..d0b11a50e 100644
--- a/litex/soc/cores/cpu/__init__.py
+++ b/litex/soc/cores/cpu/__init__.py
@@ -37,17 +37,19 @@ from litex.soc.cores.cpu.minerva import Minerva
 from litex.soc.cores.cpu.rocket import RocketRV64
 from litex.soc.cores.cpu.microwatt import Microwatt
 from litex.soc.cores.cpu.blackparrot import BlackParrotRV64
+from litex.soc.cores.cpu.serv import SERV
 
 CPUS = {
-    "None"       : CPUNone,
-    "lm32"       : LM32,
-    "mor1kx"     : MOR1KX,
-    "picorv32"   : PicoRV32,
-    "vexriscv"   : VexRiscv,
-    "minerva"    : Minerva,
-    "rocket"     : RocketRV64,
-    "microwatt"  : Microwatt,
+    "None"        : CPUNone,
+    "lm32"        : LM32,
+    "mor1kx"      : MOR1KX,
+    "picorv32"    : PicoRV32,
+    "vexriscv"    : VexRiscv,
+    "minerva"     : Minerva,
+    "rocket"      : RocketRV64,
+    "microwatt"   : Microwatt,
     "blackparrot" : BlackParrotRV64,
+    "serv"        : SERV
 }
 
 # CPU Variants/Extensions Definition ---------------------------------------------------------------
diff --git a/litex/soc/cores/cpu/serv/__init__.py b/litex/soc/cores/cpu/serv/__init__.py
new file mode 100644
index 000000000..b46284ac8
--- /dev/null
+++ b/litex/soc/cores/cpu/serv/__init__.py
@@ -0,0 +1 @@
+from litex.soc.cores.cpu.serv.core import SERV
diff --git a/litex/soc/cores/cpu/serv/core.py b/litex/soc/cores/cpu/serv/core.py
new file mode 100644
index 000000000..8128fda5a
--- /dev/null
+++ b/litex/soc/cores/cpu/serv/core.py
@@ -0,0 +1,91 @@
+# This file is Copyright (c) 2020 Florent Kermarrec <florent@enjoy-digital.fr>
+
+# License: BSD
+
+import os
+
+from migen import *
+
+from litex.soc.interconnect import wishbone
+from litex.soc.cores.cpu import CPU
+
+
+CPU_VARIANTS = ["standard"]
+
+
+class SERV(CPU):
+    name                 = "serv"
+    data_width           = 32
+    endianness           = "little"
+    gcc_triple           = ("riscv64-unknown-elf", "riscv32-unknown-elf", "riscv-none-embed",
+                            "riscv64-linux", "riscv-sifive-elf", "riscv64-none-elf")
+    linker_output_format = "elf32-littleriscv"
+    io_regions           = {0x80000000: 0x80000000} # origin, length
+
+    @property
+    def gcc_flags(self):
+        flags =  "-march=rv32i "
+        flags += "-mabi=ilp32 "
+        flags += "-D__serv__ "
+        return flags
+
+    def __init__(self, platform, variant="standard"):
+        assert variant in CPU_VARIANTS, "Unsupported variant %s" % variant
+        self.platform  = platform
+        self.variant   = variant
+        self.reset     = Signal()
+        self.ibus      = ibus = wishbone.Interface()
+        self.dbus      = dbus = wishbone.Interface()
+        self.buses     = [self.ibus, dbus]
+        self.interrupt = Signal(32)
+
+        # # #
+
+        self.cpu_params = dict(
+            # clock / reset
+            i_clk   = ClockSignal(),
+            i_i_rst = ResetSignal(),
+
+            # timer irq
+            i_i_timer_irq = 0,
+
+            # ibus
+            o_o_ibus_adr = ibus.adr,
+            o_o_ibus_cyc = ibus.cyc,
+            i_i_ibus_rdt = ibus.dat_r,
+            i_i_ibus_ack = ibus.ack,
+
+
+            # dbus
+            o_o_dbus_adr = dbus.adr,
+            o_o_dbus_dat = dbus.dat_w,
+            o_o_dbus_sel = dbus.sel,
+            o_o_dbus_we  = dbus.we,
+            o_o_dbus_cyc = dbus.cyc,
+            i_i_dbus_rdt = dbus.dat_r,
+            i_i_dbus_ack = dbus.ack,
+        )
+        self.comb += [
+            ibus.stb.eq(ibus.cyc),
+            dbus.stb.eq(dbus.cyc),
+        ]
+
+        # add verilog sources
+        self.add_sources(platform)
+
+    def set_reset_address(self, reset_address):
+        assert not hasattr(self, "reset_address")
+        self.reset_address = reset_address
+        self.cpu_params.update(p_RESET_PC=reset_address)
+
+    @staticmethod
+    def add_sources(platform):
+        # FIXME: add SERV as submodule
+        os.system("git clone https://github.com/olofk/serv")
+        vdir = os.path.join("serv", "rtl")
+        platform.add_source_dir(vdir)
+        platform.add_verilog_include_path(vdir)
+
+    def do_finalize(self):
+        assert hasattr(self, "reset_address")
+        self.specials += Instance("serv_top", **self.cpu_params)
diff --git a/litex/soc/integration/soc_core.py b/litex/soc/integration/soc_core.py
index 3eb0016c7..ab8704ced 100644
--- a/litex/soc/integration/soc_core.py
+++ b/litex/soc/integration/soc_core.py
@@ -132,6 +132,9 @@ class SoCCore(LiteXSoC):
         self.cpu_type                   = cpu_type
         self.cpu_variant                = cpu_variant
 
+        if cpu_type == "serv":
+            self.add_constant("UART_POLLING") # FIXME: use UART in polling mode for SERV bringup
+
         self.integrated_rom_size        = integrated_rom_size
         self.integrated_rom_initialized = integrated_rom_init != []
         self.integrated_sram_size       = integrated_sram_size
diff --git a/litex/soc/software/bios/boot-helper-serv.S b/litex/soc/software/bios/boot-helper-serv.S
new file mode 100644
index 000000000..e8bd5c760
--- /dev/null
+++ b/litex/soc/software/bios/boot-helper-serv.S
@@ -0,0 +1,4 @@
+	.section .text, "ax", @progbits
+	.global boot_helper
+boot_helper:
+	jr x13
diff --git a/litex/soc/software/bios/main.c b/litex/soc/software/bios/main.c
index 0d2e6d863..1d68210c9 100644
--- a/litex/soc/software/bios/main.c
+++ b/litex/soc/software/bios/main.c
@@ -647,6 +647,8 @@ int main(int i, char **c)
 	printf("RocketRV64[imac]");
 #elif __blackparrot__
         printf("BlackParrotRV64[ia]");
+#elif __serv__
+	printf("SERV");
 #else
 	printf("Unknown");
 #endif
diff --git a/litex/soc/software/bios/sdram.c b/litex/soc/software/bios/sdram.c
index 53333cd84..de49a942d 100644
--- a/litex/soc/software/bios/sdram.c
+++ b/litex/soc/software/bios/sdram.c
@@ -48,6 +48,8 @@ __attribute__((unused)) static void cdelay(int i)
 		__asm__ volatile("nop");
 #elif defined (__blackparrot__)
 		__asm__ volatile("nop");
+#elif defined (__serv__)
+		__asm__ volatile("nop");
 #else
 #error Unsupported architecture
 #endif
diff --git a/litex/soc/software/include/base/irq.h b/litex/soc/software/include/base/irq.h
index 7ff9b4033..00dad8a2b 100644
--- a/litex/soc/software/include/base/irq.h
+++ b/litex/soc/software/include/base/irq.h
@@ -75,6 +75,8 @@ static inline unsigned int irq_getie(void)
 	return 0; // FIXME
 #elif defined (__blackparrot__) 
 	return (csrr(mstatus) & CSR_MSTATUS_MIE) != 0;//TODO
+#elif defined (__serv__)
+	return 0; /* FIXME */
 #else
 #error Unsupported architecture
 #endif
@@ -104,6 +106,8 @@ static inline void irq_setie(unsigned int ie)
 	// FIXME
 #elif defined (__blackparrot__)
 	if(ie) csrs(mstatus,CSR_MSTATUS_MIE); else csrc(mstatus,CSR_MSTATUS_MIE);//TODO:BP
+#elif defined (__serv__)
+	/* FIXME */
 #else
 #error Unsupported architecture
 #endif
@@ -135,6 +139,8 @@ static inline unsigned int irq_getmask(void)
 	return 0; // FIXME
 #elif defined (__blackparrot__)
 	//TODO:BP
+#elif defined (__serv__)
+	return 0; /* FIXME */
 #else
 #error Unsupported architecture
 #endif
@@ -160,6 +166,8 @@ static inline void irq_setmask(unsigned int mask)
 	// FIXME
 #elif defined (__blackparrot__)
 	//TODO:BP
+#elif defined (__serv__)
+	/* FIXME */
 #else
 #error Unsupported architecture
 #endif
@@ -189,6 +197,8 @@ static inline unsigned int irq_pending(void)
 	return 0; // FIXME
 #elif defined (__blackparrot__)
 	return csr_readl(PLIC_PENDING) >> 1;//TODO:BP
+#elif defined (__serv__)
+	return 0;/* FIXME */
 #else
 #error Unsupported architecture
 #endif
diff --git a/litex/soc/software/libbase/crt0-serv.S b/litex/soc/software/libbase/crt0-serv.S
new file mode 100644
index 000000000..6f6e9e6c0
--- /dev/null
+++ b/litex/soc/software/libbase/crt0-serv.S
@@ -0,0 +1,63 @@
+#define MIE_MEIE 	0x800
+
+	.global _start
+_start:
+	j reset_vector
+
+reset_vector:
+	la sp, _fstack
+	la t0, trap_vector
+	csrw mtvec, t0
+
+	// initialize .bss
+	la t0, _fbss
+	la t1, _ebss
+1:	beq t0, t1, 2f
+	sw zero, 0(t0)
+	addi t0, t0, 4
+	j 1b
+2:
+	// enable external interrupts
+	li t0, MIE_MEIE
+	csrs mie, t0
+
+	call main
+1:	j 1b
+
+trap_vector:
+	addi sp, sp, -16*4
+	sw ra,  0*4(sp)
+	sw t0,  1*4(sp)
+	sw t1,  2*4(sp)
+	sw t2,  3*4(sp)
+	sw a0,  4*4(sp)
+	sw a1,  5*4(sp)
+	sw a2,  6*4(sp)
+	sw a3,  7*4(sp)
+	sw a4,  8*4(sp)
+	sw a5,  9*4(sp)
+	sw a6, 10*4(sp)
+	sw a7, 11*4(sp)
+	sw t3, 12*4(sp)
+	sw t4, 13*4(sp)
+	sw t5, 14*4(sp)
+	sw t6, 15*4(sp)
+	call isr
+	lw ra,  0*4(sp)
+	lw t0,  1*4(sp)
+	lw t1,  2*4(sp)
+	lw t2,  3*4(sp)
+	lw a0,  4*4(sp)
+	lw a1,  5*4(sp)
+	lw a2,  6*4(sp)
+	lw a3,  7*4(sp)
+	lw a4,  8*4(sp)
+	lw a5,  9*4(sp)
+	lw a6, 10*4(sp)
+	lw a7, 11*4(sp)
+	lw t3, 12*4(sp)
+	lw t4, 13*4(sp)
+	lw t5, 14*4(sp)
+	lw t6, 15*4(sp)
+	addi sp, sp, 16*4
+	mret
diff --git a/litex/soc/software/libbase/system.c b/litex/soc/software/libbase/system.c
index e8b3e5055..49d23ac6d 100644
--- a/litex/soc/software/libbase/system.c
+++ b/litex/soc/software/libbase/system.c
@@ -62,6 +62,8 @@ void flush_cpu_icache(void)
 #elif defined (__blackparrot__)
 	/* TODO: BP do something useful here! */
 	asm volatile("nop");
+#elif defined (__serv__)
+	/* no instruction cache */
 #else
 #error Unsupported architecture
 #endif
@@ -114,6 +116,8 @@ void flush_cpu_dcache(void)
 #elif defined (__blackparrot__)
 	/* FIXME: do something useful here! */
 	asm volatile("nop");
+#elif defined (__serv__)
+	/* no data cache */
 #else
 #error Unsupported architecture
 #endif

From ab92e81e3103d3de6a643949570adaab70d2d981 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?J=C4=99drzej=20Boczar?= <yendreij@gmail.com>
Date: Thu, 23 Apr 2020 13:52:28 +0200
Subject: [PATCH 19/95] bios/sdram: add automatic cdly calibration during write
 leveling

---
 litex/soc/software/bios/main.c  |   6 +
 litex/soc/software/bios/sdram.c | 200 ++++++++++++++++++++++++++------
 litex/soc/software/bios/sdram.h |   1 +
 3 files changed, 169 insertions(+), 38 deletions(-)

diff --git a/litex/soc/software/bios/main.c b/litex/soc/software/bios/main.c
index 0d2e6d863..423d4f28d 100644
--- a/litex/soc/software/bios/main.c
+++ b/litex/soc/software/bios/main.c
@@ -394,6 +394,7 @@ static void help(void)
 	puts("sdram_cal                       - run SDRAM calibration");
 	puts("sdram_mpr                       - read SDRAM MPR");
 	puts("sdram_mrwr reg value            - write SDRAM mode registers");
+	puts("sdram_cdly_scan enabled         - enable/disable cdly scan");
 #endif
 #ifdef CSR_SPISDCARD_BASE
         puts("spisdcardboot   - boot from SDCard via SPI hardware bitbang");
@@ -506,6 +507,11 @@ static void do_command(char *c)
 		sdrmrwr(reg, value);
 		sdrhw();
 	}
+	else if(strcmp(token, "sdram_cdly_scan") == 0) {
+		unsigned int enabled;
+		enabled = atoi(get_token(&c));
+		sdr_cdly_scan(enabled);
+	}
 #endif
 #ifdef CSR_SPISDCARD_BASE
         else if(strcmp(token, "spisdcardboot") == 0) spisdcardboot();
diff --git a/litex/soc/software/bios/sdram.c b/litex/soc/software/bios/sdram.c
index 53333cd84..ff094bd0e 100644
--- a/litex/soc/software/bios/sdram.c
+++ b/litex/soc/software/bios/sdram.c
@@ -310,7 +310,7 @@ static void write_delay_inc(int module) {
 	ddrphy_dly_sel_write(0);
 }
 
-int write_level(void)
+static int write_level_scan(int *delays, int show)
 {
 	int i, j, k;
 
@@ -322,20 +322,17 @@ int write_level(void)
 	int one_window_start, one_window_best_start;
 	int one_window_count, one_window_best_count;
 
-	int delays[SDRAM_PHY_MODULES];
-
 	unsigned char buf[DFII_PIX_DATA_BYTES];
 
 	int ok;
 
 	err_ddrphy_wdly = SDRAM_PHY_DELAYS - ddrphy_half_sys8x_taps_read();
 
-	printf("Write leveling:\n");
-
 	sdrwlon();
 	cdelay(100);
 	for(i=0;i<SDRAM_PHY_MODULES;i++) {
-		printf("m%d: |", i);
+		if (show)
+			printf("m%d: |", i);
 
 		/* rst delay */
 		write_delay_rst(i);
@@ -344,9 +341,9 @@ int write_level(void)
 		for(j=0;j<err_ddrphy_wdly;j++) {
 			int zero_count = 0;
 			int one_count = 0;
-			int show = 1;
+			int show_iter = show;
 #if SDRAM_PHY_DELAYS > 32
-			show = (j%16 == 0);
+			show_iter = (j%16 == 0) && show;
 #endif
 			for (k=0; k<128; k++) {
 				ddrphy_wlevel_strobe_write(1);
@@ -362,19 +359,20 @@ int write_level(void)
 				taps_scan[j] = 1;
 			else
 				taps_scan[j] = 0;
-			if (show)
+			if (show_iter)
 				printf("%d", taps_scan[j]);
 			write_delay_inc(i);
 			cdelay(10);
 		}
-		printf("|");
+		if (show)
+			printf("|");
 
 		/* find longer 1 window and set delay at the 0/1 transition */
 		one_window_active = 0;
 		one_window_start = 0;
 		one_window_count = 0;
 		one_window_best_start = 0;
-		one_window_best_count = 0;
+		one_window_best_count = -1;
 		delays[i] = -1;
 		for(j=0;j<err_ddrphy_wdly;j++) {
 			if (one_window_active) {
@@ -393,13 +391,17 @@ int write_level(void)
 				}
 			}
 		}
-		delays[i] = one_window_best_start;
+		/* succeed only if the start of a 1s window has been found */
+		if (one_window_best_count > 0 && one_window_best_start > 0) {
+			delays[i] = one_window_best_start;
 
-		/* configure write delay */
-		write_delay_rst(i);
-		for(j=0; j<delays[i]; j++)
-			write_delay_inc(i);
-		printf(" delay: %02d\n", delays[i]);
+			/* configure write delay */
+			write_delay_rst(i);
+			for(j=0; j<delays[i]; j++)
+				write_delay_inc(i);
+		}
+		if (show)
+			printf(" delay: %02d\n", delays[i]);
 	}
 
 	sdrwloff();
@@ -413,6 +415,106 @@ int write_level(void)
 	return ok;
 }
 
+static void write_level_cdly_range(unsigned int *best_error, int *best_cdly,
+		int cdly_start, int cdly_stop, int cdly_step)
+{
+	int cdly;
+	int cdly_actual = 0;
+	int delays[SDRAM_PHY_MODULES];
+
+	/* scan through the range */
+	ddrphy_cdly_rst_write(1);
+	for (cdly = cdly_start; cdly < cdly_stop; cdly += cdly_step) {
+		/* increment cdly to current value */
+		while (cdly_actual < cdly) {
+			ddrphy_cdly_inc_write(1);
+			cdelay(10);
+			cdly_actual++;
+		}
+
+		/* write level using this delay */
+		if (write_level_scan(delays, 0)) {
+			/* use the mean of delays for error calulation */
+			int delay_mean = 0;
+			for (int i=0; i < SDRAM_PHY_MODULES; ++i) {
+				delay_mean += delays[i];
+			}
+			delay_mean /= SDRAM_PHY_MODULES;
+
+			/* we want it to be in the middle */
+			int ideal_delay = (SDRAM_PHY_DELAYS - ddrphy_half_sys8x_taps_read()) / 2;
+			int error = ideal_delay - delay_mean;
+			if (error < 0)
+				error *= -1;
+
+			if (error < *best_error) {
+				printf("+");
+				*best_cdly = cdly;
+				*best_error = error;
+			} else {
+				printf("-");
+			}
+		} else {
+			printf(".");
+		}
+	}
+}
+
+int write_level(void)
+{
+	int delays[SDRAM_PHY_MODULES];
+	unsigned int best_error = ~0u;
+	int best_cdly = -1;
+	int cdly_range_start;
+	int cdly_range_end;
+	int cdly_range_step;
+
+	printf("cdly scan: ");
+
+	/* Center write leveling by varying cdly. Searching through all possible
+	 * values is slow, but we can use a simple optimization method of iterativly
+	 * scanning smaller ranges with decreasing step */
+	cdly_range_start = 0;
+	cdly_range_end = 512;
+	cdly_range_step = 64;
+	while (cdly_range_step > 0) {
+		printf("|");
+		write_level_cdly_range(&best_error, &best_cdly,
+				cdly_range_start, cdly_range_end, cdly_range_step);
+
+		/* small optimization - stop if we have zero error */
+		if (best_error == 0)
+			break;
+
+		/* use best result as the middle of next range */
+		cdly_range_start = best_cdly - cdly_range_step;
+		cdly_range_end = best_cdly + cdly_range_step + 1;
+		if (cdly_range_start < 0)
+			cdly_range_start = 0;
+		if (cdly_range_end > 512)
+			cdly_range_end = 512;
+
+		cdly_range_step /= 4;
+	}
+	printf("| best: %d\n", best_cdly);
+
+	/* if we found any working delay then set it */
+	if (best_cdly >= 0) {
+		ddrphy_cdly_rst_write(1);
+		for (int i = 0; i < best_cdly; ++i) {
+			ddrphy_cdly_inc_write(1);
+			cdelay(10);
+		}
+	}
+
+	/* re-run write leveling the final time */
+	if (!write_level_scan(delays, 1))
+		return 0;
+
+	return best_cdly >= 0;
+}
+
+
 #endif /*  SDRAM_PHY_WRITE_LEVELING_CAPABLE */
 
 static void read_delay_rst(int module) {
@@ -905,7 +1007,8 @@ int memtest(void)
 #ifdef CSR_SDRAM_BASE
 
 #if defined(SDRAM_PHY_WRITE_LEVELING_CAPABLE) || defined(SDRAM_PHY_READ_LEVELING_CAPABLE)
-int sdrlevel(void)
+
+static void read_leveling(void)
 {
 	int module;
 	int bitslip;
@@ -913,23 +1016,6 @@ int sdrlevel(void)
 	int best_score;
 	int best_bitslip;
 
-	sdrsw();
-
-	for(module=0; module<SDRAM_PHY_MODULES; module++) {
-#ifdef SDRAM_PHY_WRITE_LEVELING_CAPABLE
-		write_delay_rst(module);
-#endif
-		read_delay_rst(module);
-		read_bitslip_rst(module);
-	}
-
-#ifdef SDRAM_PHY_WRITE_LEVELING_CAPABLE
-	if(!write_level())
-		return 0;
-#endif
-
-#ifdef SDRAM_PHY_READ_LEVELING_CAPABLE
-	printf("Read leveling:\n");
 	for(module=0; module<SDRAM_PHY_MODULES; module++) {
 		/* scan possible read windows */
 		best_score = 0;
@@ -960,8 +1046,40 @@ int sdrlevel(void)
 		read_level(module);
 		printf("\n");
 	}
+}
+
+int _write_level_cdly_scan = 1;
+
+int sdrlevel(void)
+{
+	int module;
+	sdrsw();
+
+	for(module=0; module<SDRAM_PHY_MODULES; module++) {
+#ifdef SDRAM_PHY_WRITE_LEVELING_CAPABLE
+		write_delay_rst(module);
+#endif
+		read_delay_rst(module);
+		read_bitslip_rst(module);
+	}
+
+#ifdef SDRAM_PHY_WRITE_LEVELING_CAPABLE
+	printf("Write leveling:\n");
+	if (_write_level_cdly_scan) {
+		if(!write_level())
+			return 0;
+	} else {
+		/* use only the current cdly */
+		int delays[SDRAM_PHY_MODULES];
+		if (!write_level_scan(delays, 1))
+			return 0;
+	}
 #endif
 
+#ifdef SDRAM_PHY_READ_LEVELING_CAPABLE
+	printf("Read leveling:\n");
+	read_leveling();
+#endif
 
 	return 1;
 }
@@ -978,12 +1096,12 @@ int sdrinit(void)
 
 	init_sequence();
 #ifdef CSR_DDRPHY_BASE
-#if CSR_DDRPHY_EN_VTC_ADDR
-	ddrphy_en_vtc_write(0);
-#endif
 #ifdef DDRPHY_CMD_DELAY
 	ddrphy_cdly(DDRPHY_CMD_DELAY);
 #endif
+#if CSR_DDRPHY_EN_VTC_ADDR
+	ddrphy_en_vtc_write(0);
+#endif
 #if defined(SDRAM_PHY_WRITE_LEVELING_CAPABLE) || defined(SDRAM_PHY_READ_LEVELING_CAPABLE)
 	sdrlevel();
 #endif
@@ -1087,6 +1205,12 @@ void sdrmpr(void)
 	sdrhw();
 }
 
+void sdr_cdly_scan(int enabled)
+{
+	printf("Turning cdly scan %s\n", enabled ? "ON" : "OFF");
+	_write_level_cdly_scan = enabled;
+}
+
 #endif
 
 #endif
diff --git a/litex/soc/software/bios/sdram.h b/litex/soc/software/bios/sdram.h
index 15629eba8..a25711919 100644
--- a/litex/soc/software/bios/sdram.h
+++ b/litex/soc/software/bios/sdram.h
@@ -29,6 +29,7 @@ void ddrphy_cdly(unsigned int delay);
 void sdrcal(void);
 void sdrmrwr(char reg, int value);
 void sdrmpr(void);
+void sdr_cdly_scan(int enabled);
 #endif
 
 #endif /* __SDRAM_H */

From aaed4b9475c09220e8af4317c5471ae257fddbaa Mon Sep 17 00:00:00 2001
From: Florent Kermarrec <florent@enjoy-digital.fr>
Date: Sat, 25 Apr 2020 11:00:21 +0200
Subject: [PATCH 20/95] bios/sdram: review/cleanup Command/Clock calibration,
 set window at the start instead of middle.

Working on KC705 that previously required manual adjustment.
---
 litex/soc/software/bios/sdram.c | 21 ++++++++++++---------
 1 file changed, 12 insertions(+), 9 deletions(-)

diff --git a/litex/soc/software/bios/sdram.c b/litex/soc/software/bios/sdram.c
index ff094bd0e..eca275d96 100644
--- a/litex/soc/software/bios/sdram.c
+++ b/litex/soc/software/bios/sdram.c
@@ -441,21 +441,19 @@ static void write_level_cdly_range(unsigned int *best_error, int *best_cdly,
 			}
 			delay_mean /= SDRAM_PHY_MODULES;
 
-			/* we want it to be in the middle */
-			int ideal_delay = (SDRAM_PHY_DELAYS - ddrphy_half_sys8x_taps_read()) / 2;
+			/* we want it to be at the start */
+			int ideal_delay = 1;
 			int error = ideal_delay - delay_mean;
 			if (error < 0)
 				error *= -1;
 
 			if (error < *best_error) {
-				printf("+");
 				*best_cdly = cdly;
 				*best_error = error;
-			} else {
-				printf("-");
 			}
+			printf("1");
 		} else {
-			printf(".");
+			printf("0");
 		}
 	}
 }
@@ -469,14 +467,17 @@ int write_level(void)
 	int cdly_range_end;
 	int cdly_range_step;
 
-	printf("cdly scan: ");
+	printf("Command/Clk scan:\n");
 
 	/* Center write leveling by varying cdly. Searching through all possible
 	 * values is slow, but we can use a simple optimization method of iterativly
 	 * scanning smaller ranges with decreasing step */
 	cdly_range_start = 0;
-	cdly_range_end = 512;
-	cdly_range_step = 64;
+	cdly_range_end = SDRAM_PHY_DELAYS;
+	if (SDRAM_PHY_DELAYS > 32)
+		cdly_range_step = SDRAM_PHY_DELAYS/8;
+	else
+		cdly_range_step = 1;
 	while (cdly_range_step > 0) {
 		printf("|");
 		write_level_cdly_range(&best_error, &best_cdly,
@@ -507,6 +508,8 @@ int write_level(void)
 		}
 	}
 
+	printf("Data scan:\n");
+
 	/* re-run write leveling the final time */
 	if (!write_level_scan(delays, 1))
 		return 0;

From 038e1bc048731e55856999622c3a2c7ff45bb050 Mon Sep 17 00:00:00 2001
From: Florent Kermarrec <florent@enjoy-digital.fr>
Date: Sat, 25 Apr 2020 11:03:04 +0200
Subject: [PATCH 21/95] targets/kc705: manual DDRPHY_CMD_DELAY no longer
 needed.

---
 litex/boards/targets/kc705.py | 1 -
 1 file changed, 1 deletion(-)

diff --git a/litex/boards/targets/kc705.py b/litex/boards/targets/kc705.py
index 35a30c43e..87290e477 100755
--- a/litex/boards/targets/kc705.py
+++ b/litex/boards/targets/kc705.py
@@ -60,7 +60,6 @@ class BaseSoC(SoCCore):
                 sys_clk_freq = sys_clk_freq,
                 cmd_latency  = 1)
             self.add_csr("ddrphy")
-            self.add_constant("DDRPHY_CMD_DELAY", 13)
             self.add_sdram("sdram",
                 phy                     = self.ddrphy,
                 module                  = MT8JTF12864(sys_clk_freq, "1:4"),

From 85a059bf773f9224bdd7106dbc5c8639d20d3af2 Mon Sep 17 00:00:00 2001
From: Florent Kermarrec <florent@enjoy-digital.fr>
Date: Sat, 25 Apr 2020 12:11:10 +0200
Subject: [PATCH 22/95] bios/sdram: add some margin on cdly ideal_delay, do the
 read_leveling even if write_leveling is not optimal.

We need to provide enough information to ease support and understand the issue. The write leveling/read leveling
are doing there best to calibrate the DRAM correctly and memtest gives the final result.
---
 litex/soc/software/bios/sdram.c | 8 +++-----
 1 file changed, 3 insertions(+), 5 deletions(-)

diff --git a/litex/soc/software/bios/sdram.c b/litex/soc/software/bios/sdram.c
index eca275d96..ff4e8f40f 100644
--- a/litex/soc/software/bios/sdram.c
+++ b/litex/soc/software/bios/sdram.c
@@ -442,7 +442,7 @@ static void write_level_cdly_range(unsigned int *best_error, int *best_cdly,
 			delay_mean /= SDRAM_PHY_MODULES;
 
 			/* we want it to be at the start */
-			int ideal_delay = 1;
+			int ideal_delay = 4*SDRAM_PHY_DELAYS/32;
 			int error = ideal_delay - delay_mean;
 			if (error < 0)
 				error *= -1;
@@ -1069,13 +1069,11 @@ int sdrlevel(void)
 #ifdef SDRAM_PHY_WRITE_LEVELING_CAPABLE
 	printf("Write leveling:\n");
 	if (_write_level_cdly_scan) {
-		if(!write_level())
-			return 0;
+		write_level();
 	} else {
 		/* use only the current cdly */
 		int delays[SDRAM_PHY_MODULES];
-		if (!write_level_scan(delays, 1))
-			return 0;
+		write_level_scan(delays, 1);
 	}
 #endif
 

From 43e1a5d67d8d15cb1f2b17ab98a55b07622d6efd Mon Sep 17 00:00:00 2001
From: Florent Kermarrec <florent@enjoy-digital.fr>
Date: Sat, 25 Apr 2020 12:12:27 +0200
Subject: [PATCH 23/95] targets/kcu105: use cmd_latency=1.

---
 litex/boards/targets/kcu105.py | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/litex/boards/targets/kcu105.py b/litex/boards/targets/kcu105.py
index 74023f67c..b632b16cc 100755
--- a/litex/boards/targets/kcu105.py
+++ b/litex/boards/targets/kcu105.py
@@ -65,7 +65,7 @@ class BaseSoC(SoCCore):
                 memtype          = "DDR4",
                 sys_clk_freq     = sys_clk_freq,
                 iodelay_clk_freq = 200e6,
-                cmd_latency      = 0)
+                cmd_latency      = 1)
             self.add_csr("ddrphy")
             self.add_constant("USDDRPHY_DEBUG")
             self.add_sdram("sdram",

From 96e7e6e89a7972a43f5808d8b76691bfa1169bea Mon Sep 17 00:00:00 2001
From: Florent Kermarrec <florent@enjoy-digital.fr>
Date: Sat, 25 Apr 2020 12:51:33 +0200
Subject: [PATCH 24/95] bios/sdram: reduce number of scan loops during cdly
 scan to speed it up.

---
 litex/soc/software/bios/sdram.c | 10 +++++-----
 1 file changed, 5 insertions(+), 5 deletions(-)

diff --git a/litex/soc/software/bios/sdram.c b/litex/soc/software/bios/sdram.c
index ff4e8f40f..00c540ae3 100644
--- a/litex/soc/software/bios/sdram.c
+++ b/litex/soc/software/bios/sdram.c
@@ -310,7 +310,7 @@ static void write_delay_inc(int module) {
 	ddrphy_dly_sel_write(0);
 }
 
-static int write_level_scan(int *delays, int show)
+static int write_level_scan(int *delays, int loops, int show)
 {
 	int i, j, k;
 
@@ -345,7 +345,7 @@ static int write_level_scan(int *delays, int show)
 #if SDRAM_PHY_DELAYS > 32
 			show_iter = (j%16 == 0) && show;
 #endif
-			for (k=0; k<128; k++) {
+			for (k=0; k<loops; k++) {
 				ddrphy_wlevel_strobe_write(1);
 				cdelay(10);
 				csr_rd_buf_uint8(sdram_dfii_pix_rddata_addr[0],
@@ -433,7 +433,7 @@ static void write_level_cdly_range(unsigned int *best_error, int *best_cdly,
 		}
 
 		/* write level using this delay */
-		if (write_level_scan(delays, 0)) {
+		if (write_level_scan(delays, 8, 0)) {
 			/* use the mean of delays for error calulation */
 			int delay_mean = 0;
 			for (int i=0; i < SDRAM_PHY_MODULES; ++i) {
@@ -511,7 +511,7 @@ int write_level(void)
 	printf("Data scan:\n");
 
 	/* re-run write leveling the final time */
-	if (!write_level_scan(delays, 1))
+	if (!write_level_scan(delays, 128, 1))
 		return 0;
 
 	return best_cdly >= 0;
@@ -1073,7 +1073,7 @@ int sdrlevel(void)
 	} else {
 		/* use only the current cdly */
 		int delays[SDRAM_PHY_MODULES];
-		write_level_scan(delays, 1);
+		write_level_scan(delays, 128, 1);
 	}
 #endif
 

From 2efd939d06ba7903892fc5a742838b49ab1728fb Mon Sep 17 00:00:00 2001
From: Florent Kermarrec <florent@enjoy-digital.fr>
Date: Sun, 26 Apr 2020 16:26:15 +0200
Subject: [PATCH 25/95] serv: fix ibus/dbus byte/word addressing inconsistency,
 add missing ibus.sel (thanks @GregDavill).

---
 litex/soc/cores/cpu/serv/core.py | 8 ++++----
 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/litex/soc/cores/cpu/serv/core.py b/litex/soc/cores/cpu/serv/core.py
index 8128fda5a..ab73cea22 100644
--- a/litex/soc/cores/cpu/serv/core.py
+++ b/litex/soc/cores/cpu/serv/core.py
@@ -36,7 +36,7 @@ class SERV(CPU):
         self.reset     = Signal()
         self.ibus      = ibus = wishbone.Interface()
         self.dbus      = dbus = wishbone.Interface()
-        self.buses     = [self.ibus, dbus]
+        self.buses     = [ibus, dbus]
         self.interrupt = Signal(32)
 
         # # #
@@ -50,14 +50,13 @@ class SERV(CPU):
             i_i_timer_irq = 0,
 
             # ibus
-            o_o_ibus_adr = ibus.adr,
+            o_o_ibus_adr = Cat(Signal(2), ibus.adr),
             o_o_ibus_cyc = ibus.cyc,
             i_i_ibus_rdt = ibus.dat_r,
             i_i_ibus_ack = ibus.ack,
 
-
             # dbus
-            o_o_dbus_adr = dbus.adr,
+            o_o_dbus_adr = Cat(Signal(2), dbus.adr),
             o_o_dbus_dat = dbus.dat_w,
             o_o_dbus_sel = dbus.sel,
             o_o_dbus_we  = dbus.we,
@@ -67,6 +66,7 @@ class SERV(CPU):
         )
         self.comb += [
             ibus.stb.eq(ibus.cyc),
+            ibus.sel.eq(0xf),
             dbus.stb.eq(dbus.cyc),
         ]
 

From 1f9db583fd47c82d42e51058774d3654fae16883 Mon Sep 17 00:00:00 2001
From: Florent Kermarrec <florent@enjoy-digital.fr>
Date: Sun, 26 Apr 2020 21:05:47 +0200
Subject: [PATCH 26/95] serv/cores: fix verilog top level (use serv_rf_top
 instead of serv_top), working :).

---
 litex/soc/cores/cpu/serv/core.py | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/litex/soc/cores/cpu/serv/core.py b/litex/soc/cores/cpu/serv/core.py
index ab73cea22..e24853c4a 100644
--- a/litex/soc/cores/cpu/serv/core.py
+++ b/litex/soc/cores/cpu/serv/core.py
@@ -88,4 +88,4 @@ class SERV(CPU):
 
     def do_finalize(self):
         assert hasattr(self, "reset_address")
-        self.specials += Instance("serv_top", **self.cpu_params)
+        self.specials += Instance("serv_rf_top", **self.cpu_params)

From 71778ad226858624494419b5b1cc538e91a7194a Mon Sep 17 00:00:00 2001
From: Florent Kermarrec <florent@enjoy-digital.fr>
Date: Mon, 27 Apr 2020 10:27:44 +0200
Subject: [PATCH 27/95] serv: update copyrights (Greg Davill found the
 typos/issues).

---
 litex/soc/cores/cpu/serv/core.py | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/litex/soc/cores/cpu/serv/core.py b/litex/soc/cores/cpu/serv/core.py
index e24853c4a..4cda01d80 100644
--- a/litex/soc/cores/cpu/serv/core.py
+++ b/litex/soc/cores/cpu/serv/core.py
@@ -1,5 +1,5 @@
 # This file is Copyright (c) 2020 Florent Kermarrec <florent@enjoy-digital.fr>
-
+# This file is Copyright (c) 2020 Greg Davill <greg.davill@gmail.com>
 # License: BSD
 
 import os

From 642c4b303606e13f2d4c8ced0e78a4b651f482b9 Mon Sep 17 00:00:00 2001
From: Greg Davill <greg.davill@gmail.com>
Date: Mon, 27 Apr 2020 20:10:25 +0930
Subject: [PATCH 28/95] build/trellis: add verilog_read -defer option to yosys
 script

---
 litex/build/lattice/trellis.py | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/litex/build/lattice/trellis.py b/litex/build/lattice/trellis.py
index a9ae49be4..fa19b9192 100644
--- a/litex/build/lattice/trellis.py
+++ b/litex/build/lattice/trellis.py
@@ -49,7 +49,10 @@ def _build_lpf(named_sc, named_pc, build_name):
 # Yosys/Nextpnr Helpers/Templates ------------------------------------------------------------------
 
 _yosys_template = [
+    "verilog_defaults -push",
+    "verilog_defaults -add -defer",
     "{read_files}",
+    "verilog_defaults -pop",
     "attrmap -tocase keep -imap keep=\"true\" keep=1 -imap keep=\"false\" keep=0 -remove keep=0",
     "synth_ecp5 -abc9 {nwl} -json {build_name}.json -top {build_name}",
 ]

From c4c891dec51a77560f8660967f6666b170b517dc Mon Sep 17 00:00:00 2001
From: Florent Kermarrec <florent@enjoy-digital.fr>
Date: Mon, 27 Apr 2020 13:17:53 +0200
Subject: [PATCH 29/95] build/icestorm: add verilog_read -defer option to yosys
 script (changes similar the ones applied to trellis).

---
 litex/build/lattice/icestorm.py | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/litex/build/lattice/icestorm.py b/litex/build/lattice/icestorm.py
index a084a9980..2822a9b53 100644
--- a/litex/build/lattice/icestorm.py
+++ b/litex/build/lattice/icestorm.py
@@ -38,7 +38,10 @@ def _build_pre_pack(vns, clocks):
 # Yosys/Nextpnr Helpers/Templates ------------------------------------------------------------------
 
 _yosys_template = [
+    "verilog_defaults -push",
+    "verilog_defaults -add -defer",
     "{read_files}",
+    "verilog_defaults -pop",
     "attrmap -tocase keep -imap keep=\"true\" keep=1 -imap keep=\"false\" keep=0 -remove keep=0",
     "synth_ice40 {synth_opts} -json {build_name}.json -top {build_name} -dsp",
 ]

From fb9e369a193ba43a46d0e5651859b1809e8ab9b6 Mon Sep 17 00:00:00 2001
From: Florent Kermarrec <florent@enjoy-digital.fr>
Date: Mon, 27 Apr 2020 13:26:45 +0200
Subject: [PATCH 30/95] serv: connect reset.

---
 litex/soc/cores/cpu/serv/core.py | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/litex/soc/cores/cpu/serv/core.py b/litex/soc/cores/cpu/serv/core.py
index 4cda01d80..c919fb532 100644
--- a/litex/soc/cores/cpu/serv/core.py
+++ b/litex/soc/cores/cpu/serv/core.py
@@ -44,7 +44,7 @@ class SERV(CPU):
         self.cpu_params = dict(
             # clock / reset
             i_clk   = ClockSignal(),
-            i_i_rst = ResetSignal(),
+            i_i_rst = ResetSignal() | self.reset,
 
             # timer irq
             i_i_timer_irq = 0,

From 1d1a4ecd28aeb3196e7ae2adeb97e25204613a3a Mon Sep 17 00:00:00 2001
From: Florent Kermarrec <florent@enjoy-digital.fr>
Date: Mon, 27 Apr 2020 13:46:12 +0200
Subject: [PATCH 31/95] software/irq: cleanup and make explicit that irqs are
 not supported with Microwatt and SERV, fix compilation warning.

---
 litex/soc/software/bios/isr.c         |  6 ++---
 litex/soc/software/include/base/irq.h | 32 +++++++++++++--------------
 2 files changed, 19 insertions(+), 19 deletions(-)

diff --git a/litex/soc/software/bios/isr.c b/litex/soc/software/bios/isr.c
index 971bd37b6..f33cdac43 100644
--- a/litex/soc/software/bios/isr.c
+++ b/litex/soc/software/bios/isr.c
@@ -8,7 +8,7 @@
 #include <uart.h>
 #include <stdio.h>
 
- 
+
 #if defined(__blackparrot__) /*TODO: Update this function for BP*/ //
 
 void isr(void);
@@ -21,7 +21,7 @@ void isr(void)
     onetime++;
   }
 }
-#elif defined(__rocket__) 
+#elif defined(__rocket__)
 void plic_init(void);
 void plic_init(void)
 {
@@ -65,7 +65,7 @@ void isr(void)
 void isr(void);
 void isr(void)
 {
-	unsigned int irqs;
+	__attribute__((unused)) unsigned int irqs;
 
 	irqs = irq_pending() & irq_getmask();
 
diff --git a/litex/soc/software/include/base/irq.h b/litex/soc/software/include/base/irq.h
index 00dad8a2b..6a2f73944 100644
--- a/litex/soc/software/include/base/irq.h
+++ b/litex/soc/software/include/base/irq.h
@@ -72,11 +72,11 @@ static inline unsigned int irq_getie(void)
 #elif defined (__rocket__)
 	return (csrr(mstatus) & CSR_MSTATUS_MIE) != 0;
 #elif defined (__microwatt__)
-	return 0; // FIXME
-#elif defined (__blackparrot__) 
-	return (csrr(mstatus) & CSR_MSTATUS_MIE) != 0;//TODO
+	return 0; /* No interrupt support on Microwatt */
+#elif defined (__blackparrot__)
+	return (csrr(mstatus) & CSR_MSTATUS_MIE) != 0; /* FIXME */
 #elif defined (__serv__)
-	return 0; /* FIXME */
+	return 0; /* No interrupt support on SERV */
 #else
 #error Unsupported architecture
 #endif
@@ -103,11 +103,11 @@ static inline void irq_setie(unsigned int ie)
 #elif defined (__rocket__)
 	if(ie) csrs(mstatus,CSR_MSTATUS_MIE); else csrc(mstatus,CSR_MSTATUS_MIE);
 #elif defined (__microwatt__)
-	// FIXME
+	/* No interrupt support on Microwatt */
 #elif defined (__blackparrot__)
-	if(ie) csrs(mstatus,CSR_MSTATUS_MIE); else csrc(mstatus,CSR_MSTATUS_MIE);//TODO:BP
+	if(ie) csrs(mstatus,CSR_MSTATUS_MIE); else csrc(mstatus,CSR_MSTATUS_MIE); /* FIXME */
 #elif defined (__serv__)
-	/* FIXME */
+	/* No interrupt support on SERV */
 #else
 #error Unsupported architecture
 #endif
@@ -136,11 +136,11 @@ static inline unsigned int irq_getmask(void)
 #elif defined (__rocket__)
 	return *((unsigned int *)PLIC_ENABLED) >> 1;
 #elif defined (__microwatt__)
-	return 0; // FIXME
+	return 0; /* No interrupt support on Microwatt */
 #elif defined (__blackparrot__)
-	//TODO:BP
-#elif defined (__serv__)
 	return 0; /* FIXME */
+#elif defined (__serv__)
+	return 0; /* No interrupt support on SERV */
 #else
 #error Unsupported architecture
 #endif
@@ -163,11 +163,11 @@ static inline void irq_setmask(unsigned int mask)
 #elif defined (__rocket__)
 	*((unsigned int *)PLIC_ENABLED) = mask << 1;
 #elif defined (__microwatt__)
-	// FIXME
+	/* No interrupt support on Microwatt */
 #elif defined (__blackparrot__)
-	//TODO:BP
-#elif defined (__serv__)
 	/* FIXME */
+#elif defined (__serv__)
+	/* No interrupt support on SERV */
 #else
 #error Unsupported architecture
 #endif
@@ -194,11 +194,11 @@ static inline unsigned int irq_pending(void)
 #elif defined (__rocket__)
 	return *((unsigned int *)PLIC_PENDING) >> 1;
 #elif defined (__microwatt__)
-	return 0; // FIXME
+	return 0; /* No interrupt support on Microwatt */
 #elif defined (__blackparrot__)
-	return csr_readl(PLIC_PENDING) >> 1;//TODO:BP
+	return csr_readl(PLIC_PENDING) >> 1; /* FIXME */
 #elif defined (__serv__)
-	return 0;/* FIXME */
+	return 0; /* No interrupt support on SERV */
 #else
 #error Unsupported architecture
 #endif

From 9460e048ec782900c3199ebded0e57128c8216ac Mon Sep 17 00:00:00 2001
From: Florent Kermarrec <florent@enjoy-digital.fr>
Date: Mon, 27 Apr 2020 15:08:48 +0200
Subject: [PATCH 32/95] tools/litex_sim: use similar analyzer configuration
 than wiki.

---
 litex/tools/litex_sim.py | 15 ++++++++++++---
 1 file changed, 12 insertions(+), 3 deletions(-)

diff --git a/litex/tools/litex_sim.py b/litex/tools/litex_sim.py
index 7a526f83a..987681d33 100755
--- a/litex/tools/litex_sim.py
+++ b/litex/tools/litex_sim.py
@@ -270,10 +270,19 @@ class SimSoC(SoCSDRAM):
         # Analyzer ---------------------------------------------------------------------------------
         if with_analyzer:
             analyzer_signals = [
-                self.cpu.ibus,
-                self.cpu.dbus
+                self.cpu.ibus.stb,
+                self.cpu.ibus.cyc,
+                self.cpu.ibus.adr,
+                self.cpu.ibus.we,
+                self.cpu.ibus.ack,
+                self.cpu.ibus.sel,
+                self.cpu.ibus.dat_w,
+                self.cpu.ibus.dat_r,
             ]
-            self.submodules.analyzer = LiteScopeAnalyzer(analyzer_signals, 512)
+            self.submodules.analyzer = LiteScopeAnalyzer(analyzer_signals,
+                depth        = 512,
+                clock_domain = "sys",
+                csr_csv      = "analyzer.csv")
             self.add_csr("analyzer")
 
 # Build --------------------------------------------------------------------------------------------

From 3892d7a90a7c57bd58321f444c51dfae95d9f106 Mon Sep 17 00:00:00 2001
From: Franck Jullien <franck.jullien@gmail.com>
Date: Sat, 25 Apr 2020 23:22:38 +0200
Subject: [PATCH 33/95] bios: print memory usage

Print memory usage during the compilation of bios.elf.
---
 litex/soc/software/bios/Makefile |  1 +
 litex/soc/software/memusage.py   | 63 ++++++++++++++++++++++++++++++++
 2 files changed, 64 insertions(+)
 create mode 100644 litex/soc/software/memusage.py

diff --git a/litex/soc/software/bios/Makefile b/litex/soc/software/bios/Makefile
index 66be372c7..12510a712 100755
--- a/litex/soc/software/bios/Makefile
+++ b/litex/soc/software/bios/Makefile
@@ -13,6 +13,7 @@ endif
 OBJECTS=isr.o sdram.o sdcard.o main.o boot-helper-$(CPU).o boot.o
 
 all: bios.bin
+	$(PYTHON) -m litex.soc.software.memusage bios.elf $(CURDIR)/../include/generated/regions.ld $(TRIPLE)
 
 %.bin: %.elf
 	$(OBJCOPY) -O binary $< $@
diff --git a/litex/soc/software/memusage.py b/litex/soc/software/memusage.py
new file mode 100644
index 000000000..3c4dc70a8
--- /dev/null
+++ b/litex/soc/software/memusage.py
@@ -0,0 +1,63 @@
+#!/usr/bin/env python3
+
+# This file is Copyright (c) 2020 Franck Jullien <franck.jullien@gmail.com>
+# License: BSD
+
+import subprocess
+import argparse
+
+def print_usage(bios,regions, triple):
+    rom_usage = 0
+    ram_usage = 0
+
+    readelf = triple + "-readelf"
+
+    result = subprocess.run([readelf, '-e', '-W', bios], stdout=subprocess.PIPE)
+    result = result.stdout.decode('utf-8')
+    result = result.split('\n')
+
+    with open(regions, "r") as regfile:
+        for line in regfile:
+           if line == 0:
+               break
+           if 'rom' in line:
+               rom_size = int(line.split(' ')[-1], 16)
+           if 'sram' in line:
+               ram_size = int(line.split(' ')[-1], 16)
+
+    for line in result:
+        if '.text' in line:
+            if 'PROGBITS' in line:
+                tokens = list(filter(None,line.split(' ')))
+                rom_usage += int(tokens[6], 16)
+        if '.rodata' in line:
+            if 'PROGBITS' in line:
+                tokens = list(filter(None,line.split(' ')))
+                rom_usage += int(tokens[6], 16)
+        if '.data' in line:
+            if 'PROGBITS' in line:
+                tokens = list(filter(None,line.split(' ')))
+                rom_usage += int(tokens[6], 16)
+        if '.commands' in line:
+            if 'PROGBITS' in line:
+                tokens = list(filter(None,line.split(' ')))
+                rom_usage += int(tokens[6], 16)
+        if '.bss' in line:
+            if 'NOBITS' in line:
+                tokens = list(filter(None,line.split(' ')))
+                ram_usage += int(tokens[6], 16)
+
+    print("\nROM usage: {:.2f}KiB \t({:.2f}%)".format(rom_usage / 1024.0, rom_usage / rom_size * 100.0))
+    print("RAM usage: {:.2f}KiB \t({:.2f}%)\n".format(ram_usage / 1024.0, ram_usage / ram_size * 100.0))
+
+def main():
+    parser = argparse.ArgumentParser(description="Print bios memory usage")
+    parser.add_argument("input", help="input file")
+    parser.add_argument("regions", help="regions definitions")
+    parser.add_argument("triple", help="toolchain triple")
+    args = parser.parse_args()
+    print_usage(args.input, args.regions, args.triple)
+
+
+if __name__ == "__main__":
+    main()

From 4dece4ce24972fb2652ee6183bed1cec9ab40672 Mon Sep 17 00:00:00 2001
From: Florent Kermarrec <florent@enjoy-digital.fr>
Date: Mon, 27 Apr 2020 19:06:16 +0200
Subject: [PATCH 34/95] soc/cpu: simplify integration of CPU without interrupts
 (and automatically use UART_POLLING mode in this case).

---
 litex/soc/cores/cpu/serv/core.py      |  1 -
 litex/soc/integration/soc.py          | 16 +++++++++++-----
 litex/soc/integration/soc_core.py     |  3 ---
 litex/soc/software/bios/boot.c        |  3 +++
 litex/soc/software/bios/isr.c         | 14 ++++++++++----
 litex/soc/software/bios/main.c        |  3 ++-
 litex/soc/software/include/base/irq.h | 25 +++++--------------------
 7 files changed, 31 insertions(+), 34 deletions(-)

diff --git a/litex/soc/cores/cpu/serv/core.py b/litex/soc/cores/cpu/serv/core.py
index c919fb532..4fb2f0a49 100644
--- a/litex/soc/cores/cpu/serv/core.py
+++ b/litex/soc/cores/cpu/serv/core.py
@@ -37,7 +37,6 @@ class SERV(CPU):
         self.ibus      = ibus = wishbone.Interface()
         self.dbus      = dbus = wishbone.Interface()
         self.buses     = [ibus, dbus]
-        self.interrupt = Signal(32)
 
         # # #
 
diff --git a/litex/soc/integration/soc.py b/litex/soc/integration/soc.py
index b06abdef7..dcea829aa 100644
--- a/litex/soc/integration/soc.py
+++ b/litex/soc/integration/soc.py
@@ -723,7 +723,7 @@ class SoC(Module):
             raise
         self.constants[name] = SoCConstant(value)
 
-    def add_config(self, name, value):
+    def add_config(self, name, value=None):
         name = "CONFIG_" + name
         if isinstance(value, str):
             self.add_constant(name + "_" + value)
@@ -784,8 +784,10 @@ class SoC(Module):
             for n, cpu_bus in enumerate(self.cpu.buses):
                 self.bus.add_master(name="cpu_bus{}".format(n), master=cpu_bus)
             self.csr.add("cpu", use_loc_if_exists=True)
-            for name, loc in self.cpu.interrupts.items():
-                self.irq.add(name, loc)
+            if hasattr(self.cpu, "interrupt"):
+                for name, loc in self.cpu.interrupts.items():
+                    self.irq.add(name, loc)
+                self.add_config("CPU_HAS_INTERRUPT")
             if hasattr(self, "ctrl"):
                 self.comb += self.cpu.reset.eq(self.ctrl.reset)
             self.add_config("CPU_RESET_ADDR", reset_address)
@@ -797,7 +799,8 @@ class SoC(Module):
         self.check_if_exists(name)
         setattr(self.submodules, name, Timer())
         self.csr.add(name, use_loc_if_exists=True)
-        self.irq.add(name, use_loc_if_exists=True)
+        if hasattr(self.cpu, "interrupt"):
+            self.irq.add(name, use_loc_if_exists=True)
 
     # SoC finalization -----------------------------------------------------------------------------
     def do_finalize(self):
@@ -974,7 +977,10 @@ class LiteXSoC(SoC):
 
         self.csr.add("uart_phy", use_loc_if_exists=True)
         self.csr.add("uart", use_loc_if_exists=True)
-        self.irq.add("uart", use_loc_if_exists=True)
+        if hasattr(self.cpu, "interrupt"):
+            self.irq.add("uart", use_loc_if_exists=True)
+        else:
+            self.add_constant("UART_POLLING")
 
     # Add SDRAM ------------------------------------------------------------------------------------
     def add_sdram(self, name, phy, module, origin, size=None,
diff --git a/litex/soc/integration/soc_core.py b/litex/soc/integration/soc_core.py
index ab8704ced..3eb0016c7 100644
--- a/litex/soc/integration/soc_core.py
+++ b/litex/soc/integration/soc_core.py
@@ -132,9 +132,6 @@ class SoCCore(LiteXSoC):
         self.cpu_type                   = cpu_type
         self.cpu_variant                = cpu_variant
 
-        if cpu_type == "serv":
-            self.add_constant("UART_POLLING") # FIXME: use UART in polling mode for SERV bringup
-
         self.integrated_rom_size        = integrated_rom_size
         self.integrated_rom_initialized = integrated_rom_init != []
         self.integrated_sram_size       = integrated_sram_size
diff --git a/litex/soc/software/bios/boot.c b/litex/soc/software/bios/boot.c
index c6c8b9583..08b3be4a8 100644
--- a/litex/soc/software/bios/boot.c
+++ b/litex/soc/software/bios/boot.c
@@ -18,6 +18,7 @@
 
 #include <generated/mem.h>
 #include <generated/csr.h>
+#include <generated/soc.h>
 
 #ifdef CSR_ETHMAC_BASE
 #include <net/microudp.h>
@@ -38,8 +39,10 @@ static void __attribute__((noreturn)) boot(unsigned long r1, unsigned long r2, u
 	printf("Executing booted program at 0x%08x\n\n", addr);
 	printf("--============= \e[1mLiftoff!\e[0m ===============--\n");
 	uart_sync();
+#ifdef CONFIG_CPU_HAS_INTERRUPT
 	irq_setmask(0);
 	irq_setie(0);
+#endif
 /* FIXME: understand why flushing icache on Vexriscv make boot fail  */
 #ifndef __vexriscv__
 	flush_cpu_icache();
diff --git a/litex/soc/software/bios/isr.c b/litex/soc/software/bios/isr.c
index f33cdac43..0044f3d16 100644
--- a/litex/soc/software/bios/isr.c
+++ b/litex/soc/software/bios/isr.c
@@ -4,14 +4,16 @@
 
 
 #include <generated/csr.h>
+#include <generated/soc.h>
 #include <irq.h>
 #include <uart.h>
 #include <stdio.h>
 
+void isr(void);
+
+#ifdef CONFIG_CPU_HAS_INTERRUPT
 
 #if defined(__blackparrot__) /*TODO: Update this function for BP*/ //
-
-void isr(void);
 void isr(void)
 {
   static int onetime = 0;
@@ -36,7 +38,6 @@ void plic_init(void)
 	*((unsigned int *)PLIC_THRSHLD) = 0;
 }
 
-void isr(void);
 void isr(void)
 {
 	unsigned int claim;
@@ -62,7 +63,6 @@ void isr(void)
 	}
 }
 #else
-void isr(void);
 void isr(void)
 {
 	__attribute__((unused)) unsigned int irqs;
@@ -75,3 +75,9 @@ void isr(void)
 #endif
 }
 #endif
+
+#else
+
+void isr(void){};
+
+#endif
diff --git a/litex/soc/software/bios/main.c b/litex/soc/software/bios/main.c
index 08fc6faa9..b6501edbb 100644
--- a/litex/soc/software/bios/main.c
+++ b/litex/soc/software/bios/main.c
@@ -616,9 +616,10 @@ int main(int i, char **c)
 {
 	char buffer[64];
 	int sdr_ok;
-
+#ifdef CONFIG_CPU_HAS_INTERRUPT
 	irq_setmask(0);
 	irq_setie(1);
+#endif
 	uart_init();
 
 	printf("\n");
diff --git a/litex/soc/software/include/base/irq.h b/litex/soc/software/include/base/irq.h
index 6a2f73944..9fd8e1805 100644
--- a/litex/soc/software/include/base/irq.h
+++ b/litex/soc/software/include/base/irq.h
@@ -7,6 +7,9 @@ extern "C" {
 
 #include <system.h>
 #include <generated/csr.h>
+#include <generated/soc.h>
+
+#ifdef CONFIG_CPU_HAS_INTERRUPT
 
 #ifdef __picorv32__
 // PicoRV32 has a very limited interrupt support, implemented via custom
@@ -71,12 +74,8 @@ static inline unsigned int irq_getie(void)
 	return (csrr(mstatus) & CSR_MSTATUS_MIE) != 0;
 #elif defined (__rocket__)
 	return (csrr(mstatus) & CSR_MSTATUS_MIE) != 0;
-#elif defined (__microwatt__)
-	return 0; /* No interrupt support on Microwatt */
 #elif defined (__blackparrot__)
 	return (csrr(mstatus) & CSR_MSTATUS_MIE) != 0; /* FIXME */
-#elif defined (__serv__)
-	return 0; /* No interrupt support on SERV */
 #else
 #error Unsupported architecture
 #endif
@@ -102,12 +101,8 @@ static inline void irq_setie(unsigned int ie)
 	if(ie) csrs(mstatus,CSR_MSTATUS_MIE); else csrc(mstatus,CSR_MSTATUS_MIE);
 #elif defined (__rocket__)
 	if(ie) csrs(mstatus,CSR_MSTATUS_MIE); else csrc(mstatus,CSR_MSTATUS_MIE);
-#elif defined (__microwatt__)
-	/* No interrupt support on Microwatt */
 #elif defined (__blackparrot__)
 	if(ie) csrs(mstatus,CSR_MSTATUS_MIE); else csrc(mstatus,CSR_MSTATUS_MIE); /* FIXME */
-#elif defined (__serv__)
-	/* No interrupt support on SERV */
 #else
 #error Unsupported architecture
 #endif
@@ -135,12 +130,8 @@ static inline unsigned int irq_getmask(void)
 	return mask;
 #elif defined (__rocket__)
 	return *((unsigned int *)PLIC_ENABLED) >> 1;
-#elif defined (__microwatt__)
-	return 0; /* No interrupt support on Microwatt */
 #elif defined (__blackparrot__)
 	return 0; /* FIXME */
-#elif defined (__serv__)
-	return 0; /* No interrupt support on SERV */
 #else
 #error Unsupported architecture
 #endif
@@ -162,12 +153,8 @@ static inline void irq_setmask(unsigned int mask)
 	asm volatile ("csrw %0, %1" :: "i"(CSR_IRQ_MASK), "r"(mask));
 #elif defined (__rocket__)
 	*((unsigned int *)PLIC_ENABLED) = mask << 1;
-#elif defined (__microwatt__)
-	/* No interrupt support on Microwatt */
 #elif defined (__blackparrot__)
 	/* FIXME */
-#elif defined (__serv__)
-	/* No interrupt support on SERV */
 #else
 #error Unsupported architecture
 #endif
@@ -193,12 +180,8 @@ static inline unsigned int irq_pending(void)
 	return pending;
 #elif defined (__rocket__)
 	return *((unsigned int *)PLIC_PENDING) >> 1;
-#elif defined (__microwatt__)
-	return 0; /* No interrupt support on Microwatt */
 #elif defined (__blackparrot__)
 	return csr_readl(PLIC_PENDING) >> 1; /* FIXME */
-#elif defined (__serv__)
-	return 0; /* No interrupt support on SERV */
 #else
 #error Unsupported architecture
 #endif
@@ -208,4 +191,6 @@ static inline unsigned int irq_pending(void)
 }
 #endif
 
+#endif
+
 #endif /* __IRQ_H */

From f71014b9fb09ae649c1aa58e9575b995eaa9702d Mon Sep 17 00:00:00 2001
From: shuffle2 <godisgovernment@gmail.com>
Date: Mon, 27 Apr 2020 11:14:18 -0700
Subject: [PATCH 35/95] diamond: fix include paths

include paths given via tcl script need semicolon separators and forward slash as directory separator (even on windows)
---
 litex/build/lattice/diamond.py | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/litex/build/lattice/diamond.py b/litex/build/lattice/diamond.py
index e3f91133f..cf44d096b 100644
--- a/litex/build/lattice/diamond.py
+++ b/litex/build/lattice/diamond.py
@@ -68,8 +68,8 @@ def _build_tcl(device, sources, vincpaths, build_name):
     ]))
 
     # Add include paths
-    for path in vincpaths:
-        tcl.append("prj_impl option {include path} {\"" + path + "\"}")
+    vincpath = ';'.join(map(lambda x: x.replace('\\', '/'), vincpaths))
+    tcl.append("prj_impl option {include path} {\"" + vincpath + "\"}")
 
     # Add sources
     for filename, language, library in sources:
@@ -201,4 +201,4 @@ class LatticeDiamondToolchain:
         from_.attr.add("keep")
         to.attr.add("keep")
         if (to, from_) not in self.false_paths:
-            self.false_paths.add((from_, to))
\ No newline at end of file
+            self.false_paths.add((from_, to))

From 467fee3e236e21adb0debe6bd4be07bda4558b4d Mon Sep 17 00:00:00 2001
From: Florent Kermarrec <florent@enjoy-digital.fr>
Date: Mon, 27 Apr 2020 23:08:15 +0200
Subject: [PATCH 36/95] soc/cpu: rename cpu.buses to cpu.periph_buses.

---
 litex/soc/cores/cpu/blackparrot/core.py | 12 ++++++------
 litex/soc/cores/cpu/lm32/core.py        | 14 +++++++-------
 litex/soc/cores/cpu/microwatt/core.py   | 12 ++++++------
 litex/soc/cores/cpu/minerva/core.py     | 14 +++++++-------
 litex/soc/cores/cpu/mor1kx/core.py      | 14 +++++++-------
 litex/soc/cores/cpu/picorv32/core.py    | 14 +++++++-------
 litex/soc/cores/cpu/rocket/core.py      |  2 +-
 litex/soc/cores/cpu/serv/core.py        | 12 ++++++------
 litex/soc/cores/cpu/vexriscv/core.py    |  2 +-
 litex/soc/integration/soc.py            |  2 +-
 10 files changed, 49 insertions(+), 49 deletions(-)

diff --git a/litex/soc/cores/cpu/blackparrot/core.py b/litex/soc/cores/cpu/blackparrot/core.py
index 897664892..fe220cf2e 100644
--- a/litex/soc/cores/cpu/blackparrot/core.py
+++ b/litex/soc/cores/cpu/blackparrot/core.py
@@ -73,12 +73,12 @@ class BlackParrotRV64(CPU):
     def __init__(self, platform, variant="standard"):
         assert variant in CPU_VARIANTS, "Unsupported variant %s" % variant
 
-        self.platform  = platform
-        self.variant   = variant
-        self.reset     = Signal()
-        self.interrupt = Signal(4)
-        self.idbus     = idbus = wishbone.Interface(data_width=64, adr_width=37)
-        self.buses     = [idbus]
+        self.platform     = platform
+        self.variant      = variant
+        self.reset        = Signal()
+        self.interrupt    = Signal(4)
+        self.idbus        = idbus = wishbone.Interface(data_width=64, adr_width=37)
+        self.periph_buses = [idbus]
 
         # # #
 
diff --git a/litex/soc/cores/cpu/lm32/core.py b/litex/soc/cores/cpu/lm32/core.py
index 9ef8333b9..e1b6bce39 100644
--- a/litex/soc/cores/cpu/lm32/core.py
+++ b/litex/soc/cores/cpu/lm32/core.py
@@ -34,13 +34,13 @@ class LM32(CPU):
 
     def __init__(self, platform, variant="standard"):
         assert variant in CPU_VARIANTS, "Unsupported variant %s" % variant
-        self.platform  = platform
-        self.variant   = variant
-        self.reset     = Signal()
-        self.ibus      = i = wishbone.Interface()
-        self.dbus      = d = wishbone.Interface()
-        self.interrupt = Signal(32)
-        self.buses     = [i, d]
+        self.platform     = platform
+        self.variant      = variant
+        self.reset        = Signal()
+        self.ibus         = i = wishbone.Interface()
+        self.dbus         = d = wishbone.Interface()
+        self.interrupt    = Signal(32)
+        self.periph_buses = [i, d]
 
         # # #
 
diff --git a/litex/soc/cores/cpu/microwatt/core.py b/litex/soc/cores/cpu/microwatt/core.py
index 584ad4450..17b6e3eaa 100644
--- a/litex/soc/cores/cpu/microwatt/core.py
+++ b/litex/soc/cores/cpu/microwatt/core.py
@@ -41,12 +41,12 @@ class Microwatt(CPU):
 
     def __init__(self, platform, variant="standard"):
         assert variant in CPU_VARIANTS, "Unsupported variant %s" % variant
-        self.platform = platform
-        self.variant  = variant
-        self.reset    = Signal()
-        self.wb_insn  = wb_insn = wishbone.Interface(data_width=64, adr_width=28)
-        self.wb_data  = wb_data = wishbone.Interface(data_width=64, adr_width=28)
-        self.buses    = [wb_insn, wb_data]
+        self.platform     = platform
+        self.variant      = variant
+        self.reset        = Signal()
+        self.wb_insn      = wb_insn = wishbone.Interface(data_width=64, adr_width=28)
+        self.wb_data      = wb_data = wishbone.Interface(data_width=64, adr_width=28)
+        self.periph_buses = [wb_insn, wb_data]
 
         # # #
 
diff --git a/litex/soc/cores/cpu/minerva/core.py b/litex/soc/cores/cpu/minerva/core.py
index 2edbfe7ee..1603fea74 100644
--- a/litex/soc/cores/cpu/minerva/core.py
+++ b/litex/soc/cores/cpu/minerva/core.py
@@ -31,13 +31,13 @@ class Minerva(CPU):
 
     def __init__(self, platform, variant="standard"):
         assert variant in CPU_VARIANTS, "Unsupported variant %s" % variant
-        self.platform  = platform
-        self.variant   = variant
-        self.reset     = Signal()
-        self.ibus      = wishbone.Interface()
-        self.dbus      = wishbone.Interface()
-        self.buses     = [self.ibus, self.dbus]
-        self.interrupt = Signal(32)
+        self.platform     = platform
+        self.variant      = variant
+        self.reset        = Signal()
+        self.ibus         = wishbone.Interface()
+        self.dbus         = wishbone.Interface()
+        self.periph_buses = [self.ibus, self.dbus]
+        self.interrupt    = Signal(32)
 
         # TODO: create variants
         self.with_icache = False
diff --git a/litex/soc/cores/cpu/mor1kx/core.py b/litex/soc/cores/cpu/mor1kx/core.py
index c82b6e55d..59ece9ff2 100644
--- a/litex/soc/cores/cpu/mor1kx/core.py
+++ b/litex/soc/cores/cpu/mor1kx/core.py
@@ -63,13 +63,13 @@ class MOR1KX(CPU):
 
     def __init__(self, platform, variant="standard"):
         assert variant in CPU_VARIANTS, "Unsupported variant %s" % variant
-        self.platform  = platform
-        self.variant   = variant
-        self.reset     = Signal()
-        self.ibus      = i = wishbone.Interface()
-        self.dbus      = d = wishbone.Interface()
-        self.buses     = [i, d]
-        self.interrupt = Signal(32)
+        self.platform     = platform
+        self.variant      = variant
+        self.reset        = Signal()
+        self.ibus         = i = wishbone.Interface()
+        self.dbus         = d = wishbone.Interface()
+        self.periph_buses = [i, d]
+        self.interrupt    = Signal(32)
 
         if variant == "linux":
             self.mem_map = self.mem_map_linux
diff --git a/litex/soc/cores/cpu/picorv32/core.py b/litex/soc/cores/cpu/picorv32/core.py
index 304f6c14d..03fc355d2 100644
--- a/litex/soc/cores/cpu/picorv32/core.py
+++ b/litex/soc/cores/cpu/picorv32/core.py
@@ -56,13 +56,13 @@ class PicoRV32(CPU):
 
     def __init__(self, platform, variant="standard"):
         assert variant in CPU_VARIANTS, "Unsupported variant %s" % variant
-        self.platform  = platform
-        self.variant   = variant
-        self.reset     = Signal()
-        self.idbus     = idbus = wishbone.Interface()
-        self.buses     = [idbus]
-        self.interrupt = Signal(32)
-        self.trap      = Signal()
+        self.platform     = platform
+        self.variant      = variant
+        self.reset        = Signal()
+        self.idbus        = idbus = wishbone.Interface()
+        self.periph_buses = [idbus]
+        self.interrupt    = Signal(32)
+        self.trap         = Signal()
 
         # # #
 
diff --git a/litex/soc/cores/cpu/rocket/core.py b/litex/soc/cores/cpu/rocket/core.py
index 14bab0f41..7d7afdf6c 100644
--- a/litex/soc/cores/cpu/rocket/core.py
+++ b/litex/soc/cores/cpu/rocket/core.py
@@ -106,7 +106,7 @@ class RocketRV64(CPU):
 
         self.mmio_wb   = mmio_wb = wishbone.Interface(data_width=mmio_dw, adr_width=32-log2_int(mmio_dw//8))
 
-        self.buses     = [mmio_wb]
+        self.periph_buses = [mmio_wb]
 
         # # #
 
diff --git a/litex/soc/cores/cpu/serv/core.py b/litex/soc/cores/cpu/serv/core.py
index 4fb2f0a49..00f313498 100644
--- a/litex/soc/cores/cpu/serv/core.py
+++ b/litex/soc/cores/cpu/serv/core.py
@@ -31,12 +31,12 @@ class SERV(CPU):
 
     def __init__(self, platform, variant="standard"):
         assert variant in CPU_VARIANTS, "Unsupported variant %s" % variant
-        self.platform  = platform
-        self.variant   = variant
-        self.reset     = Signal()
-        self.ibus      = ibus = wishbone.Interface()
-        self.dbus      = dbus = wishbone.Interface()
-        self.buses     = [ibus, dbus]
+        self.platform     = platform
+        self.variant      = variant
+        self.reset        = Signal()
+        self.ibus         = ibus = wishbone.Interface()
+        self.dbus         = dbus = wishbone.Interface()
+        self.periph_buses = [ibus, dbus]
 
         # # #
 
diff --git a/litex/soc/cores/cpu/vexriscv/core.py b/litex/soc/cores/cpu/vexriscv/core.py
index 4e0bbc0a0..bedd0de5a 100644
--- a/litex/soc/cores/cpu/vexriscv/core.py
+++ b/litex/soc/cores/cpu/vexriscv/core.py
@@ -105,7 +105,7 @@ class VexRiscv(CPU, AutoCSR):
         self.reset            = Signal()
         self.ibus             = ibus = wishbone.Interface()
         self.dbus             = dbus = wishbone.Interface()
-        self.buses            = [ibus, dbus]
+        self.periph_buses     = [ibus, dbus]
         self.interrupt        = Signal(32)
 
         self.cpu_params = dict(
diff --git a/litex/soc/integration/soc.py b/litex/soc/integration/soc.py
index dcea829aa..fbc86b6b4 100644
--- a/litex/soc/integration/soc.py
+++ b/litex/soc/integration/soc.py
@@ -781,7 +781,7 @@ class SoC(Module):
             if reset_address is None:
                 reset_address = self.mem_map["rom"]
             self.cpu.set_reset_address(reset_address)
-            for n, cpu_bus in enumerate(self.cpu.buses):
+            for n, cpu_bus in enumerate(self.cpu.periph_buses):
                 self.bus.add_master(name="cpu_bus{}".format(n), master=cpu_bus)
             self.csr.add("cpu", use_loc_if_exists=True)
             if hasattr(self.cpu, "interrupt"):

From 5ef869b9ebdcbfbe037e1fee6a06866a2837a168 Mon Sep 17 00:00:00 2001
From: Florent Kermarrec <florent@enjoy-digital.fr>
Date: Mon, 27 Apr 2020 23:51:17 +0200
Subject: [PATCH 37/95] soc/cpu: add memory_buses to cpus and use them in
 add_sdram.

This allows the CPU to have direct buses to the memory and replace the Rocket specific code.
---
 litex/soc/cores/cpu/__init__.py         |  2 +
 litex/soc/cores/cpu/blackparrot/core.py |  1 +
 litex/soc/cores/cpu/lm32/core.py        |  1 +
 litex/soc/cores/cpu/microwatt/core.py   |  1 +
 litex/soc/cores/cpu/minerva/core.py     |  3 +-
 litex/soc/cores/cpu/mor1kx/core.py      |  4 +-
 litex/soc/cores/cpu/picorv32/core.py    |  5 +-
 litex/soc/cores/cpu/rocket/core.py      |  1 +
 litex/soc/cores/cpu/serv/core.py        |  1 +
 litex/soc/cores/cpu/vexriscv/core.py    |  9 ++-
 litex/soc/integration/soc.py            | 96 +++++++++++++++----------
 11 files changed, 81 insertions(+), 43 deletions(-)

diff --git a/litex/soc/cores/cpu/__init__.py b/litex/soc/cores/cpu/__init__.py
index d0b11a50e..21f7ce5d5 100644
--- a/litex/soc/cores/cpu/__init__.py
+++ b/litex/soc/cores/cpu/__init__.py
@@ -26,6 +26,8 @@ class CPUNone(CPU):
     data_width           = 32
     reset_address        = 0x00000000
     io_regions           = {0x00000000: 0x100000000} # origin, length
+    periph_buses         = []
+    memory_buses         = []
 
 # CPUS ---------------------------------------------------------------------------------------------
 
diff --git a/litex/soc/cores/cpu/blackparrot/core.py b/litex/soc/cores/cpu/blackparrot/core.py
index fe220cf2e..6b186947c 100644
--- a/litex/soc/cores/cpu/blackparrot/core.py
+++ b/litex/soc/cores/cpu/blackparrot/core.py
@@ -79,6 +79,7 @@ class BlackParrotRV64(CPU):
         self.interrupt    = Signal(4)
         self.idbus        = idbus = wishbone.Interface(data_width=64, adr_width=37)
         self.periph_buses = [idbus]
+        self.memory_buses = []
 
         # # #
 
diff --git a/litex/soc/cores/cpu/lm32/core.py b/litex/soc/cores/cpu/lm32/core.py
index e1b6bce39..b05e1ede4 100644
--- a/litex/soc/cores/cpu/lm32/core.py
+++ b/litex/soc/cores/cpu/lm32/core.py
@@ -41,6 +41,7 @@ class LM32(CPU):
         self.dbus         = d = wishbone.Interface()
         self.interrupt    = Signal(32)
         self.periph_buses = [i, d]
+        self.memory_buses = []
 
         # # #
 
diff --git a/litex/soc/cores/cpu/microwatt/core.py b/litex/soc/cores/cpu/microwatt/core.py
index 17b6e3eaa..b951959b2 100644
--- a/litex/soc/cores/cpu/microwatt/core.py
+++ b/litex/soc/cores/cpu/microwatt/core.py
@@ -47,6 +47,7 @@ class Microwatt(CPU):
         self.wb_insn      = wb_insn = wishbone.Interface(data_width=64, adr_width=28)
         self.wb_data      = wb_data = wishbone.Interface(data_width=64, adr_width=28)
         self.periph_buses = [wb_insn, wb_data]
+        self.memory_buses = []
 
         # # #
 
diff --git a/litex/soc/cores/cpu/minerva/core.py b/litex/soc/cores/cpu/minerva/core.py
index 1603fea74..4ec118b0f 100644
--- a/litex/soc/cores/cpu/minerva/core.py
+++ b/litex/soc/cores/cpu/minerva/core.py
@@ -34,10 +34,11 @@ class Minerva(CPU):
         self.platform     = platform
         self.variant      = variant
         self.reset        = Signal()
+        self.interrupt    = Signal(32)
         self.ibus         = wishbone.Interface()
         self.dbus         = wishbone.Interface()
         self.periph_buses = [self.ibus, self.dbus]
-        self.interrupt    = Signal(32)
+        self.memory_buses = []
 
         # TODO: create variants
         self.with_icache = False
diff --git a/litex/soc/cores/cpu/mor1kx/core.py b/litex/soc/cores/cpu/mor1kx/core.py
index 59ece9ff2..d64dd1db0 100644
--- a/litex/soc/cores/cpu/mor1kx/core.py
+++ b/litex/soc/cores/cpu/mor1kx/core.py
@@ -66,10 +66,12 @@ class MOR1KX(CPU):
         self.platform     = platform
         self.variant      = variant
         self.reset        = Signal()
+        self.interrupt    = Signal(32)
         self.ibus         = i = wishbone.Interface()
         self.dbus         = d = wishbone.Interface()
         self.periph_buses = [i, d]
-        self.interrupt    = Signal(32)
+        self.memory_buses = []
+
 
         if variant == "linux":
             self.mem_map = self.mem_map_linux
diff --git a/litex/soc/cores/cpu/picorv32/core.py b/litex/soc/cores/cpu/picorv32/core.py
index 03fc355d2..459520bc0 100644
--- a/litex/soc/cores/cpu/picorv32/core.py
+++ b/litex/soc/cores/cpu/picorv32/core.py
@@ -58,11 +58,12 @@ class PicoRV32(CPU):
         assert variant in CPU_VARIANTS, "Unsupported variant %s" % variant
         self.platform     = platform
         self.variant      = variant
+        self.trap         = Signal()
         self.reset        = Signal()
+        self.interrupt    = Signal(32)
         self.idbus        = idbus = wishbone.Interface()
         self.periph_buses = [idbus]
-        self.interrupt    = Signal(32)
-        self.trap         = Signal()
+        self.memory_buses = []
 
         # # #
 
diff --git a/litex/soc/cores/cpu/rocket/core.py b/litex/soc/cores/cpu/rocket/core.py
index 7d7afdf6c..9af3bed15 100644
--- a/litex/soc/cores/cpu/rocket/core.py
+++ b/litex/soc/cores/cpu/rocket/core.py
@@ -107,6 +107,7 @@ class RocketRV64(CPU):
         self.mmio_wb   = mmio_wb = wishbone.Interface(data_width=mmio_dw, adr_width=32-log2_int(mmio_dw//8))
 
         self.periph_buses = [mmio_wb]
+        self.memory_buses = [mem_axi]
 
         # # #
 
diff --git a/litex/soc/cores/cpu/serv/core.py b/litex/soc/cores/cpu/serv/core.py
index 00f313498..92d49a6fc 100644
--- a/litex/soc/cores/cpu/serv/core.py
+++ b/litex/soc/cores/cpu/serv/core.py
@@ -37,6 +37,7 @@ class SERV(CPU):
         self.ibus         = ibus = wishbone.Interface()
         self.dbus         = dbus = wishbone.Interface()
         self.periph_buses = [ibus, dbus]
+        self.memory_buses = []
 
         # # #
 
diff --git a/litex/soc/cores/cpu/vexriscv/core.py b/litex/soc/cores/cpu/vexriscv/core.py
index bedd0de5a..869fe0763 100644
--- a/litex/soc/cores/cpu/vexriscv/core.py
+++ b/litex/soc/cores/cpu/vexriscv/core.py
@@ -103,14 +103,17 @@ class VexRiscv(CPU, AutoCSR):
         self.variant          = variant
         self.external_variant = None
         self.reset            = Signal()
+        self.interrupt        = Signal(32)
         self.ibus             = ibus = wishbone.Interface()
         self.dbus             = dbus = wishbone.Interface()
         self.periph_buses     = [ibus, dbus]
-        self.interrupt        = Signal(32)
+        self.memory_buses     = []
+
+        # # #
 
         self.cpu_params = dict(
-                i_clk=ClockSignal(),
-                i_reset=ResetSignal() | self.reset,
+                i_clk                    = ClockSignal(),
+                i_reset                  = ResetSignal() | self.reset,
 
                 i_externalInterruptArray = self.interrupt,
                 i_timerInterrupt         = 0,
diff --git a/litex/soc/integration/soc.py b/litex/soc/integration/soc.py
index fbc86b6b4..11e8dd2b2 100644
--- a/litex/soc/integration/soc.py
+++ b/litex/soc/integration/soc.py
@@ -991,6 +991,7 @@ class LiteXSoC(SoC):
         **kwargs):
 
         # Imports
+        from litedram.common import LiteDRAMNativePort
         from litedram.core import LiteDRAMCore
         from litedram.frontend.wishbone import LiteDRAMWishbone2Native
         from litedram.frontend.axi import LiteDRAMAXI2Native
@@ -1004,50 +1005,73 @@ class LiteXSoC(SoC):
             **kwargs)
         self.csr.add("sdram")
 
-        # LiteDRAM port
-        port = self.sdram.crossbar.get_port()
-        port.data_width = 2**int(log2(port.data_width)) # Round to nearest power of 2
-
-        # SDRAM size
+        # Compute/Check SDRAM size
         sdram_size = 2**(module.geom_settings.bankbits +
                          module.geom_settings.rowbits +
                          module.geom_settings.colbits)*phy.settings.databits//8
         if size is not None:
             sdram_size = min(sdram_size, size)
+
+        # Add SDRAM region
         self.bus.add_region("main_ram", SoCRegion(origin=origin, size=sdram_size))
 
         # SoC [<--> L2 Cache] <--> LiteDRAM --------------------------------------------------------
-        if self.cpu.name == "rocket":
-            # Rocket has its own I/D L1 cache: connect directly to LiteDRAM when possible.
-            if port.data_width == self.cpu.mem_axi.data_width:
-                self.logger.info("Matching AXI MEM data width ({})\n".format(port.data_width))
-                self.submodules += LiteDRAMAXI2Native(
-                    axi          = self.cpu.mem_axi,
-                    port         = port,
-                    base_address = self.bus.regions["main_ram"].origin)
-            else:
-                self.logger.info("Converting MEM data width: {} to {} via Wishbone".format(
-                    port.data_width,
-                    self.cpu.mem_axi.data_width))
-                # FIXME: replace WB data-width converter with native AXI converter!!!
-                mem_wb  = wishbone.Interface(
-                    data_width = self.cpu.mem_axi.data_width,
-                    adr_width  = 32-log2_int(self.cpu.mem_axi.data_width//8))
-                # NOTE: AXI2Wishbone FSMs must be reset with the CPU!
-                mem_a2w = ResetInserter()(axi.AXI2Wishbone(
-                    axi          = self.cpu.mem_axi,
-                    wishbone     = mem_wb,
-                    base_address = 0))
-                self.comb += mem_a2w.reset.eq(ResetSignal() | self.cpu.reset)
-                self.submodules += mem_a2w
-                litedram_wb = wishbone.Interface(port.data_width)
-                self.submodules += LiteDRAMWishbone2Native(
-                    wishbone     = litedram_wb,
-                    port         = port,
-                    base_address = origin)
-                self.submodules += wishbone.Converter(mem_wb, litedram_wb)
-        elif self.with_wishbone:
-            # Wishbone Slave SDRAM interface
+        if len(self.cpu.memory_buses):
+            # When CPU has at least a direct memory bus, connect them directly to LiteDRAM.
+            for mem_bus in self.cpu.memory_buses:
+                # Request a LiteDRAM native port.
+                port = self.sdram.crossbar.get_port()
+                port.data_width = 2**int(log2(port.data_width)) # Round to nearest power of 2.
+
+                # Check if bus is an AXI bus and connect it.
+                if isinstance(mem_bus, axi.AXIInterface):
+                    # If same data_width, connect it directly.
+                    if port.data_width == mem_bus.data_width:
+                        self.logger.info("Matching AXI MEM data width ({})\n".format(port.data_width))
+                        self.submodules += LiteDRAMAXI2Native(
+                            axi          = self.cpu.mem_axi,
+                            port         = port,
+                            base_address = self.bus.regions["main_ram"].origin)
+                    # If different data_width, do the adaptation and connect it via Wishbone.
+                    else:
+                        self.logger.info("Converting MEM data width: {} to {} via Wishbone".format(
+                            port.data_width,
+                            self.cpu.mem_axi.data_width))
+                        # FIXME: replace WB data-width converter with native AXI converter!!!
+                        mem_wb  = wishbone.Interface(
+                            data_width = self.cpu.mem_axi.data_width,
+                            adr_width  = 32-log2_int(self.cpu.mem_axi.data_width//8))
+                        # NOTE: AXI2Wishbone FSMs must be reset with the CPU!
+                        mem_a2w = ResetInserter()(axi.AXI2Wishbone(
+                            axi          = self.cpu.mem_axi,
+                            wishbone     = mem_wb,
+                            base_address = 0))
+                        self.comb += mem_a2w.reset.eq(ResetSignal() | self.cpu.reset)
+                        self.submodules += mem_a2w
+                        litedram_wb = wishbone.Interface(port.data_width)
+                        self.submodules += LiteDRAMWishbone2Native(
+                            wishbone     = litedram_wb,
+                            port         = port,
+                            base_address = origin)
+                        self.submodules += wishbone.Converter(mem_wb, litedram_wb)
+                # Check if bus is a Native bus and connect it.
+                if isinstance(mem_bus, LiteDRAMNativePort):
+                    # If same data_width, connect it directly.
+                    if port.data_width == mem_bus.data_width:
+                        self.comb += mem_bus.cmd.connect(port.cmd)
+                        self.comb += mem_bus.wdata.connect(port.wdata)
+                        self.comb += port.rdata.connect(mem_bus.rdata)
+                    # Else raise Error.
+                    else:
+                        raise NotImplementedError
+        else:
+            # When CPU has no direct memory interface, create a Wishbone Slave interface to LiteDRAM.
+
+            # Request a LiteDRAM native port.
+            port = self.sdram.crossbar.get_port()
+            port.data_width = 2**int(log2(port.data_width)) # Round to nearest power of 2.
+
+            # Create Wishbone Slave.
             wb_sdram = wishbone.Interface()
             self.bus.add_slave("main_ram", wb_sdram)
 

From ff61b1f6fab8d6ec588f42d502db254c57a0d866 Mon Sep 17 00:00:00 2001
From: Florent Kermarrec <florent@enjoy-digital.fr>
Date: Tue, 28 Apr 2020 08:58:26 +0200
Subject: [PATCH 38/95] litex_setup: disable automatic clone of
 BlackParrot/Microwatt CPUs, reorder LiteX data.

The support is not fully finished, so let the user install the pythondata for these CPUs manually with pip.
---
 litex_setup.py | 17 ++++++++---------
 1 file changed, 8 insertions(+), 9 deletions(-)

diff --git a/litex_setup.py b/litex_setup.py
index 9e5a085df..52c2635ed 100755
--- a/litex_setup.py
+++ b/litex_setup.py
@@ -19,8 +19,8 @@ repos = [
     ("migen",        ("https://github.com/m-labs/",        True,  True)),
 
     # LiteX SoC builder
-    ("pythondata-software-compiler_rt", ("https://github.com/litex-hub/", False, True)),
-    ("litex",        ("https://github.com/enjoy-digital/", False,  True)),
+    ("pythondata-software-compiler_rt", ("https://github.com/litex-hub/",     False, True)),
+    ("litex",                           ("https://github.com/enjoy-digital/", False, True)),
 
     # LiteX cores ecosystem
     ("liteeth",      ("https://github.com/enjoy-digital/", False, True)),
@@ -38,15 +38,14 @@ repos = [
     ("litex-boards", ("https://github.com/litex-hub/",     False, True)),
 
     # Optional LiteX data
-    ("pythondata-cpu-blackparrot", ("https://github.com/litex-hub/", False, True)),
-    ("pythondata-cpu-mor1kx",      ("https://github.com/litex-hub/", False, True)),
-    ("pythondata-cpu-lm32",        ("https://github.com/litex-hub/", False, True)),
-    ("pythondata-cpu-microwatt",   ("https://github.com/litex-hub/", False, True)),
-    ("pythondata-cpu-picorv32",    ("https://github.com/litex-hub/", False, True)),
-    ("pythondata-cpu-rocket",      ("https://github.com/litex-hub/", False, True)),
-    ("pythondata-cpu-vexriscv",    ("https://github.com/litex-hub/", False, True)),
     ("pythondata-misc-tapcfg",     ("https://github.com/litex-hub/", False, True)),
+    ("pythondata-cpu-lm32",        ("https://github.com/litex-hub/", False, True)),
+    ("pythondata-cpu-mor1kx",      ("https://github.com/litex-hub/", False, True)),
+    ("pythondata-cpu-picorv32",    ("https://github.com/litex-hub/", False, True)),
+    ("pythondata-cpu-vexriscv",    ("https://github.com/litex-hub/", False, True)),
+    ("pythondata-cpu-rocket",      ("https://github.com/litex-hub/", False, True)),
 ]
+
 repos = OrderedDict(repos)
 
 # RISC-V toolchain download ------------------------------------------------------------------------

From 1b069268822d2041f0051a0f3a2cb26e952c5271 Mon Sep 17 00:00:00 2001
From: Florent Kermarrec <florent@enjoy-digital.fr>
Date: Tue, 28 Apr 2020 09:02:59 +0200
Subject: [PATCH 39/95] README: update Python minimal version to 3.6.

---
 README.md | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/README.md b/README.md
index 0d28a9408..b6651b8c8 100644
--- a/README.md
+++ b/README.md
@@ -95,7 +95,7 @@ Provides definitions/modules to build cores (bus, bank, flow), cores and tools t
 Provides platforms and targets for the supported boards. All Migen's platforms can also be used in LiteX. The boards present in the LiteX repository are the official ones that are used for development/CI. More boards are available at: https://github.com/litex-hub/litex-boards
 
 # Quick start guide
-1. Install Python 3.5+ and FPGA vendor's development tools and/or [Verilator](http://www.veripool.org/).
+1. Install Python 3.6+ and FPGA vendor's development tools and/or [Verilator](http://www.veripool.org/).
 2. Install Migen/LiteX and the LiteX's cores:
 
 ```sh

From 6d0896de1d2cbbb925f3cddfa7baa721d635cb17 Mon Sep 17 00:00:00 2001
From: Florent Kermarrec <florent@enjoy-digital.fr>
Date: Tue, 28 Apr 2020 10:32:13 +0200
Subject: [PATCH 40/95] cpu/serv: switch to pythondata package instead of local
 git clone.

---
 litex/soc/cores/cpu/serv/core.py | 9 ++++-----
 litex_setup.py                   | 1 +
 2 files changed, 5 insertions(+), 5 deletions(-)

diff --git a/litex/soc/cores/cpu/serv/core.py b/litex/soc/cores/cpu/serv/core.py
index 92d49a6fc..d99661d66 100644
--- a/litex/soc/cores/cpu/serv/core.py
+++ b/litex/soc/cores/cpu/serv/core.py
@@ -6,6 +6,7 @@ import os
 
 from migen import *
 
+from litex import get_data_mod
 from litex.soc.interconnect import wishbone
 from litex.soc.cores.cpu import CPU
 
@@ -80,11 +81,9 @@ class SERV(CPU):
 
     @staticmethod
     def add_sources(platform):
-        # FIXME: add SERV as submodule
-        os.system("git clone https://github.com/olofk/serv")
-        vdir = os.path.join("serv", "rtl")
-        platform.add_source_dir(vdir)
-        platform.add_verilog_include_path(vdir)
+        vdir = get_data_mod("cpu", "serv").data_location
+        platform.add_source_dir(os.path.join(vdir, "rtl"))
+        platform.add_verilog_include_path(os.path.join(vdir, "rtl"))
 
     def do_finalize(self):
         assert hasattr(self, "reset_address")
diff --git a/litex_setup.py b/litex_setup.py
index 52c2635ed..f2502abc0 100755
--- a/litex_setup.py
+++ b/litex_setup.py
@@ -42,6 +42,7 @@ repos = [
     ("pythondata-cpu-lm32",        ("https://github.com/litex-hub/", False, True)),
     ("pythondata-cpu-mor1kx",      ("https://github.com/litex-hub/", False, True)),
     ("pythondata-cpu-picorv32",    ("https://github.com/litex-hub/", False, True)),
+    ("pythondata-cpu-serv",        ("https://github.com/litex-hub/", False, True)),
     ("pythondata-cpu-vexriscv",    ("https://github.com/litex-hub/", False, True)),
     ("pythondata-cpu-rocket",      ("https://github.com/litex-hub/", False, True)),
 ]

From 56aa7897df99d7ad68ea537ab096c3abdc683666 Mon Sep 17 00:00:00 2001
From: Florent Kermarrec <florent@enjoy-digital.fr>
Date: Tue, 28 Apr 2020 11:36:44 +0200
Subject: [PATCH 41/95] create first release, add CHANGES and note about Python
 modules in README.

---
 CHANGES   | 32 ++++++++++++++++++++++++++++++++
 README.md |  5 ++++-
 2 files changed, 36 insertions(+), 1 deletion(-)
 create mode 100644 CHANGES

diff --git a/CHANGES b/CHANGES
new file mode 100644
index 000000000..221c91be1
--- /dev/null
+++ b/CHANGES
@@ -0,0 +1,32 @@
+[> 2020.04, released April 28th, 2020
+-------------------------------------
+
+	[> Description
+	--------------
+	First release of LiteX and the ecosystem of cores!
+
+	LiteX is a Migen/MiSoC based Core/SoC builder that provides the infrastructure to easily create
+	Cores/SoCs (with or without CPU).
+
+	The common components of a SoC are provided directly:
+	- Buses and Streams (Wishbone, AXI, Avalon-ST)
+	- Interconnect
+	- Common cores (RAM, ROM, Timer, UART, etc...)
+	- CPU wrappers/integration
+	- etc...
+	And SoC creation capabilities can be greatly extended with the ecosystem of LiteX cores (DRAM,
+	PCIe, Ethernet, SATA, etc...) that can be integrated/simulated/build easily with LiteX.
+
+	It also provides build backends for open-source and vendors toolchains.
+
+	[> Issues resolved
+	------------------
+	- NA
+
+	[> Added Features
+	------------------
+	- NA
+
+	[> API changes/Deprecation
+	--------------------------
+	- https://github.com/enjoy-digital/litex/pull/399: Converting LiteX to use Python modules.
diff --git a/README.md b/README.md
index b6651b8c8..7ebdc2f24 100644
--- a/README.md
+++ b/README.md
@@ -5,10 +5,13 @@
 ```
 [![](https://travis-ci.com/enjoy-digital/litex.svg?branch=master)](https://travis-ci.com/enjoy-digital/litex)
 ![License](https://img.shields.io/badge/License-BSD%202--Clause-orange.svg)
+
+> **Note:** In release 2020.04, LiteX switched to Python modules instead of Git submodules. Existing users will have to reinstall LiteX following the [installation guide](https://github.com/enjoy-digital/litex/wiki/Installation#litex-installation-guide).
+
 # Welcome to LiteX!
 
 LiteX is a Migen/MiSoC based Core/SoC builder that provides the infrastructure to easily create Cores/SoCs (with or without CPU).
-The common components of a SoC are provided directly: Buses and Streams (Wishbone, AXI, Avalon-ST), Interconnect, Common cores (RAM, ROM, Timer, UART, etc...), CPU wrappers/integration, etc... and SoC creation capabilities can be greatly extended with the ecosystem of LiteX cores (DRAM, PCIe, Ethernet, SATA, etc...) than can be integrated/simulated/build easily with LiteX. It also provides build backends for open-source and vendors toolchains.
+The common components of a SoC are provided directly: Buses and Streams (Wishbone, AXI, Avalon-ST), Interconnect, Common cores (RAM, ROM, Timer, UART, etc...), CPU wrappers/integration, etc... and SoC creation capabilities can be greatly extended with the ecosystem of LiteX cores (DRAM, PCIe, Ethernet, SATA, etc...) that can be integrated/simulated/build easily with LiteX. It also provides build backends for open-source and vendors toolchains.
 
 Think of Migen as a toolbox to create FPGA designs in Python and LiteX as a
 SoC builder to create/develop/debug FPGA SoCs in Python.

From 17b766546b784c023ce9e1e79cfc2af3a379ff34 Mon Sep 17 00:00:00 2001
From: bunnie <bunnie@kosagi.com>
Date: Wed, 29 Apr 2020 00:34:19 +0800
Subject: [PATCH 42/95] propose patch to not break litex for python 3.5

---
 litex/build/lattice/programmer.py | 8 ++++----
 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/litex/build/lattice/programmer.py b/litex/build/lattice/programmer.py
index addc51dcf..c97bb07b0 100644
--- a/litex/build/lattice/programmer.py
+++ b/litex/build/lattice/programmer.py
@@ -32,7 +32,7 @@ class OpenOCDJTAGProgrammer(GenericProgrammer):
     def load_bitstream(self, bitstream_file):
         svf_file = bitstream_file.replace(".bit", ".svf")
 
-        subprocess.call(["openocd", "-f", self.openocd_config , "-c", f"transport select jtag; init; svf \"{svf_file}\"; exit"])
+        subprocess.call(["openocd", "-f", self.openocd_config , "-c", "transport select jtag; init; svf \"{}\"; exit".format(svf_file)])
 
     def flash(self, address, data, erase=False, verify=True):
         if self.flash_proxy_basename is None:
@@ -50,11 +50,11 @@ class OpenOCDJTAGProgrammer(GenericProgrammer):
             "target create ecp5.spi0.proxy testee -chain-position ecp5.tap",
             "flash bank spi0 jtagspi 0 0 0 0 ecp5.spi0.proxy 0x32",
             "init",
-            f"svf \"{flash_proxy}\"" if flash_proxy is not None else "",
+            "svf \"{}\"" if flash_proxy is not None else "".format(flash_proxy),
             "reset halt",
             "flash probe spi0",
-            f"flash write_image {erase} \"{data}\" 0x{address:x}",
-            f"flash verify_bank spi0 \"{data}\" 0x{address:x}" if verify else "",
+            "flash write_image {0} \"{1}\" 0x{2:x}".format(erase, data, address),
+            "flash verify_bank spi0 \"{0}\" 0x{1:x}" if verify else "".format(data, address),
             "exit"
         ])
         subprocess.call(["openocd", "-f", self.openocd_config, "-c", script])

From a11f1c39b7eafca10d8cb934f8caa01fd11aa067 Mon Sep 17 00:00:00 2001
From: Ilya Epifanov <elijah.epifanov@gmail.com>
Date: Tue, 28 Apr 2020 22:04:44 +0200
Subject: [PATCH 43/95] Removed erase flag and made progress output less noisy

---
 litex/build/lattice/programmer.py | 13 ++++---------
 1 file changed, 4 insertions(+), 9 deletions(-)

diff --git a/litex/build/lattice/programmer.py b/litex/build/lattice/programmer.py
index c97bb07b0..0095c147f 100644
--- a/litex/build/lattice/programmer.py
+++ b/litex/build/lattice/programmer.py
@@ -32,28 +32,23 @@ class OpenOCDJTAGProgrammer(GenericProgrammer):
     def load_bitstream(self, bitstream_file):
         svf_file = bitstream_file.replace(".bit", ".svf")
 
-        subprocess.call(["openocd", "-f", self.openocd_config , "-c", "transport select jtag; init; svf \"{}\"; exit".format(svf_file)])
+        subprocess.call(["openocd", "-f", self.openocd_config , "-c", "transport select jtag; init; svf quiet progress \"{}\"; exit".format(svf_file)])
 
-    def flash(self, address, data, erase=False, verify=True):
+    def flash(self, address, data, verify=True):
         if self.flash_proxy_basename is None:
             flash_proxy = None
         else:
             flash_proxy = self.find_flash_proxy()
 
-        if erase:
-            erase = "erase"
-        else:
-            erase = ""
-
         script = "; ".join([
             "transport select jtag",
             "target create ecp5.spi0.proxy testee -chain-position ecp5.tap",
             "flash bank spi0 jtagspi 0 0 0 0 ecp5.spi0.proxy 0x32",
             "init",
-            "svf \"{}\"" if flash_proxy is not None else "".format(flash_proxy),
+            "svf quiet progress \"{}\"".format(flash_proxy) if flash_proxy is not None else "",
             "reset halt",
             "flash probe spi0",
-            "flash write_image {0} \"{1}\" 0x{2:x}".format(erase, data, address),
+            "flash write_image erase \"{0}\" 0x{1:x}".format(data, address),
             "flash verify_bank spi0 \"{0}\" 0x{1:x}" if verify else "".format(data, address),
             "exit"
         ])

From 9941e4c16b58589c114b637b6c1ef87fe4ecd527 Mon Sep 17 00:00:00 2001
From: Florent Kermarrec <florent@enjoy-digital.fr>
Date: Wed, 29 Apr 2020 08:00:55 +0200
Subject: [PATCH 44/95] travis: add back test on python3.5 (python3.6 is
 recommended but we can try to keep 3.5 compatibility until we have good
 reason to no longer support it).

---
 .travis.yml | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/.travis.yml b/.travis.yml
index 8f491ae73..f461f48c9 100644
--- a/.travis.yml
+++ b/.travis.yml
@@ -1,5 +1,9 @@
 jobs:
   include:
+    - os: linux
+      dist: xenial
+      language: python
+      python: "3.5"
     - os: linux
       dist: xenial
       language: python

From 3531a6417312a9b716901ed540b9a66d69855a0b Mon Sep 17 00:00:00 2001
From: Florent Kermarrec <florent@enjoy-digital.fr>
Date: Wed, 29 Apr 2020 20:11:47 +0200
Subject: [PATCH 45/95] soc: allow passing custom CPU class to SoC.

Useful to experiment with custom CPU wrappers and a first step to make CPUs plugable.
---
 litex/soc/integration/soc.py      | 5 +++--
 litex/soc/integration/soc_core.py | 3 +++
 2 files changed, 6 insertions(+), 2 deletions(-)

diff --git a/litex/soc/integration/soc.py b/litex/soc/integration/soc.py
index 11e8dd2b2..d22989a20 100644
--- a/litex/soc/integration/soc.py
+++ b/litex/soc/integration/soc.py
@@ -762,7 +762,7 @@ class SoC(Module):
         self.add_config("CSR_DATA_WIDTH", self.csr.data_width)
         self.add_config("CSR_ALIGNMENT",  self.csr.alignment)
 
-    def add_cpu(self, name="vexriscv", variant="standard", reset_address=None):
+    def add_cpu(self, name="vexriscv", variant="standard", cls=None, reset_address=None):
         if name not in cpu.CPUS.keys():
             self.logger.error("{} CPU {}, supporteds: {}".format(
                 colorer(name),
@@ -770,7 +770,8 @@ class SoC(Module):
                 colorer(", ".join(cpu.CPUS.keys()))))
             raise
         # Add CPU
-        self.submodules.cpu = cpu.CPUS[name](self.platform, variant)
+        cpu_cls = cls if cls is not None else cpu.CPUS[name]
+        self.submodules.cpu = cpu_cls(self.platform, variant)
         # Update SoC with CPU constraints
         for n, (origin, size) in enumerate(self.cpu.io_regions.items()):
             self.bus.add_region("io{}".format(n), SoCIORegion(origin=origin, size=size, cached=False))
diff --git a/litex/soc/integration/soc_core.py b/litex/soc/integration/soc_core.py
index 3eb0016c7..f61555a31 100644
--- a/litex/soc/integration/soc_core.py
+++ b/litex/soc/integration/soc_core.py
@@ -65,6 +65,7 @@ class SoCCore(LiteXSoC):
         cpu_type                 = "vexriscv",
         cpu_reset_address        = None,
         cpu_variant              = None,
+        cpu_cls                  = None,
         # ROM parameters
         integrated_rom_size      = 0,
         integrated_rom_init      = [],
@@ -131,6 +132,7 @@ class SoCCore(LiteXSoC):
 
         self.cpu_type                   = cpu_type
         self.cpu_variant                = cpu_variant
+        self.cpu_cls                    = cpu_cls
 
         self.integrated_rom_size        = integrated_rom_size
         self.integrated_rom_initialized = integrated_rom_init != []
@@ -154,6 +156,7 @@ class SoCCore(LiteXSoC):
         self.add_cpu(
             name          = str(cpu_type),
             variant       = "standard" if cpu_variant is None else cpu_variant,
+            cls           = cpu_cls,
             reset_address = None if integrated_rom_size else cpu_reset_address)
 
         # Add User's interrupts

From 0a1afbf66f69779a618f72393457f275d59e0c4c Mon Sep 17 00:00:00 2001
From: Florent Kermarrec <florent@enjoy-digital.fr>
Date: Thu, 30 Apr 2020 21:31:58 +0200
Subject: [PATCH 46/95] litex/__init__.py: remove retro-compat > 6 months old.

---
 litex/__init__.py                 | 8 --------
 litex/soc/integration/soc_zynq.py | 2 +-
 2 files changed, 1 insertion(+), 9 deletions(-)

diff --git a/litex/__init__.py b/litex/__init__.py
index 0499e31a8..5f37b49da 100644
--- a/litex/__init__.py
+++ b/litex/__init__.py
@@ -1,13 +1,5 @@
 import sys
 
-# retro-compat 2019-09-30
-from litex.soc.interconnect import packet
-sys.modules["litex.soc.interconnect.stream_packet"] = packet
-
-# retro-compat 2019-09-29
-from litex.soc.integration import export
-sys.modules["litex.soc.integration.cpu_interface"] = export
-
 from litex.tools.litex_client import RemoteClient
 
 def get_data_mod(data_type, data_name):
diff --git a/litex/soc/integration/soc_zynq.py b/litex/soc/integration/soc_zynq.py
index 3bcc86b90..b65c2f770 100644
--- a/litex/soc/integration/soc_zynq.py
+++ b/litex/soc/integration/soc_zynq.py
@@ -7,7 +7,7 @@ from migen import *
 
 from litex.build.generic_platform import tools
 from litex.soc.integration.soc_core import *
-from litex.soc.integration.cpu_interface import get_csr_header
+from litex.soc.integration.export import get_csr_header
 from litex.soc.interconnect import wishbone
 from litex.soc.interconnect import axi
 

From b82b3b7ecffee3740641b547a238c918db0892c2 Mon Sep 17 00:00:00 2001
From: Florent Kermarrec <florent@enjoy-digital.fr>
Date: Thu, 30 Apr 2020 21:45:53 +0200
Subject: [PATCH 47/95] integration/soc: rename usb_cdc to usb_acm.

As discussed on Discord recently.
---
 litex/soc/integration/soc.py | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/litex/soc/integration/soc.py b/litex/soc/integration/soc.py
index d22989a20..55557ecf1 100644
--- a/litex/soc/integration/soc.py
+++ b/litex/soc/integration/soc.py
@@ -958,8 +958,8 @@ class LiteXSoC(SoC):
                 tx_fifo_depth = fifo_depth,
                 rx_fifo_depth = fifo_depth))
 
-        # USB CDC (with ValentyUSB core)
-        elif name in ["usb_cdc"]:
+        # USB ACM (with ValentyUSB core)
+        elif name in ["usb_acm"]:
             import valentyusb.usbcore.io as usbio
             import valentyusb.usbcore.cpu.cdc_eptri as cdc_eptri
             usb_pads = self.platform.request("usb")

From 0abc7d4f0bb635775698f7e18072bc69b72a7db5 Mon Sep 17 00:00:00 2001
From: Florent Kermarrec <florent@enjoy-digital.fr>
Date: Fri, 1 May 2020 11:01:50 +0200
Subject: [PATCH 48/95] cpu/Minerva: Clone the repository locally for now, we
 need to create a pythondata repository.

---
 litex/soc/cores/cpu/minerva/core.py | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/litex/soc/cores/cpu/minerva/core.py b/litex/soc/cores/cpu/minerva/core.py
index 4ec118b0f..a4b63e629 100644
--- a/litex/soc/cores/cpu/minerva/core.py
+++ b/litex/soc/cores/cpu/minerva/core.py
@@ -98,8 +98,8 @@ class Minerva(CPU):
             cli_params.append("--with-dcache")
         if with_muldiv:
             cli_params.append("--with-muldiv")
-        _dir = os.path.abspath(os.path.dirname(__file__))
-        if subprocess.call(["python3", os.path.join(_dir, "verilog", "cli.py"), *cli_params, "generate"],
+        os.system("git clone http://github.com/lambdaconcept/minerva") # FIXME: create pythondata.
+        if subprocess.call(["python3", os.path.join("minerva", "cli.py"), *cli_params, "generate"],
             stdout=open(verilog_filename, "w")):
             raise OSError("Unable to elaborate Minerva CPU, please check your nMigen/Yosys install")
 

From bb70a2325a778220f110d4287d4f96b11c7d0acb Mon Sep 17 00:00:00 2001
From: Florent Kermarrec <florent@enjoy-digital.fr>
Date: Fri, 1 May 2020 08:15:17 +0200
Subject: [PATCH 49/95] cpu/software: move CPU specific software from the BIOS
 to the CPU directories.

This simplifies the integration of the CPUs' software, avoid complex switches in the code,
and is a first step to make CPUs fully pluggable.

The CPU name is no longer present in the crt0 files (for example crt0-vexriscv-ctr.o
becomes crt0-ctr.o) so users building firmwares externally will have to update their
Makefiles to remove the $(CPU) from crt0-$(CPU)-ctr.o.
---
 .../cpu/blackparrot/boot-helper.S}            |   0
 .../cpu/blackparrot/crt0.S}                   |   0
 litex/soc/cores/cpu/blackparrot/csr-defs.h    |   8 +
 litex/soc/cores/cpu/blackparrot/irq.h         |  51 +++++
 .../base => cores/cpu/blackparrot}/system.h   |  20 +-
 .../cpu/lm32/boot-helper.S}                   |   0
 .../crt0-lm32.S => cores/cpu/lm32/crt0.S}     |   0
 litex/soc/cores/cpu/lm32/irq.h                |  47 +++++
 litex/soc/cores/cpu/lm32/system.h             |  18 ++
 .../cpu/microwatt/boot-helper.S}              |   0
 .../cpu/microwatt/crt0.S}                     |   0
 litex/soc/cores/cpu/microwatt/irq.h           |   4 +
 litex/soc/cores/cpu/microwatt/system.h        |  18 ++
 .../cpu/minerva/boot-helper.S}                |   0
 .../cpu/minerva/crt0.S}                       |   0
 .../base => cores/cpu/minerva}/csr-defs.h     |   7 -
 litex/soc/cores/cpu/minerva/irq.h             |  45 ++++
 litex/soc/cores/cpu/minerva/system.h          |  42 ++++
 .../cpu/mor1kx/boot-helper.S}                 |   0
 .../crt0-mor1kx.S => cores/cpu/mor1kx/crt0.S} |   0
 litex/soc/cores/cpu/mor1kx/irq.h              |  44 ++++
 litex/soc/cores/cpu/mor1kx/system.h           |  33 +++
 .../cpu/picorv32/boot-helper.S}               |   0
 .../cpu/picorv32/crt0.S}                      |   2 +-
 .../cpu/picorv32/extraops.S}                  |   0
 litex/soc/cores/cpu/picorv32/irq.h            |  67 ++++++
 litex/soc/cores/cpu/picorv32/system.h         |  18 ++
 .../cpu/rocket/boot-helper.S}                 |   0
 .../crt0-rocket.S => cores/cpu/rocket/crt0.S} |   0
 litex/soc/cores/cpu/rocket/csr-defs.h         |   8 +
 litex/soc/cores/cpu/rocket/irq.h              |  50 +++++
 litex/soc/cores/cpu/rocket/system.h           |  42 ++++
 .../cpu/serv/boot-helper.S}                   |   0
 .../crt0-serv.S => cores/cpu/serv/crt0.S}     |   0
 litex/soc/cores/cpu/serv/irq.h                |   4 +
 litex/soc/cores/cpu/serv/system.h             |  18 ++
 .../cpu/vexriscv/boot-helper.S}               |   0
 .../cpu/vexriscv/crt0.S}                      |   0
 litex/soc/cores/cpu/vexriscv/csr-defs.h       |  11 +
 litex/soc/cores/cpu/vexriscv/irq.h            |  45 ++++
 litex/soc/cores/cpu/vexriscv/system.h         |  42 ++++
 litex/soc/integration/export.py               |   4 +-
 litex/soc/software/bios/Makefile              |  14 +-
 litex/soc/software/bios/sdram.c               |   1 +
 litex/soc/software/common.mak                 |   2 +-
 litex/soc/software/include/base/irq.h         | 196 ------------------
 litex/soc/software/libbase/Makefile           |   8 +-
 47 files changed, 636 insertions(+), 233 deletions(-)
 rename litex/soc/{software/bios/boot-helper-blackparrot.S => cores/cpu/blackparrot/boot-helper.S} (100%)
 rename litex/soc/{software/libbase/crt0-blackparrot.S => cores/cpu/blackparrot/crt0.S} (100%)
 create mode 100644 litex/soc/cores/cpu/blackparrot/csr-defs.h
 create mode 100644 litex/soc/cores/cpu/blackparrot/irq.h
 rename litex/soc/{software/include/base => cores/cpu/blackparrot}/system.h (69%)
 rename litex/soc/{software/bios/boot-helper-lm32.S => cores/cpu/lm32/boot-helper.S} (100%)
 rename litex/soc/{software/libbase/crt0-lm32.S => cores/cpu/lm32/crt0.S} (100%)
 mode change 100755 => 100644
 create mode 100644 litex/soc/cores/cpu/lm32/irq.h
 create mode 100644 litex/soc/cores/cpu/lm32/system.h
 rename litex/soc/{software/bios/boot-helper-microwatt.S => cores/cpu/microwatt/boot-helper.S} (100%)
 rename litex/soc/{software/libbase/crt0-microwatt.S => cores/cpu/microwatt/crt0.S} (100%)
 create mode 100644 litex/soc/cores/cpu/microwatt/irq.h
 create mode 100644 litex/soc/cores/cpu/microwatt/system.h
 rename litex/soc/{software/bios/boot-helper-minerva.S => cores/cpu/minerva/boot-helper.S} (100%)
 rename litex/soc/{software/libbase/crt0-minerva.S => cores/cpu/minerva/crt0.S} (100%)
 rename litex/soc/{software/include/base => cores/cpu/minerva}/csr-defs.h (59%)
 create mode 100644 litex/soc/cores/cpu/minerva/irq.h
 create mode 100644 litex/soc/cores/cpu/minerva/system.h
 rename litex/soc/{software/bios/boot-helper-mor1kx.S => cores/cpu/mor1kx/boot-helper.S} (100%)
 rename litex/soc/{software/libbase/crt0-mor1kx.S => cores/cpu/mor1kx/crt0.S} (100%)
 create mode 100644 litex/soc/cores/cpu/mor1kx/irq.h
 create mode 100644 litex/soc/cores/cpu/mor1kx/system.h
 rename litex/soc/{software/bios/boot-helper-picorv32.S => cores/cpu/picorv32/boot-helper.S} (100%)
 rename litex/soc/{software/libbase/crt0-picorv32.S => cores/cpu/picorv32/crt0.S} (99%)
 rename litex/soc/{software/include/base/picorv32-extraops.S => cores/cpu/picorv32/extraops.S} (100%)
 create mode 100644 litex/soc/cores/cpu/picorv32/irq.h
 create mode 100644 litex/soc/cores/cpu/picorv32/system.h
 rename litex/soc/{software/bios/boot-helper-rocket.S => cores/cpu/rocket/boot-helper.S} (100%)
 rename litex/soc/{software/libbase/crt0-rocket.S => cores/cpu/rocket/crt0.S} (100%)
 create mode 100644 litex/soc/cores/cpu/rocket/csr-defs.h
 create mode 100644 litex/soc/cores/cpu/rocket/irq.h
 create mode 100644 litex/soc/cores/cpu/rocket/system.h
 rename litex/soc/{software/bios/boot-helper-serv.S => cores/cpu/serv/boot-helper.S} (100%)
 rename litex/soc/{software/libbase/crt0-serv.S => cores/cpu/serv/crt0.S} (100%)
 create mode 100644 litex/soc/cores/cpu/serv/irq.h
 create mode 100644 litex/soc/cores/cpu/serv/system.h
 rename litex/soc/{software/bios/boot-helper-vexriscv.S => cores/cpu/vexriscv/boot-helper.S} (100%)
 rename litex/soc/{software/libbase/crt0-vexriscv.S => cores/cpu/vexriscv/crt0.S} (100%)
 create mode 100644 litex/soc/cores/cpu/vexriscv/csr-defs.h
 create mode 100644 litex/soc/cores/cpu/vexriscv/irq.h
 create mode 100644 litex/soc/cores/cpu/vexriscv/system.h
 delete mode 100644 litex/soc/software/include/base/irq.h

diff --git a/litex/soc/software/bios/boot-helper-blackparrot.S b/litex/soc/cores/cpu/blackparrot/boot-helper.S
similarity index 100%
rename from litex/soc/software/bios/boot-helper-blackparrot.S
rename to litex/soc/cores/cpu/blackparrot/boot-helper.S
diff --git a/litex/soc/software/libbase/crt0-blackparrot.S b/litex/soc/cores/cpu/blackparrot/crt0.S
similarity index 100%
rename from litex/soc/software/libbase/crt0-blackparrot.S
rename to litex/soc/cores/cpu/blackparrot/crt0.S
diff --git a/litex/soc/cores/cpu/blackparrot/csr-defs.h b/litex/soc/cores/cpu/blackparrot/csr-defs.h
new file mode 100644
index 000000000..170bd4540
--- /dev/null
+++ b/litex/soc/cores/cpu/blackparrot/csr-defs.h
@@ -0,0 +1,8 @@
+#ifndef CSR_DEFS__H
+#define CSR_DEFS__H
+
+#define CSR_MSTATUS_MIE 0x8
+
+#define CSR_DCACHE_INFO 0xCC0
+
+#endif	/* CSR_DEFS__H */
diff --git a/litex/soc/cores/cpu/blackparrot/irq.h b/litex/soc/cores/cpu/blackparrot/irq.h
new file mode 100644
index 000000000..af5b7991c
--- /dev/null
+++ b/litex/soc/cores/cpu/blackparrot/irq.h
@@ -0,0 +1,51 @@
+#ifndef __IRQ_H
+#define __IRQ_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <system.h>
+#include <generated/csr.h>
+#include <generated/soc.h>
+
+// The RocketChip uses a Platform-Level Interrupt Controller (PLIC) which
+// is programmed and queried via a set of MMIO registers.
+// TODO: How about Blackparrot? Should be probably included in linux version
+
+#define PLIC_BASE    0x0c000000L // Base address and per-pin priority array
+#define PLIC_PENDING 0x0c001000L // Bit field matching currently pending pins
+#define PLIC_ENABLED 0x0c002000L // Bit field corresponding to the current mask
+#define PLIC_THRSHLD 0x0c200000L // Per-pin priority must be >= this to trigger
+#define PLIC_CLAIM   0x0c200004L // Claim & completion register address
+
+static inline unsigned int irq_getie(void)
+{
+	return (csrr(mstatus) & CSR_MSTATUS_MIE) != 0; /* FIXME */
+}
+
+static inline void irq_setie(unsigned int ie)
+{
+	if(ie) csrs(mstatus,CSR_MSTATUS_MIE); else csrc(mstatus,CSR_MSTATUS_MIE); /* FIXME */
+}
+
+static inline unsigned int irq_getmask(void)
+{
+	return 0; /* FIXME */
+}
+
+static inline void irq_setmask(unsigned int mask)
+{
+	/* FIXME */
+}
+
+static inline unsigned int irq_pending(void)
+{
+	return csr_readl(PLIC_PENDING) >> 1; /* FIXME */
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __IRQ_H */
diff --git a/litex/soc/software/include/base/system.h b/litex/soc/cores/cpu/blackparrot/system.h
similarity index 69%
rename from litex/soc/software/include/base/system.h
rename to litex/soc/cores/cpu/blackparrot/system.h
index ef3bf45b0..cccdb54d2 100644
--- a/litex/soc/software/include/base/system.h
+++ b/litex/soc/cores/cpu/blackparrot/system.h
@@ -11,25 +11,8 @@ void flush_l2_cache(void);
 
 void busy_wait(unsigned int ms);
 
-#ifdef __or1k__
-#include <spr-defs.h>
-static inline unsigned long mfspr(unsigned long add)
-{
-	unsigned long ret;
-
-	__asm__ __volatile__ ("l.mfspr %0,%1,0" : "=r" (ret) : "r" (add));
-
-	return ret;
-}
-
-static inline void mtspr(unsigned long add, unsigned long val)
-{
-	__asm__ __volatile__ ("l.mtspr %0,%1,0" : : "r" (add), "r" (val));
-}
-#endif
-
-#if defined(__vexriscv__) || defined(__minerva__) || defined(__rocket__) || defined(__blackparrot__)
 #include <csr-defs.h>
+
 #define csrr(reg) ({ unsigned long __tmp; \
   asm volatile ("csrr %0, " #reg : "=r"(__tmp)); \
   __tmp; })
@@ -51,7 +34,6 @@ static inline void mtspr(unsigned long add, unsigned long val)
 	asm volatile ("csrrc x0, " #reg ", %0" :: "i"(bit)); \
   else \
 	asm volatile ("csrrc x0, " #reg ", %0" :: "r"(bit)); })
-#endif
 
 #ifdef __cplusplus
 }
diff --git a/litex/soc/software/bios/boot-helper-lm32.S b/litex/soc/cores/cpu/lm32/boot-helper.S
similarity index 100%
rename from litex/soc/software/bios/boot-helper-lm32.S
rename to litex/soc/cores/cpu/lm32/boot-helper.S
diff --git a/litex/soc/software/libbase/crt0-lm32.S b/litex/soc/cores/cpu/lm32/crt0.S
old mode 100755
new mode 100644
similarity index 100%
rename from litex/soc/software/libbase/crt0-lm32.S
rename to litex/soc/cores/cpu/lm32/crt0.S
diff --git a/litex/soc/cores/cpu/lm32/irq.h b/litex/soc/cores/cpu/lm32/irq.h
new file mode 100644
index 000000000..dd9477fa4
--- /dev/null
+++ b/litex/soc/cores/cpu/lm32/irq.h
@@ -0,0 +1,47 @@
+#ifndef __IRQ_H
+#define __IRQ_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <system.h>
+#include <generated/csr.h>
+#include <generated/soc.h>
+
+static inline unsigned int irq_getie(void)
+{
+	unsigned int ie;
+	__asm__ __volatile__("rcsr %0, IE" : "=r" (ie));
+	return ie;
+}
+
+static inline void irq_setie(unsigned int ie)
+{
+	__asm__ __volatile__("wcsr IE, %0" : : "r" (ie));
+}
+
+static inline unsigned int irq_getmask(void)
+{
+	unsigned int mask;
+	__asm__ __volatile__("rcsr %0, IM" : "=r" (mask));
+	return mask;
+}
+
+static inline void irq_setmask(unsigned int mask)
+{
+	__asm__ __volatile__("wcsr IM, %0" : : "r" (mask));
+}
+
+static inline unsigned int irq_pending(void)
+{
+	unsigned int pending;
+	__asm__ __volatile__("rcsr %0, IP" : "=r" (pending));
+	return pending;
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __IRQ_H */
diff --git a/litex/soc/cores/cpu/lm32/system.h b/litex/soc/cores/cpu/lm32/system.h
new file mode 100644
index 000000000..989c9c621
--- /dev/null
+++ b/litex/soc/cores/cpu/lm32/system.h
@@ -0,0 +1,18 @@
+#ifndef __SYSTEM_H
+#define __SYSTEM_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+void flush_cpu_icache(void);
+void flush_cpu_dcache(void);
+void flush_l2_cache(void);
+
+void busy_wait(unsigned int ms);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __SYSTEM_H */
diff --git a/litex/soc/software/bios/boot-helper-microwatt.S b/litex/soc/cores/cpu/microwatt/boot-helper.S
similarity index 100%
rename from litex/soc/software/bios/boot-helper-microwatt.S
rename to litex/soc/cores/cpu/microwatt/boot-helper.S
diff --git a/litex/soc/software/libbase/crt0-microwatt.S b/litex/soc/cores/cpu/microwatt/crt0.S
similarity index 100%
rename from litex/soc/software/libbase/crt0-microwatt.S
rename to litex/soc/cores/cpu/microwatt/crt0.S
diff --git a/litex/soc/cores/cpu/microwatt/irq.h b/litex/soc/cores/cpu/microwatt/irq.h
new file mode 100644
index 000000000..7374cf506
--- /dev/null
+++ b/litex/soc/cores/cpu/microwatt/irq.h
@@ -0,0 +1,4 @@
+#ifndef __IRQ_H
+#define __IRQ_H
+
+#endif /* __IRQ_H */
diff --git a/litex/soc/cores/cpu/microwatt/system.h b/litex/soc/cores/cpu/microwatt/system.h
new file mode 100644
index 000000000..989c9c621
--- /dev/null
+++ b/litex/soc/cores/cpu/microwatt/system.h
@@ -0,0 +1,18 @@
+#ifndef __SYSTEM_H
+#define __SYSTEM_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+void flush_cpu_icache(void);
+void flush_cpu_dcache(void);
+void flush_l2_cache(void);
+
+void busy_wait(unsigned int ms);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __SYSTEM_H */
diff --git a/litex/soc/software/bios/boot-helper-minerva.S b/litex/soc/cores/cpu/minerva/boot-helper.S
similarity index 100%
rename from litex/soc/software/bios/boot-helper-minerva.S
rename to litex/soc/cores/cpu/minerva/boot-helper.S
diff --git a/litex/soc/software/libbase/crt0-minerva.S b/litex/soc/cores/cpu/minerva/crt0.S
similarity index 100%
rename from litex/soc/software/libbase/crt0-minerva.S
rename to litex/soc/cores/cpu/minerva/crt0.S
diff --git a/litex/soc/software/include/base/csr-defs.h b/litex/soc/cores/cpu/minerva/csr-defs.h
similarity index 59%
rename from litex/soc/software/include/base/csr-defs.h
rename to litex/soc/cores/cpu/minerva/csr-defs.h
index 75c8e043d..5f5ea8476 100644
--- a/litex/soc/software/include/base/csr-defs.h
+++ b/litex/soc/cores/cpu/minerva/csr-defs.h
@@ -3,15 +3,8 @@
 
 #define CSR_MSTATUS_MIE 0x8
 
-#if defined (__vexriscv__)
-#define CSR_IRQ_MASK 0xBC0
-#define CSR_IRQ_PENDING 0xFC0
-#endif
-
-#if defined (__minerva__)
 #define CSR_IRQ_MASK 0x330
 #define CSR_IRQ_PENDING 0x360
-#endif
 
 #define CSR_DCACHE_INFO 0xCC0
 
diff --git a/litex/soc/cores/cpu/minerva/irq.h b/litex/soc/cores/cpu/minerva/irq.h
new file mode 100644
index 000000000..69bac122d
--- /dev/null
+++ b/litex/soc/cores/cpu/minerva/irq.h
@@ -0,0 +1,45 @@
+#ifndef __IRQ_H
+#define __IRQ_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <system.h>
+#include <generated/csr.h>
+#include <generated/soc.h>
+
+static inline unsigned int irq_getie(void)
+{
+	return (csrr(mstatus) & CSR_MSTATUS_MIE) != 0;
+}
+
+static inline void irq_setie(unsigned int ie)
+{
+	if(ie) csrs(mstatus,CSR_MSTATUS_MIE); else csrc(mstatus,CSR_MSTATUS_MIE);
+}
+
+static inline unsigned int irq_getmask(void)
+{
+	unsigned int mask;
+	asm volatile ("csrr %0, %1" : "=r"(mask) : "i"(CSR_IRQ_MASK));
+	return mask;
+}
+
+static inline void irq_setmask(unsigned int mask)
+{
+	asm volatile ("csrw %0, %1" :: "i"(CSR_IRQ_MASK), "r"(mask));
+}
+
+static inline unsigned int irq_pending(void)
+{
+	unsigned int pending;
+	asm volatile ("csrr %0, %1" : "=r"(pending) : "i"(CSR_IRQ_PENDING));
+	return pending;
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __IRQ_H */
diff --git a/litex/soc/cores/cpu/minerva/system.h b/litex/soc/cores/cpu/minerva/system.h
new file mode 100644
index 000000000..cccdb54d2
--- /dev/null
+++ b/litex/soc/cores/cpu/minerva/system.h
@@ -0,0 +1,42 @@
+#ifndef __SYSTEM_H
+#define __SYSTEM_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+void flush_cpu_icache(void);
+void flush_cpu_dcache(void);
+void flush_l2_cache(void);
+
+void busy_wait(unsigned int ms);
+
+#include <csr-defs.h>
+
+#define csrr(reg) ({ unsigned long __tmp; \
+  asm volatile ("csrr %0, " #reg : "=r"(__tmp)); \
+  __tmp; })
+
+#define csrw(reg, val) ({ \
+  if (__builtin_constant_p(val) && (unsigned long)(val) < 32) \
+	asm volatile ("csrw " #reg ", %0" :: "i"(val)); \
+  else \
+	asm volatile ("csrw " #reg ", %0" :: "r"(val)); })
+
+#define csrs(reg, bit) ({ \
+  if (__builtin_constant_p(bit) && (unsigned long)(bit) < 32) \
+	asm volatile ("csrrs x0, " #reg ", %0" :: "i"(bit)); \
+  else \
+	asm volatile ("csrrs x0, " #reg ", %0" :: "r"(bit)); })
+
+#define csrc(reg, bit) ({ \
+  if (__builtin_constant_p(bit) && (unsigned long)(bit) < 32) \
+	asm volatile ("csrrc x0, " #reg ", %0" :: "i"(bit)); \
+  else \
+	asm volatile ("csrrc x0, " #reg ", %0" :: "r"(bit)); })
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __SYSTEM_H */
diff --git a/litex/soc/software/bios/boot-helper-mor1kx.S b/litex/soc/cores/cpu/mor1kx/boot-helper.S
similarity index 100%
rename from litex/soc/software/bios/boot-helper-mor1kx.S
rename to litex/soc/cores/cpu/mor1kx/boot-helper.S
diff --git a/litex/soc/software/libbase/crt0-mor1kx.S b/litex/soc/cores/cpu/mor1kx/crt0.S
similarity index 100%
rename from litex/soc/software/libbase/crt0-mor1kx.S
rename to litex/soc/cores/cpu/mor1kx/crt0.S
diff --git a/litex/soc/cores/cpu/mor1kx/irq.h b/litex/soc/cores/cpu/mor1kx/irq.h
new file mode 100644
index 000000000..acc64c0a7
--- /dev/null
+++ b/litex/soc/cores/cpu/mor1kx/irq.h
@@ -0,0 +1,44 @@
+#ifndef __IRQ_H
+#define __IRQ_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <system.h>
+#include <generated/csr.h>
+#include <generated/soc.h>
+
+static inline unsigned int irq_getie(void)
+{
+	return !!(mfspr(SPR_SR) & SPR_SR_IEE);
+}
+
+static inline void irq_setie(unsigned int ie)
+{
+	if (ie & 0x1)
+		mtspr(SPR_SR, mfspr(SPR_SR) | SPR_SR_IEE);
+	else
+		mtspr(SPR_SR, mfspr(SPR_SR) & ~SPR_SR_IEE);
+}
+
+static inline unsigned int irq_getmask(void)
+{
+	return mfspr(SPR_PICMR);
+}
+
+static inline void irq_setmask(unsigned int mask)
+{
+	mtspr(SPR_PICMR, mask);
+}
+
+static inline unsigned int irq_pending(void)
+{
+	return mfspr(SPR_PICSR);
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __IRQ_H */
diff --git a/litex/soc/cores/cpu/mor1kx/system.h b/litex/soc/cores/cpu/mor1kx/system.h
new file mode 100644
index 000000000..004a00e3c
--- /dev/null
+++ b/litex/soc/cores/cpu/mor1kx/system.h
@@ -0,0 +1,33 @@
+#ifndef __SYSTEM_H
+#define __SYSTEM_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+void flush_cpu_icache(void);
+void flush_cpu_dcache(void);
+void flush_l2_cache(void);
+
+void busy_wait(unsigned int ms);
+
+#include <spr-defs.h>
+static inline unsigned long mfspr(unsigned long add)
+{
+	unsigned long ret;
+
+	__asm__ __volatile__ ("l.mfspr %0,%1,0" : "=r" (ret) : "r" (add));
+
+	return ret;
+}
+
+static inline void mtspr(unsigned long add, unsigned long val)
+{
+	__asm__ __volatile__ ("l.mtspr %0,%1,0" : : "r" (add), "r" (val));
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __SYSTEM_H */
diff --git a/litex/soc/software/bios/boot-helper-picorv32.S b/litex/soc/cores/cpu/picorv32/boot-helper.S
similarity index 100%
rename from litex/soc/software/bios/boot-helper-picorv32.S
rename to litex/soc/cores/cpu/picorv32/boot-helper.S
diff --git a/litex/soc/software/libbase/crt0-picorv32.S b/litex/soc/cores/cpu/picorv32/crt0.S
similarity index 99%
rename from litex/soc/software/libbase/crt0-picorv32.S
rename to litex/soc/cores/cpu/picorv32/crt0.S
index 3f7a4f5c0..49883ed09 100644
--- a/litex/soc/software/libbase/crt0-picorv32.S
+++ b/litex/soc/cores/cpu/picorv32/crt0.S
@@ -5,7 +5,7 @@
  * purpose with or without fee is hereby granted.
  */
 
-#include "picorv32-extraops.S"
+#include "extraops.S"
 
 /*
  * Interrupt vector.
diff --git a/litex/soc/software/include/base/picorv32-extraops.S b/litex/soc/cores/cpu/picorv32/extraops.S
similarity index 100%
rename from litex/soc/software/include/base/picorv32-extraops.S
rename to litex/soc/cores/cpu/picorv32/extraops.S
diff --git a/litex/soc/cores/cpu/picorv32/irq.h b/litex/soc/cores/cpu/picorv32/irq.h
new file mode 100644
index 000000000..0badb1320
--- /dev/null
+++ b/litex/soc/cores/cpu/picorv32/irq.h
@@ -0,0 +1,67 @@
+#ifndef __IRQ_H
+#define __IRQ_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <system.h>
+#include <generated/csr.h>
+#include <generated/soc.h>
+
+// PicoRV32 has a very limited interrupt support, implemented via custom
+// instructions. It also doesn't have a global interrupt enable/disable, so
+// we have to emulate it via saving and restoring a mask and using 0/~1 as a
+// hardware mask.
+// Due to all this somewhat low-level mess, all of the glue is implemented in
+// the RiscV crt0, and this header is kept as a thin wrapper. Since interrupts
+// managed by this layer, do not call interrupt instructions directly, as the
+// state will go out of sync with the hardware.
+
+// Read only.
+extern unsigned int _irq_pending;
+// Read only.
+extern unsigned int _irq_mask;
+// Read only.
+extern unsigned int _irq_enabled;
+extern void _irq_enable(void);
+extern void _irq_disable(void);
+extern void _irq_setmask(unsigned int);
+
+static inline unsigned int irq_getie(void)
+{
+	return _irq_enabled != 0;
+}
+
+static inline void irq_setie(unsigned int ie)
+{
+    if (ie & 0x1)
+        _irq_enable();
+    else
+        _irq_disable();
+}
+
+static inline unsigned int irq_getmask(void)
+{
+    // PicoRV32 interrupt mask bits are high-disabled. This is the inverse of how
+    // LiteX sees things.
+    return ~_irq_mask;
+}
+
+static inline void irq_setmask(unsigned int mask)
+{
+    // PicoRV32 interrupt mask bits are high-disabled. This is the inverse of how
+    // LiteX sees things.
+    _irq_setmask(~mask);
+}
+
+static inline unsigned int irq_pending(void)
+{
+	return _irq_pending;
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __IRQ_H */
diff --git a/litex/soc/cores/cpu/picorv32/system.h b/litex/soc/cores/cpu/picorv32/system.h
new file mode 100644
index 000000000..989c9c621
--- /dev/null
+++ b/litex/soc/cores/cpu/picorv32/system.h
@@ -0,0 +1,18 @@
+#ifndef __SYSTEM_H
+#define __SYSTEM_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+void flush_cpu_icache(void);
+void flush_cpu_dcache(void);
+void flush_l2_cache(void);
+
+void busy_wait(unsigned int ms);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __SYSTEM_H */
diff --git a/litex/soc/software/bios/boot-helper-rocket.S b/litex/soc/cores/cpu/rocket/boot-helper.S
similarity index 100%
rename from litex/soc/software/bios/boot-helper-rocket.S
rename to litex/soc/cores/cpu/rocket/boot-helper.S
diff --git a/litex/soc/software/libbase/crt0-rocket.S b/litex/soc/cores/cpu/rocket/crt0.S
similarity index 100%
rename from litex/soc/software/libbase/crt0-rocket.S
rename to litex/soc/cores/cpu/rocket/crt0.S
diff --git a/litex/soc/cores/cpu/rocket/csr-defs.h b/litex/soc/cores/cpu/rocket/csr-defs.h
new file mode 100644
index 000000000..170bd4540
--- /dev/null
+++ b/litex/soc/cores/cpu/rocket/csr-defs.h
@@ -0,0 +1,8 @@
+#ifndef CSR_DEFS__H
+#define CSR_DEFS__H
+
+#define CSR_MSTATUS_MIE 0x8
+
+#define CSR_DCACHE_INFO 0xCC0
+
+#endif	/* CSR_DEFS__H */
diff --git a/litex/soc/cores/cpu/rocket/irq.h b/litex/soc/cores/cpu/rocket/irq.h
new file mode 100644
index 000000000..9548b01fd
--- /dev/null
+++ b/litex/soc/cores/cpu/rocket/irq.h
@@ -0,0 +1,50 @@
+#ifndef __IRQ_H
+#define __IRQ_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <system.h>
+#include <generated/csr.h>
+#include <generated/soc.h>
+
+// The RocketChip uses a Platform-Level Interrupt Controller (PLIC) which
+// is programmed and queried via a set of MMIO registers.
+
+#define PLIC_BASE    0x0c000000L // Base address and per-pin priority array
+#define PLIC_PENDING 0x0c001000L // Bit field matching currently pending pins
+#define PLIC_ENABLED 0x0c002000L // Bit field corresponding to the current mask
+#define PLIC_THRSHLD 0x0c200000L // Per-pin priority must be >= this to trigger
+#define PLIC_CLAIM   0x0c200004L // Claim & completion register address
+
+static inline unsigned int irq_getie(void)
+{
+	return (csrr(mstatus) & CSR_MSTATUS_MIE) != 0;
+}
+
+static inline void irq_setie(unsigned int ie)
+{
+	if(ie) csrs(mstatus,CSR_MSTATUS_MIE); else csrc(mstatus,CSR_MSTATUS_MIE);
+}
+
+static inline unsigned int irq_getmask(void)
+{
+	return *((unsigned int *)PLIC_ENABLED) >> 1;
+}
+
+static inline void irq_setmask(unsigned int mask)
+{
+	*((unsigned int *)PLIC_ENABLED) = mask << 1;
+}
+
+static inline unsigned int irq_pending(void)
+{
+	return *((unsigned int *)PLIC_PENDING) >> 1;
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __IRQ_H */
diff --git a/litex/soc/cores/cpu/rocket/system.h b/litex/soc/cores/cpu/rocket/system.h
new file mode 100644
index 000000000..cccdb54d2
--- /dev/null
+++ b/litex/soc/cores/cpu/rocket/system.h
@@ -0,0 +1,42 @@
+#ifndef __SYSTEM_H
+#define __SYSTEM_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+void flush_cpu_icache(void);
+void flush_cpu_dcache(void);
+void flush_l2_cache(void);
+
+void busy_wait(unsigned int ms);
+
+#include <csr-defs.h>
+
+#define csrr(reg) ({ unsigned long __tmp; \
+  asm volatile ("csrr %0, " #reg : "=r"(__tmp)); \
+  __tmp; })
+
+#define csrw(reg, val) ({ \
+  if (__builtin_constant_p(val) && (unsigned long)(val) < 32) \
+	asm volatile ("csrw " #reg ", %0" :: "i"(val)); \
+  else \
+	asm volatile ("csrw " #reg ", %0" :: "r"(val)); })
+
+#define csrs(reg, bit) ({ \
+  if (__builtin_constant_p(bit) && (unsigned long)(bit) < 32) \
+	asm volatile ("csrrs x0, " #reg ", %0" :: "i"(bit)); \
+  else \
+	asm volatile ("csrrs x0, " #reg ", %0" :: "r"(bit)); })
+
+#define csrc(reg, bit) ({ \
+  if (__builtin_constant_p(bit) && (unsigned long)(bit) < 32) \
+	asm volatile ("csrrc x0, " #reg ", %0" :: "i"(bit)); \
+  else \
+	asm volatile ("csrrc x0, " #reg ", %0" :: "r"(bit)); })
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __SYSTEM_H */
diff --git a/litex/soc/software/bios/boot-helper-serv.S b/litex/soc/cores/cpu/serv/boot-helper.S
similarity index 100%
rename from litex/soc/software/bios/boot-helper-serv.S
rename to litex/soc/cores/cpu/serv/boot-helper.S
diff --git a/litex/soc/software/libbase/crt0-serv.S b/litex/soc/cores/cpu/serv/crt0.S
similarity index 100%
rename from litex/soc/software/libbase/crt0-serv.S
rename to litex/soc/cores/cpu/serv/crt0.S
diff --git a/litex/soc/cores/cpu/serv/irq.h b/litex/soc/cores/cpu/serv/irq.h
new file mode 100644
index 000000000..7374cf506
--- /dev/null
+++ b/litex/soc/cores/cpu/serv/irq.h
@@ -0,0 +1,4 @@
+#ifndef __IRQ_H
+#define __IRQ_H
+
+#endif /* __IRQ_H */
diff --git a/litex/soc/cores/cpu/serv/system.h b/litex/soc/cores/cpu/serv/system.h
new file mode 100644
index 000000000..989c9c621
--- /dev/null
+++ b/litex/soc/cores/cpu/serv/system.h
@@ -0,0 +1,18 @@
+#ifndef __SYSTEM_H
+#define __SYSTEM_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+void flush_cpu_icache(void);
+void flush_cpu_dcache(void);
+void flush_l2_cache(void);
+
+void busy_wait(unsigned int ms);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __SYSTEM_H */
diff --git a/litex/soc/software/bios/boot-helper-vexriscv.S b/litex/soc/cores/cpu/vexriscv/boot-helper.S
similarity index 100%
rename from litex/soc/software/bios/boot-helper-vexriscv.S
rename to litex/soc/cores/cpu/vexriscv/boot-helper.S
diff --git a/litex/soc/software/libbase/crt0-vexriscv.S b/litex/soc/cores/cpu/vexriscv/crt0.S
similarity index 100%
rename from litex/soc/software/libbase/crt0-vexriscv.S
rename to litex/soc/cores/cpu/vexriscv/crt0.S
diff --git a/litex/soc/cores/cpu/vexriscv/csr-defs.h b/litex/soc/cores/cpu/vexriscv/csr-defs.h
new file mode 100644
index 000000000..d98e8dfb7
--- /dev/null
+++ b/litex/soc/cores/cpu/vexriscv/csr-defs.h
@@ -0,0 +1,11 @@
+#ifndef CSR_DEFS__H
+#define CSR_DEFS__H
+
+#define CSR_MSTATUS_MIE 0x8
+
+#define CSR_IRQ_MASK 0xBC0
+#define CSR_IRQ_PENDING 0xFC0
+
+#define CSR_DCACHE_INFO 0xCC0
+
+#endif	/* CSR_DEFS__H */
diff --git a/litex/soc/cores/cpu/vexriscv/irq.h b/litex/soc/cores/cpu/vexriscv/irq.h
new file mode 100644
index 000000000..69bac122d
--- /dev/null
+++ b/litex/soc/cores/cpu/vexriscv/irq.h
@@ -0,0 +1,45 @@
+#ifndef __IRQ_H
+#define __IRQ_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <system.h>
+#include <generated/csr.h>
+#include <generated/soc.h>
+
+static inline unsigned int irq_getie(void)
+{
+	return (csrr(mstatus) & CSR_MSTATUS_MIE) != 0;
+}
+
+static inline void irq_setie(unsigned int ie)
+{
+	if(ie) csrs(mstatus,CSR_MSTATUS_MIE); else csrc(mstatus,CSR_MSTATUS_MIE);
+}
+
+static inline unsigned int irq_getmask(void)
+{
+	unsigned int mask;
+	asm volatile ("csrr %0, %1" : "=r"(mask) : "i"(CSR_IRQ_MASK));
+	return mask;
+}
+
+static inline void irq_setmask(unsigned int mask)
+{
+	asm volatile ("csrw %0, %1" :: "i"(CSR_IRQ_MASK), "r"(mask));
+}
+
+static inline unsigned int irq_pending(void)
+{
+	unsigned int pending;
+	asm volatile ("csrr %0, %1" : "=r"(pending) : "i"(CSR_IRQ_PENDING));
+	return pending;
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __IRQ_H */
diff --git a/litex/soc/cores/cpu/vexriscv/system.h b/litex/soc/cores/cpu/vexriscv/system.h
new file mode 100644
index 000000000..cccdb54d2
--- /dev/null
+++ b/litex/soc/cores/cpu/vexriscv/system.h
@@ -0,0 +1,42 @@
+#ifndef __SYSTEM_H
+#define __SYSTEM_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+void flush_cpu_icache(void);
+void flush_cpu_dcache(void);
+void flush_l2_cache(void);
+
+void busy_wait(unsigned int ms);
+
+#include <csr-defs.h>
+
+#define csrr(reg) ({ unsigned long __tmp; \
+  asm volatile ("csrr %0, " #reg : "=r"(__tmp)); \
+  __tmp; })
+
+#define csrw(reg, val) ({ \
+  if (__builtin_constant_p(val) && (unsigned long)(val) < 32) \
+	asm volatile ("csrw " #reg ", %0" :: "i"(val)); \
+  else \
+	asm volatile ("csrw " #reg ", %0" :: "r"(val)); })
+
+#define csrs(reg, bit) ({ \
+  if (__builtin_constant_p(bit) && (unsigned long)(bit) < 32) \
+	asm volatile ("csrrs x0, " #reg ", %0" :: "i"(bit)); \
+  else \
+	asm volatile ("csrrs x0, " #reg ", %0" :: "r"(bit)); })
+
+#define csrc(reg, bit) ({ \
+  if (__builtin_constant_p(bit) && (unsigned long)(bit) < 32) \
+	asm volatile ("csrrc x0, " #reg ", %0" :: "i"(bit)); \
+  else \
+	asm volatile ("csrrc x0, " #reg ", %0" :: "r"(bit)); })
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __SYSTEM_H */
diff --git a/litex/soc/integration/export.py b/litex/soc/integration/export.py
index 2761443a5..9117d82e3 100644
--- a/litex/soc/integration/export.py
+++ b/litex/soc/integration/export.py
@@ -15,6 +15,7 @@
 
 import os
 import json
+import inspect
 from shutil import which
 from sysconfig import get_platform
 
@@ -85,7 +86,8 @@ def get_cpu_mak(cpu, compile_software):
         ("CPU", cpu.name),
         ("CPUFLAGS", flags),
         ("CPUENDIANNESS", cpu.endianness),
-        ("CLANG", str(int(clang)))
+        ("CLANG", str(int(clang))),
+        ("CPU_DIRECTORY", os.path.dirname(inspect.getfile(cpu.__class__))),
     ]
 
 
diff --git a/litex/soc/software/bios/Makefile b/litex/soc/software/bios/Makefile
index 12510a712..cc3b973aa 100755
--- a/litex/soc/software/bios/Makefile
+++ b/litex/soc/software/bios/Makefile
@@ -2,7 +2,7 @@ include ../include/generated/variables.mak
 include $(SOC_DIRECTORY)/software/common.mak
 
 ifeq ($(CPU),blackparrot)
-BP_LIBS =  -L$(BP_EXTERNAL_DIR)/lib/gcc/riscv64-unknown-elf/8.3.0 
+BP_LIBS  = -L$(BP_EXTERNAL_DIR)/lib/gcc/riscv64-unknown-elf/8.3.0
 BP_FLAGS = -lgcc
 endif
 # Permit TFTP_SERVER_PORT override from shell environment / command line
@@ -10,7 +10,7 @@ ifdef TFTP_SERVER_PORT
 CFLAGS += -DTFTP_SERVER_PORT=$(TFTP_SERVER_PORT)
 endif
 
-OBJECTS=isr.o sdram.o sdcard.o main.o boot-helper-$(CPU).o boot.o
+OBJECTS=isr.o sdram.o sdcard.o main.o boot-helper.o boot.o
 
 all: bios.bin
 	$(PYTHON) -m litex.soc.software.memusage bios.elf $(CURDIR)/../include/generated/regions.ld $(TRIPLE)
@@ -29,9 +29,9 @@ endif
 bios.elf: $(BIOS_DIRECTORY)/linker.ld $(OBJECTS)
 
 
-%.elf: ../libbase/crt0-$(CPU)-ctr.o ../libnet/libnet.a ../libbase/libbase-nofloat.a ../libcompiler_rt/libcompiler_rt.a
+%.elf: ../libbase/crt0-ctr.o ../libnet/libnet.a ../libbase/libbase-nofloat.a ../libcompiler_rt/libcompiler_rt.a
 	$(LD) $(LDFLAGS) -T $(BIOS_DIRECTORY)/linker.ld -N -o $@ \
-		../libbase/crt0-$(CPU)-ctr.o \
+		../libbase/crt0-ctr.o \
 		$(OBJECTS) \
 		-L../libnet \
 		-L../libbase \
@@ -39,7 +39,7 @@ bios.elf: $(BIOS_DIRECTORY)/linker.ld $(OBJECTS)
 		$(BP_LIBS) \
 		-lnet -lbase-nofloat -lcompiler_rt \
 		$(BP_FLAGS)
-	
+
 ifneq ($(OS),Windows_NT)
 	chmod -x $@
 endif
@@ -53,6 +53,10 @@ endif
 %.o: $(BIOS_DIRECTORY)/%.S
 	$(assemble)
 
+boot-helper.o: $(CPU_DIRECTORY)/boot-helper.S
+	cp $(CPU_DIRECTORY)/boot-helper.S $(BIOS_DIRECTORY)/boot-helper.S
+	$(assemble)
+
 clean:
 	$(RM) $(OBJECTS) bios.elf bios.bin .*~ *~
 
diff --git a/litex/soc/software/bios/sdram.c b/litex/soc/software/bios/sdram.c
index 8d8ddfefe..513a12665 100644
--- a/litex/soc/software/bios/sdram.c
+++ b/litex/soc/software/bios/sdram.c
@@ -29,6 +29,7 @@
 
 __attribute__((unused)) static void cdelay(int i)
 {
+	/* FIXME: move nop definitions to CPUs */
 	while(i > 0) {
 #if defined (__lm32__)
 		__asm__ volatile("nop");
diff --git a/litex/soc/software/common.mak b/litex/soc/software/common.mak
index 18fc50c3f..83f1aba42 100644
--- a/litex/soc/software/common.mak
+++ b/litex/soc/software/common.mak
@@ -45,7 +45,7 @@ DEPFLAGS += -MD -MP
 
 # Toolchain options
 #
-INCLUDES = -I$(SOC_DIRECTORY)/software/include/base -I$(SOC_DIRECTORY)/software/include -I$(SOC_DIRECTORY)/common -I$(BUILDINC_DIRECTORY)
+INCLUDES = -I$(SOC_DIRECTORY)/software/include/base -I$(SOC_DIRECTORY)/software/include -I$(SOC_DIRECTORY)/common -I$(BUILDINC_DIRECTORY) -I$(CPU_DIRECTORY)
 COMMONFLAGS = $(DEPFLAGS) -Os $(CPUFLAGS) -g3 -fomit-frame-pointer -Wall -fno-builtin -nostdinc $(INCLUDES)
 CFLAGS = $(COMMONFLAGS) -fexceptions -Wstrict-prototypes -Wold-style-definition -Wmissing-prototypes
 CXXFLAGS = $(COMMONFLAGS) -std=c++11 -I$(SOC_DIRECTORY)/software/include/basec++ -fexceptions -fno-rtti -ffreestanding
diff --git a/litex/soc/software/include/base/irq.h b/litex/soc/software/include/base/irq.h
deleted file mode 100644
index 9fd8e1805..000000000
--- a/litex/soc/software/include/base/irq.h
+++ /dev/null
@@ -1,196 +0,0 @@
-#ifndef __IRQ_H
-#define __IRQ_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#include <system.h>
-#include <generated/csr.h>
-#include <generated/soc.h>
-
-#ifdef CONFIG_CPU_HAS_INTERRUPT
-
-#ifdef __picorv32__
-// PicoRV32 has a very limited interrupt support, implemented via custom
-// instructions. It also doesn't have a global interrupt enable/disable, so
-// we have to emulate it via saving and restoring a mask and using 0/~1 as a
-// hardware mask.
-// Due to all this somewhat low-level mess, all of the glue is implemented in
-// the RiscV crt0, and this header is kept as a thin wrapper. Since interrupts
-// managed by this layer, do not call interrupt instructions directly, as the
-// state will go out of sync with the hardware.
-
-// Read only.
-extern unsigned int _irq_pending;
-// Read only.
-extern unsigned int _irq_mask;
-// Read only.
-extern unsigned int _irq_enabled;
-extern void _irq_enable(void);
-extern void _irq_disable(void);
-extern void _irq_setmask(unsigned int);
-#endif
-
-#ifdef __rocket__
-// The RocketChip uses a Platform-Level Interrupt Controller (PLIC) which
-// is programmed and queried via a set of MMIO registers.
-
-#define PLIC_BASE    0x0c000000L // Base address and per-pin priority array
-#define PLIC_PENDING 0x0c001000L // Bit field matching currently pending pins
-#define PLIC_ENABLED 0x0c002000L // Bit field corresponding to the current mask
-#define PLIC_THRSHLD 0x0c200000L // Per-pin priority must be >= this to trigger
-#define PLIC_CLAIM   0x0c200004L // Claim & completion register address
-#endif /* __rocket__ */
-
-
-#ifdef __blackparrot__
-// The RocketChip uses a Platform-Level Interrupt Controller (PLIC) which
-// is programmed and queried via a set of MMIO registers.
-// TODO: How about Blackparrot? Should be probably included in linux version
-
-#define PLIC_BASE    0x0c000000L // Base address and per-pin priority array
-#define PLIC_PENDING 0x0c001000L // Bit field matching currently pending pins
-#define PLIC_ENABLED 0x0c002000L // Bit field corresponding to the current mask
-#define PLIC_THRSHLD 0x0c200000L // Per-pin priority must be >= this to trigger
-#define PLIC_CLAIM   0x0c200004L // Claim & completion register address
-#endif /* __blackparrot__ */
-
-
-
-static inline unsigned int irq_getie(void)
-{
-#if defined (__lm32__)
-	unsigned int ie;
-	__asm__ __volatile__("rcsr %0, IE" : "=r" (ie));
-	return ie;
-#elif defined (__or1k__)
-	return !!(mfspr(SPR_SR) & SPR_SR_IEE);
-#elif defined (__picorv32__)
-	return _irq_enabled != 0;
-#elif defined (__vexriscv__)
-	return (csrr(mstatus) & CSR_MSTATUS_MIE) != 0;
-#elif defined (__minerva__)
-	return (csrr(mstatus) & CSR_MSTATUS_MIE) != 0;
-#elif defined (__rocket__)
-	return (csrr(mstatus) & CSR_MSTATUS_MIE) != 0;
-#elif defined (__blackparrot__)
-	return (csrr(mstatus) & CSR_MSTATUS_MIE) != 0; /* FIXME */
-#else
-#error Unsupported architecture
-#endif
-}
-
-static inline void irq_setie(unsigned int ie)
-{
-#if defined (__lm32__)
-	__asm__ __volatile__("wcsr IE, %0" : : "r" (ie));
-#elif defined (__or1k__)
-	if (ie & 0x1)
-		mtspr(SPR_SR, mfspr(SPR_SR) | SPR_SR_IEE);
-	else
-		mtspr(SPR_SR, mfspr(SPR_SR) & ~SPR_SR_IEE);
-#elif defined (__picorv32__)
-    if (ie & 0x1)
-        _irq_enable();
-    else
-        _irq_disable();
-#elif defined (__vexriscv__)
-	if(ie) csrs(mstatus,CSR_MSTATUS_MIE); else csrc(mstatus,CSR_MSTATUS_MIE);
-#elif defined (__minerva__)
-	if(ie) csrs(mstatus,CSR_MSTATUS_MIE); else csrc(mstatus,CSR_MSTATUS_MIE);
-#elif defined (__rocket__)
-	if(ie) csrs(mstatus,CSR_MSTATUS_MIE); else csrc(mstatus,CSR_MSTATUS_MIE);
-#elif defined (__blackparrot__)
-	if(ie) csrs(mstatus,CSR_MSTATUS_MIE); else csrc(mstatus,CSR_MSTATUS_MIE); /* FIXME */
-#else
-#error Unsupported architecture
-#endif
-}
-
-static inline unsigned int irq_getmask(void)
-{
-#if defined (__lm32__)
-	unsigned int mask;
-	__asm__ __volatile__("rcsr %0, IM" : "=r" (mask));
-	return mask;
-#elif defined (__or1k__)
-	return mfspr(SPR_PICMR);
-#elif defined (__picorv32__)
-    // PicoRV32 interrupt mask bits are high-disabled. This is the inverse of how
-    // LiteX sees things.
-    return ~_irq_mask;
-#elif defined (__vexriscv__)
-	unsigned int mask;
-	asm volatile ("csrr %0, %1" : "=r"(mask) : "i"(CSR_IRQ_MASK));
-	return mask;
-#elif defined (__minerva__)
-	unsigned int mask;
-	asm volatile ("csrr %0, %1" : "=r"(mask) : "i"(CSR_IRQ_MASK));
-	return mask;
-#elif defined (__rocket__)
-	return *((unsigned int *)PLIC_ENABLED) >> 1;
-#elif defined (__blackparrot__)
-	return 0; /* FIXME */
-#else
-#error Unsupported architecture
-#endif
-}
-
-static inline void irq_setmask(unsigned int mask)
-{
-#if defined (__lm32__)
-	__asm__ __volatile__("wcsr IM, %0" : : "r" (mask));
-#elif defined (__or1k__)
-	mtspr(SPR_PICMR, mask);
-#elif defined (__picorv32__)
-    // PicoRV32 interrupt mask bits are high-disabled. This is the inverse of how
-    // LiteX sees things.
-    _irq_setmask(~mask);
-#elif defined (__vexriscv__)
-	asm volatile ("csrw %0, %1" :: "i"(CSR_IRQ_MASK), "r"(mask));
-#elif defined (__minerva__)
-	asm volatile ("csrw %0, %1" :: "i"(CSR_IRQ_MASK), "r"(mask));
-#elif defined (__rocket__)
-	*((unsigned int *)PLIC_ENABLED) = mask << 1;
-#elif defined (__blackparrot__)
-	/* FIXME */
-#else
-#error Unsupported architecture
-#endif
-}
-
-static inline unsigned int irq_pending(void)
-{
-#if defined (__lm32__)
-	unsigned int pending;
-	__asm__ __volatile__("rcsr %0, IP" : "=r" (pending));
-	return pending;
-#elif defined (__or1k__)
-	return mfspr(SPR_PICSR);
-#elif defined (__picorv32__)
-	return _irq_pending;
-#elif defined (__vexriscv__)
-	unsigned int pending;
-	asm volatile ("csrr %0, %1" : "=r"(pending) : "i"(CSR_IRQ_PENDING));
-	return pending;
-#elif defined (__minerva__)
-	unsigned int pending;
-	asm volatile ("csrr %0, %1" : "=r"(pending) : "i"(CSR_IRQ_PENDING));
-	return pending;
-#elif defined (__rocket__)
-	return *((unsigned int *)PLIC_PENDING) >> 1;
-#elif defined (__blackparrot__)
-	return csr_readl(PLIC_PENDING) >> 1; /* FIXME */
-#else
-#error Unsupported architecture
-#endif
-}
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif
-
-#endif /* __IRQ_H */
diff --git a/litex/soc/software/libbase/Makefile b/litex/soc/software/libbase/Makefile
index e3a80a039..e81a5316e 100755
--- a/litex/soc/software/libbase/Makefile
+++ b/litex/soc/software/libbase/Makefile
@@ -4,7 +4,7 @@ include $(SOC_DIRECTORY)/software/common.mak
 OBJECTS=exception.o libc.o errno.o crc16.o crc32.o console.o \
 	system.o id.o uart.o time.o qsort.o strtod.o spiflash.o spisdcard.o strcasecmp.o mdio.o
 
-all: crt0-$(CPU)-ctr.o crt0-$(CPU)-xip.o libbase.a libbase-nofloat.a
+all: crt0-ctr.o crt0-xip.o libbase.a libbase-nofloat.a
 
 libbase.a: $(OBJECTS) vsnprintf.o
 	$(AR) crs libbase.a $(OBJECTS) vsnprintf.o
@@ -24,10 +24,12 @@ vsnprintf-nofloat.o: $(LIBBASE_DIRECTORY)/vsnprintf.c
 %.o: $(LIBBASE_DIRECTORY)/%.S
 	$(assemble)
 
-crt0-$(CPU)-ctr.o: $(LIBBASE_DIRECTORY)/crt0-$(CPU).S
+crt0-ctr.o: $(CPU_DIRECTORY)/crt0.S
+	cp $(CPU_DIRECTORY)/crt0.S $(LIBBASE_DIRECTORY)/crt0-crt.S
 	$(assemble)
 
-crt0-$(CPU)-xip.o: $(LIBBASE_DIRECTORY)/crt0-$(CPU).S
+crt0-xip.o: $(CPU_DIRECTORY)/crt0.S
+	cp $(CPU_DIRECTORY)/crt0.S $(LIBBASE_DIRECTORY)/crt0-xip.S
 	$(CC) -c -DEXECUTE_IN_PLACE $(CFLAGS) -o $@ $<
 
 .PHONY: all clean

From e764eabda1aaeaa9d7ccb63ab276e23696d43339 Mon Sep 17 00:00:00 2001
From: Franck Jullien <franck.jullien@gmail.com>
Date: Mon, 27 Apr 2020 21:52:36 +0200
Subject: [PATCH 50/95] builder: add a parameter to pass options to BIOS
 Makefile

---
 litex/soc/integration/builder.py | 8 +++++++-
 1 file changed, 7 insertions(+), 1 deletion(-)

diff --git a/litex/soc/integration/builder.py b/litex/soc/integration/builder.py
index 745eb75e9..4fd1b2330 100644
--- a/litex/soc/integration/builder.py
+++ b/litex/soc/integration/builder.py
@@ -49,7 +49,8 @@ class Builder:
         csr_json         = None,
         csr_csv          = None,
         csr_svd          = None,
-        memory_x         = None):
+        memory_x         = None,
+        bios_options     = None):
         self.soc = soc
 
         # From Python doc: makedirs() will become confused if the path
@@ -66,6 +67,7 @@ class Builder:
         self.csr_json = csr_json
         self.csr_svd  = csr_svd
         self.memory_x = memory_x
+        self.bios_options = bios_options
 
         self.software_packages = []
         for name in soc_software_packages:
@@ -110,6 +112,10 @@ class Builder:
             for name, src_dir in self.software_packages:
                 define(name.upper() + "_DIRECTORY", src_dir)
 
+            if self.bios_options is not None:
+                for option in self.bios_options:
+                    define(option, "1")
+
             write_to_file(
                 os.path.join(self.generated_dir, "variables.mak"),
                 "".join(variables_contents))

From bc5a1986e237931554f7362e3bde44ba56fed5a7 Mon Sep 17 00:00:00 2001
From: Franck Jullien <franck.jullien@gmail.com>
Date: Tue, 28 Apr 2020 23:03:18 +0200
Subject: [PATCH 51/95] bios: add terminal history

Terminal history and characters parsing is done in readline.c.
Passing TERM_NO_HIST disable terminal history.
Passing TERM_MINI use a simple terminal implementation in order to save
more space.
---
 litex/soc/software/bios/Makefile          |  15 +-
 litex/soc/software/bios/main.c            |  61 +---
 litex/soc/software/bios/readline.c        | 331 ++++++++++++++++++++++
 litex/soc/software/bios/readline.h        |  83 ++++++
 litex/soc/software/bios/readline_simple.c |  59 ++++
 5 files changed, 500 insertions(+), 49 deletions(-)
 create mode 100644 litex/soc/software/bios/readline.c
 create mode 100644 litex/soc/software/bios/readline.h
 create mode 100644 litex/soc/software/bios/readline_simple.c

diff --git a/litex/soc/software/bios/Makefile b/litex/soc/software/bios/Makefile
index cc3b973aa..5ede7cd71 100755
--- a/litex/soc/software/bios/Makefile
+++ b/litex/soc/software/bios/Makefile
@@ -2,7 +2,7 @@ include ../include/generated/variables.mak
 include $(SOC_DIRECTORY)/software/common.mak
 
 ifeq ($(CPU),blackparrot)
-BP_LIBS  = -L$(BP_EXTERNAL_DIR)/lib/gcc/riscv64-unknown-elf/8.3.0
+BP_LIBS =  -L$(BP_EXTERNAL_DIR)/lib/gcc/riscv64-unknown-elf/8.3.0 
 BP_FLAGS = -lgcc
 endif
 # Permit TFTP_SERVER_PORT override from shell environment / command line
@@ -12,6 +12,17 @@ endif
 
 OBJECTS=isr.o sdram.o sdcard.o main.o boot-helper.o boot.o
 
+ifdef TERM_NO_HIST
+CFLAGS += -DTERM_NO_HIST
+endif
+
+ifdef TERM_MINI
+CFLAGS += -DTERM_MINI
+OBJECTS += readline_simple.o
+else
+OBJECTS += readline.o
+endif
+
 all: bios.bin
 	$(PYTHON) -m litex.soc.software.memusage bios.elf $(CURDIR)/../include/generated/regions.ld $(TRIPLE)
 
@@ -39,7 +50,7 @@ bios.elf: $(BIOS_DIRECTORY)/linker.ld $(OBJECTS)
 		$(BP_LIBS) \
 		-lnet -lbase-nofloat -lcompiler_rt \
 		$(BP_FLAGS)
-
+	
 ifneq ($(OS),Windows_NT)
 	chmod -x $@
 endif
diff --git a/litex/soc/software/bios/main.c b/litex/soc/software/bios/main.c
index b6501edbb..368031f6a 100644
--- a/litex/soc/software/bios/main.c
+++ b/litex/soc/software/bios/main.c
@@ -10,6 +10,7 @@
 // This file is Copyright (c) 2018 Jean-François Nguyen <jf@lambdaconcept.fr>
 // This file is Copyright (c) 2018 Sergiusz Bazanski <q3k@q3k.org>
 // This file is Copyright (c) 2016 Tim 'mithro' Ansell <mithro@mithis.com>
+// This file is Copyright (c) 2020 Franck Jullien <franck.jullien@gmail.com>
 
 // License: BSD
 
@@ -42,6 +43,7 @@
 #include "sdram.h"
 #include "sdcard.h"
 #include "boot.h"
+#include "readline.h"
 
 /* General address space functions */
 
@@ -548,48 +550,6 @@ static void crcbios(void)
 	}
 }
 
-static void readstr(char *s, int size)
-{
-	static char skip = 0;
-	char c[2];
-	int ptr;
-
-	c[1] = 0;
-	ptr = 0;
-	while(1) {
-		c[0] = readchar();
-		if (c[0] == skip)
-			continue;
-		skip = 0;
-		switch(c[0]) {
-			case 0x7f:
-			case 0x08:
-				if(ptr > 0) {
-					ptr--;
-					putsnonl("\x08 \x08");
-				}
-				break;
-			case 0x07:
-				break;
-			case '\r':
-				skip = '\n';
-				s[ptr] = 0x00;
-				putsnonl("\n");
-				return;
-			case '\n':
-				skip = '\r';
-				s[ptr] = 0x00;
-				putsnonl("\n");
-				return;
-			default:
-				putsnonl(c);
-				s[ptr] = c[0];
-				ptr++;
-				break;
-		}
-	}
-}
-
 static void boot_sequence(void)
 {
 	if(serialboot()) {
@@ -614,7 +574,7 @@ static void boot_sequence(void)
 
 int main(int i, char **c)
 {
-	char buffer[64];
+	char buffer[CMD_LINE_BUFFER_SIZE];
 	int sdr_ok;
 #ifdef CONFIG_CPU_HAS_INTERRUPT
 	irq_setmask(0);
@@ -696,10 +656,17 @@ int main(int i, char **c)
 	}
 
 	printf("--============= \e[1mConsole\e[0m ================--\n");
-    while(1) {
-		putsnonl("\e[92;1mlitex\e[0m> ");
-		readstr(buffer, 64);
-		do_command(buffer);
+#if !defined(TERM_MINI) && !defined(TERM_NO_HIST)
+	hist_init();
+#endif
+	printf("\n%s", PROMPT);
+	while(1) {
+		readline(buffer, CMD_LINE_BUFFER_SIZE);
+		if (buffer[0] != 0) {
+			printf("\n");
+			do_command(buffer);
+		}
+		printf("\n%s", PROMPT);
 	}
 	return 0;
 }
diff --git a/litex/soc/software/bios/readline.c b/litex/soc/software/bios/readline.c
new file mode 100644
index 000000000..998ebc0ef
--- /dev/null
+++ b/litex/soc/software/bios/readline.c
@@ -0,0 +1,331 @@
+// This file is Copyright (c) 2020 Franck Jullien <franck.jullien@gmail.com>
+//
+//     Largely inspired/copied from U-boot and Barebox projects wich are:
+//         Wolfgang Denk, DENX Software Engineering, <wd@denx.de>
+//         Sascha Hauer, Pengutronix, <s.hauer@pengutronix.de>
+//     cmdline-editing related codes from vivi
+//         Author: Janghoon Lyu <nandy@mizi.com>
+
+// SPDX-License-Identifier: BSD-Source-Code
+
+#include <stdlib.h>
+#include <stdio.h>
+#include <string.h>
+#include <ctype.h>
+
+#include <console.h>
+#include <uart.h>
+
+#include "readline.h"
+
+#ifndef TERM_NO_HIST
+static int hist_max = 0;
+static int hist_add_idx = 0;
+static int hist_cur = 0;
+static int hist_num = 0;
+static char hist_lines[HIST_MAX][CMD_LINE_BUFFER_SIZE];
+#endif
+
+#define ARRAY_SIZE(array)  (sizeof(array) / sizeof(array[0]))
+
+static const struct esc_cmds esccmds[] = {
+	{"OA", KEY_UP},       // cursor key Up
+	{"OB", KEY_DOWN},     // cursor key Down
+	{"OC", KEY_RIGHT},    // Cursor Key Right
+	{"OD", KEY_LEFT},     // cursor key Left
+	{"OH", KEY_HOME},     // Cursor Key Home
+	{"OF", KEY_END},      // Cursor Key End
+	{"[A", KEY_UP},       // cursor key Up
+	{"[B", KEY_DOWN},     // cursor key Down
+	{"[C", KEY_RIGHT},    // Cursor Key Right
+	{"[D", KEY_LEFT},     // cursor key Left
+	{"[H", KEY_HOME},     // Cursor Key Home
+	{"[F", KEY_END},      // Cursor Key End
+	{"[1~", KEY_HOME},    // Cursor Key Home
+	{"[2~", KEY_INSERT},  // Cursor Key Insert
+	{"[3~", KEY_DEL},     // Cursor Key Delete
+	{"[4~", KEY_END},     // Cursor Key End
+	{"[5~", KEY_PAGEUP},  // Cursor Key Page Up
+	{"[6~", KEY_PAGEDOWN},// Cursor Key Page Down
+};
+
+static int read_key(void)
+{
+	char c;
+	char esc[5];
+	c = readchar();
+
+	if (c == 27) {
+		int i = 0;
+		esc[i++] = readchar();
+		esc[i++] = readchar();
+		if (isdigit(esc[1])) {
+			while(1) {
+				esc[i] = readchar();
+				if (esc[i++] == '~')
+					break;
+				if (i == ARRAY_SIZE(esc))
+					return -1;
+			}
+		}
+		esc[i] = 0;
+		for (i = 0; i < ARRAY_SIZE(esccmds); i++){
+			if (!strcmp(esc, esccmds[i].seq))
+				return esccmds[i].val;
+		}
+		return -1;
+	}
+	return c;
+}
+
+#ifndef TERM_NO_HIST
+static void cread_add_to_hist(char *line)
+{
+	strcpy(&hist_lines[hist_add_idx][0], line);
+
+	if (++hist_add_idx >= HIST_MAX)
+		hist_add_idx = 0;
+
+	if (hist_add_idx > hist_max)
+		hist_max = hist_add_idx;
+
+	hist_num++;
+}
+
+static char* hist_prev(void)
+{
+	char *ret;
+	int old_cur;
+
+	if (hist_cur < 0)
+		return NULL;
+
+	old_cur = hist_cur;
+	if (--hist_cur < 0)
+		hist_cur = hist_max;
+
+	if (hist_cur == hist_add_idx) {
+		hist_cur = old_cur;
+		ret = NULL;
+	} else {
+		ret = &hist_lines[hist_cur][0];
+	}
+
+	return ret;
+}
+
+static char* hist_next(void)
+{
+	char *ret;
+
+	if (hist_cur < 0)
+		return  NULL;
+
+	if (hist_cur == hist_add_idx)
+		return  NULL;
+
+	if (++hist_cur > hist_max)
+		hist_cur = 0;
+
+	if (hist_cur == hist_add_idx)
+		ret = "";
+	else
+		ret = &hist_lines[hist_cur][0];
+
+	return ret;
+}
+
+void hist_init(void)
+{
+	int i;
+
+	hist_max = 0;
+	hist_add_idx = 0;
+	hist_cur = -1;
+	hist_num = 0;
+
+	for (i = 0; i < HIST_MAX; i++)
+		hist_lines[i][0] = '\0';
+}
+#endif
+
+static void cread_add_char(char ichar, int insert, unsigned long *num,
+			   unsigned long *eol_num, char *buf, unsigned long len)
+{
+	unsigned long wlen;
+
+	if (insert || *num == *eol_num) {
+		if (*eol_num > len - 1) {
+			getcmd_cbeep();
+			return;
+		}
+		(*eol_num)++;
+	}
+
+	if (insert) {
+		wlen = *eol_num - *num;
+		if (wlen > 1) {
+			memmove(&buf[*num+1], &buf[*num], wlen-1);
+		}
+
+		buf[*num] = ichar;
+		putnstr(buf + *num, wlen);
+		(*num)++;
+		while (--wlen) {
+			getcmd_putch(CTL_BACKSPACE);
+		}
+	} else {
+		/* echo the character */
+		wlen = 1;
+		buf[*num] = ichar;
+		putnstr(buf + *num, wlen);
+		(*num)++;
+	}
+}
+
+int readline(char *buf, int len)
+{
+	unsigned long num = 0;
+	unsigned long eol_num = 0;
+	unsigned long wlen;
+	int insert = 1;
+	char ichar;
+
+	while (1) {
+
+		ichar = read_key();
+
+		if ((ichar == '\n') || (ichar == '\r'))
+			break;
+
+		switch (ichar) {
+		case '\t':
+			break;
+
+		case KEY_HOME:
+			BEGINNING_OF_LINE();
+			break;
+		case CTL_CH('c'):	/* ^C - break */
+			*buf = 0;	/* discard input */
+			return -1;
+			break;
+		case KEY_RIGHT:
+			if (num < eol_num) {
+				getcmd_putch(buf[num]);
+				num++;
+			}
+			break;
+		case KEY_LEFT:
+			if (num) {
+				getcmd_putch(CTL_BACKSPACE);
+			 	num--;
+			}
+			break;
+		case CTL_CH('d'):
+			if (num < eol_num) {
+				wlen = eol_num - num - 1;
+				if (wlen) {
+					memmove(&buf[num], &buf[num+1], wlen);
+					putnstr(buf + num, (int)wlen);
+				}
+
+				getcmd_putch(' ');
+				do {
+					getcmd_putch(CTL_BACKSPACE);
+				} while (wlen--);
+				eol_num--;
+			}
+			break;
+		case KEY_ERASE_TO_EOL:
+			ERASE_TO_EOL();
+			break;
+		case KEY_REFRESH_TO_EOL:
+		case KEY_END:
+			REFRESH_TO_EOL();
+			break;
+		case KEY_INSERT:
+			insert = !insert;
+			break;
+		case KEY_ERASE_LINE:
+			BEGINNING_OF_LINE();
+			ERASE_TO_EOL();
+			break;
+		case DEL:
+		case KEY_DEL7:
+		case 8:
+			if (num) {
+				wlen = eol_num - num;
+				num--;
+				memmove(buf + num, buf + num + 1, wlen);
+				getcmd_putch(CTL_BACKSPACE);
+				putnstr(buf + num, (int)wlen);
+				getcmd_putch(' ');
+				do {
+					getcmd_putch(CTL_BACKSPACE);
+				} while (wlen--);
+				eol_num--;
+			}
+			break;
+		case KEY_DEL:
+			if (num < eol_num) {
+				wlen = eol_num - num;
+				memmove(buf + num, buf + num + 1, wlen);
+				putnstr(buf + num, (int)(wlen - 1));
+				getcmd_putch(' ');
+				do {
+					getcmd_putch(CTL_BACKSPACE);
+				} while (--wlen);
+				eol_num--;
+			}
+			break;
+		case KEY_UP:
+		case KEY_DOWN:
+		{
+#ifndef TERM_NO_HIST
+			char * hline;
+			if (ichar == KEY_UP)
+			 	hline = hist_prev();
+			else
+			 	hline = hist_next();
+
+			if (!hline) {
+				getcmd_cbeep();
+				break;
+			}
+
+			/* nuke the current line */
+			/* first, go home */
+			BEGINNING_OF_LINE();
+
+			/* erase to end of line */
+			ERASE_TO_EOL();
+
+			/* copy new line into place and display */
+			strcpy(buf, hline);
+			eol_num = strlen(buf);
+			REFRESH_TO_EOL();
+#endif
+			break;
+		}
+
+		default:
+			if (isascii(ichar) && isprint(ichar))
+				cread_add_char (ichar, insert, &num, &eol_num, buf, len);
+			break;
+		}
+	}
+
+	len = eol_num;
+	buf[eol_num] = '\0';
+
+#ifndef TERM_NO_HIST
+	if (buf[0] && buf[0] != CREAD_HIST_CHAR) 
+		cread_add_to_hist(buf);
+	hist_cur = hist_add_idx;
+#endif
+
+	num = 0;
+	eol_num = 0;
+
+	return len;
+}
diff --git a/litex/soc/software/bios/readline.h b/litex/soc/software/bios/readline.h
new file mode 100644
index 000000000..f1284c5d1
--- /dev/null
+++ b/litex/soc/software/bios/readline.h
@@ -0,0 +1,83 @@
+#ifndef __READLINE_H__
+#define __READLINE_H__
+
+#include <stdlib.h>
+#include <stdio.h>
+
+#define CMD_LINE_BUFFER_SIZE	64
+
+#define PROMPT "\e[92;1mlitex\e[0m> "
+
+#define ESC	27
+
+struct esc_cmds {
+	const char *seq;
+	char val;
+};
+
+#define CTL_CH(c)		((c) - 'a' + 1)
+
+/* Misc. non-Ascii keys */
+#define KEY_UP			CTL_CH('p')	/* cursor key Up	*/
+#define KEY_DOWN		CTL_CH('n')	/* cursor key Down	*/
+#define KEY_RIGHT		CTL_CH('f')	/* Cursor Key Right	*/
+#define KEY_LEFT		CTL_CH('b')	/* cursor key Left	*/
+#define KEY_HOME		CTL_CH('a')	/* Cursor Key Home	*/
+#define KEY_ERASE_TO_EOL	CTL_CH('k')
+#define KEY_REFRESH_TO_EOL	CTL_CH('e')
+#define KEY_ERASE_LINE		CTL_CH('x')
+#define KEY_INSERT		CTL_CH('o')
+#define KEY_CLEAR_SCREEN	CTL_CH('l')
+#define KEY_DEL7		127
+#define KEY_END			133		/* Cursor Key End	*/
+#define KEY_PAGEUP		135		/* Cursor Key Page Up	*/
+#define KEY_PAGEDOWN		136		/* Cursor Key Page Down	*/
+#define KEY_DEL			137		/* Cursor Key Del	*/
+
+#define MAX_CMDBUF_SIZE		256
+
+#define CTL_BACKSPACE		('\b')
+#define DEL			255
+#define DEL7			127
+#define CREAD_HIST_CHAR		('!')
+
+#define HIST_MAX		10
+
+#define putnstr(str,n)	do {			\
+		printf ("%.*s", n, str);	\
+	} while (0)
+
+#define getcmd_putch(ch)	putchar(ch)
+#define getcmd_cbeep()		getcmd_putch('\a')
+#define ANSI_CLEAR_SCREEN	"\e[2J\e[;H"
+
+#define BEGINNING_OF_LINE() {			\
+	while (num) {				\
+		getcmd_putch(CTL_BACKSPACE);	\
+		num--;				\
+	}					\
+}
+
+#define ERASE_TO_EOL() {				\
+	if (num < eol_num) {				\
+		int t;					\
+		for (t = num; t < eol_num; t++)		\
+			getcmd_putch(' ');		\
+		while (t-- > num)			\
+			getcmd_putch(CTL_BACKSPACE);	\
+		eol_num = num;				\
+	}						\
+}
+
+#define REFRESH_TO_EOL() {			\
+	if (num < eol_num) {			\
+		wlen = eol_num - num;		\
+		putnstr(buf + num, (int)wlen);	\
+		num = eol_num;			\
+	}					\
+}
+
+int readline(char *buf, int len);
+void hist_init(void);
+
+#endif /* READLINE_H_ */
diff --git a/litex/soc/software/bios/readline_simple.c b/litex/soc/software/bios/readline_simple.c
new file mode 100644
index 000000000..bcf062138
--- /dev/null
+++ b/litex/soc/software/bios/readline_simple.c
@@ -0,0 +1,59 @@
+// This file is Copyright (c) 2013-2014 Sebastien Bourdeauducq <sb@m-labs.hk>
+// This file is Copyright (c) 2014-2019 Florent Kermarrec <florent@enjoy-digital.fr>
+
+// SPDX-License-Identifier: BSD-Source-Code
+
+#include <stdlib.h>
+#include <stdio.h>
+#include <string.h>
+#include <ctype.h>
+
+#include <console.h>
+#include <uart.h>
+
+#include "readline.h"
+
+int readline(char *s, int size)
+{
+	static char skip = 0;
+	char c[2];
+	int ptr;
+
+	c[1] = 0;
+	ptr = 0;
+	while(1) {
+		c[0] = readchar();
+		if (c[0] == skip)
+			continue;
+		skip = 0;
+		switch(c[0]) {
+			case 0x7f:
+			case 0x08:
+				if(ptr > 0) {
+					ptr--;
+					putsnonl("\x08 \x08");
+				}
+				break;
+			case 0x07:
+				break;
+			case '\r':
+				skip = '\n';
+				s[ptr] = 0x00;
+				putsnonl("\n");
+				return 0;
+			case '\n':
+				skip = '\r';
+				s[ptr] = 0x00;
+				putsnonl("\n");
+				return 0;
+			default:
+				putsnonl(c);
+				s[ptr] = c[0];
+				ptr++;
+				break;
+		}
+	}
+
+	return 0;
+}
+

From 86cab3d3627636d71889be327f4f893207d64226 Mon Sep 17 00:00:00 2001
From: Franck Jullien <franck.jullien@gmail.com>
Date: Tue, 28 Apr 2020 23:15:04 +0200
Subject: [PATCH 52/95] bios: move helper functions to their own file

---
 litex/soc/software/bios/Makefile  |  8 +++-
 litex/soc/software/bios/helpers.c | 76 +++++++++++++++++++++++++++++++
 litex/soc/software/bios/helpers.h |  7 +++
 litex/soc/software/bios/main.c    | 66 +--------------------------
 4 files changed, 91 insertions(+), 66 deletions(-)
 create mode 100644 litex/soc/software/bios/helpers.c
 create mode 100644 litex/soc/software/bios/helpers.h

diff --git a/litex/soc/software/bios/Makefile b/litex/soc/software/bios/Makefile
index 5ede7cd71..d48ab817d 100755
--- a/litex/soc/software/bios/Makefile
+++ b/litex/soc/software/bios/Makefile
@@ -10,7 +10,13 @@ ifdef TFTP_SERVER_PORT
 CFLAGS += -DTFTP_SERVER_PORT=$(TFTP_SERVER_PORT)
 endif
 
-OBJECTS=isr.o sdram.o sdcard.o main.o boot-helper.o boot.o
+OBJECTS = isr.o			\
+	  sdram.o		\
+	  sdcard.o		\
+	  main.o		\
+	  boot-helper.o		\
+	  boot.o		\
+	  helpers.o
 
 ifdef TERM_NO_HIST
 CFLAGS += -DTERM_NO_HIST
diff --git a/litex/soc/software/bios/helpers.c b/litex/soc/software/bios/helpers.c
new file mode 100644
index 000000000..21eb6e1fc
--- /dev/null
+++ b/litex/soc/software/bios/helpers.c
@@ -0,0 +1,76 @@
+// This file is Copyright (c) 2017 Florent Kermarrec <florent@enjoy-digital.fr>
+
+// SPDX-License-Identifier: BSD-Source-Code
+
+#include <stdio.h>
+#include <console.h>
+#include <crc.h>
+#include <string.h>
+
+#include "readline.h"
+#include "helpers.h"
+
+extern unsigned int _ftext, _edata;
+
+#define NUMBER_OF_BYTES_ON_A_LINE 16
+void dump_bytes(unsigned int *ptr, int count, unsigned long addr)
+{
+	char *data = (char *)ptr;
+	int line_bytes = 0, i = 0;
+
+	putsnonl("Memory dump:");
+	while (count > 0) {
+		line_bytes =
+			(count > NUMBER_OF_BYTES_ON_A_LINE)?
+				NUMBER_OF_BYTES_ON_A_LINE : count;
+
+		printf("\n0x%08x  ", addr);
+		for (i = 0; i < line_bytes; i++)
+			printf("%02x ", *(unsigned char *)(data+i));
+
+		for (; i < NUMBER_OF_BYTES_ON_A_LINE; i++)
+			printf("   ");
+
+		printf(" ");
+
+		for (i = 0; i<line_bytes; i++) {
+			if ((*(data+i) < 0x20) || (*(data+i) > 0x7e))
+				printf(".");
+			else
+				printf("%c", *(data+i));
+		}
+
+		for (; i < NUMBER_OF_BYTES_ON_A_LINE; i++)
+			printf(" ");
+
+		data += (char)line_bytes;
+		count -= line_bytes;
+		addr += line_bytes;
+	}
+	printf("\n");
+}
+
+void crcbios(void)
+{
+	unsigned long offset_bios;
+	unsigned long length;
+	unsigned int expected_crc;
+	unsigned int actual_crc;
+
+	/*
+	 * _edata is located right after the end of the flat
+	 * binary image. The CRC tool writes the 32-bit CRC here.
+	 * We also use the address of _edata to know the length
+	 * of our code.
+	 */
+	offset_bios = (unsigned long)&_ftext;
+	expected_crc = _edata;
+	length = (unsigned long)&_edata - offset_bios;
+	actual_crc = crc32((unsigned char *)offset_bios, length);
+	if (expected_crc == actual_crc)
+		printf(" BIOS CRC passed (%08x)\n", actual_crc);
+	else {
+		printf(" BIOS CRC failed (expected %08x, got %08x)\n", expected_crc, actual_crc);
+		printf(" The system will continue, but expect problems.\n");
+	}
+}
diff --git a/litex/soc/software/bios/helpers.h b/litex/soc/software/bios/helpers.h
new file mode 100644
index 000000000..227dcd174
--- /dev/null
+++ b/litex/soc/software/bios/helpers.h
@@ -0,0 +1,7 @@
+#ifndef __HELPERS_H__
+#define __HELPERS_H__
+
+void dump_bytes(unsigned int *ptr, int count, unsigned long addr);
+void crcbios(void);
+
+#endif
diff --git a/litex/soc/software/bios/main.c b/litex/soc/software/bios/main.c
index 368031f6a..7f9187a31 100644
--- a/litex/soc/software/bios/main.c
+++ b/litex/soc/software/bios/main.c
@@ -44,47 +44,10 @@
 #include "sdcard.h"
 #include "boot.h"
 #include "readline.h"
+#include "helpers.h"
 
 /* General address space functions */
 
-#define NUMBER_OF_BYTES_ON_A_LINE 16
-static void dump_bytes(unsigned int *ptr, int count, unsigned long addr)
-{
-	char *data = (char *)ptr;
-	int line_bytes = 0, i = 0;
-
-	putsnonl("Memory dump:");
-	while(count > 0){
-		line_bytes =
-			(count > NUMBER_OF_BYTES_ON_A_LINE)?
-				NUMBER_OF_BYTES_ON_A_LINE : count;
-
-		printf("\n0x%08x  ", addr);
-		for(i=0;i<line_bytes;i++)
-			printf("%02x ", *(unsigned char *)(data+i));
-
-		for(;i<NUMBER_OF_BYTES_ON_A_LINE;i++)
-			printf("   ");
-
-		printf(" ");
-
-		for(i=0;i<line_bytes;i++) {
-			if((*(data+i) < 0x20) || (*(data+i) > 0x7e))
-				printf(".");
-			else
-				printf("%c", *(data+i));
-		}
-
-		for(;i<NUMBER_OF_BYTES_ON_A_LINE;i++)
-			printf(" ");
-
-		data += (char)line_bytes;
-		count -= line_bytes;
-		addr += line_bytes;
-	}
-	printf("\n");
-}
-
 static void mr(char *startaddr, char *len)
 {
 	char *c;
@@ -523,33 +486,6 @@ static void do_command(char *c)
 		printf("Command not found\n");
 }
 
-extern unsigned int _ftext, _edata;
-
-static void crcbios(void)
-{
-	unsigned long offset_bios;
-	unsigned long length;
-	unsigned int expected_crc;
-	unsigned int actual_crc;
-
-	/*
-	 * _edata is located right after the end of the flat
-	 * binary image. The CRC tool writes the 32-bit CRC here.
-	 * We also use the address of _edata to know the length
-	 * of our code.
-	 */
-	offset_bios = (unsigned long)&_ftext;
-	expected_crc = _edata;
-	length = (unsigned long)&_edata - offset_bios;
-	actual_crc = crc32((unsigned char *)offset_bios, length);
-	if(expected_crc == actual_crc)
-		printf(" BIOS CRC passed (%08x)\n", actual_crc);
-	else {
-		printf(" BIOS CRC failed (expected %08x, got %08x)\n", expected_crc, actual_crc);
-		printf(" The system will continue, but expect problems.\n");
-	}
-}
-
 static void boot_sequence(void)
 {
 	if(serialboot()) {

From fc2b8226c544977626795705e06e1e768e5dd847 Mon Sep 17 00:00:00 2001
From: Franck Jullien <franck.jullien@gmail.com>
Date: Wed, 29 Apr 2020 21:33:51 +0200
Subject: [PATCH 53/95] bios: switch command handler to a modular format

Command are now described with a structure. A pointer to this
structure is placed in a dedicated linker section.
---
 litex/soc/software/bios/Makefile              |  13 +-
 litex/soc/software/bios/command.h             |  47 ++
 litex/soc/software/bios/commands/cmd_bios.c   | 125 +++++
 litex/soc/software/bios/commands/cmd_boot.c   |  59 +++
 litex/soc/software/bios/commands/cmd_dram.c   | 222 +++++++++
 litex/soc/software/bios/commands/cmd_mdio.c   | 132 +++++
 .../software/bios/commands/cmd_mem_access.c   | 137 ++++++
 litex/soc/software/bios/commands/cmd_sdcard.c |  85 ++++
 .../software/bios/commands/cmd_spi_flash.c    |  75 +++
 .../soc/software/bios/commands/cmd_usddrphy.c | 128 +++++
 litex/soc/software/bios/helpers.c             |  52 ++
 litex/soc/software/bios/helpers.h             |   2 +
 litex/soc/software/bios/linker.ld             |   7 +
 litex/soc/software/bios/main.c                | 451 +-----------------
 litex/soc/software/bios/sdram.c               |  71 +--
 litex/soc/software/bios/sdram.h               |   8 +-
 16 files changed, 1104 insertions(+), 510 deletions(-)
 create mode 100644 litex/soc/software/bios/command.h
 create mode 100644 litex/soc/software/bios/commands/cmd_bios.c
 create mode 100644 litex/soc/software/bios/commands/cmd_boot.c
 create mode 100644 litex/soc/software/bios/commands/cmd_dram.c
 create mode 100644 litex/soc/software/bios/commands/cmd_mdio.c
 create mode 100644 litex/soc/software/bios/commands/cmd_mem_access.c
 create mode 100644 litex/soc/software/bios/commands/cmd_sdcard.c
 create mode 100644 litex/soc/software/bios/commands/cmd_spi_flash.c
 create mode 100644 litex/soc/software/bios/commands/cmd_usddrphy.c

diff --git a/litex/soc/software/bios/Makefile b/litex/soc/software/bios/Makefile
index d48ab817d..c80e0a130 100755
--- a/litex/soc/software/bios/Makefile
+++ b/litex/soc/software/bios/Makefile
@@ -16,7 +16,15 @@ OBJECTS = isr.o			\
 	  main.o		\
 	  boot-helper.o		\
 	  boot.o		\
-	  helpers.o
+	  helpers.o		\
+	  cmd_bios.o		\
+	  cmd_boot.o		\
+	  cmd_dram.o		\
+	  cmd_mdio.o		\
+	  cmd_mem_access.o	\
+	  cmd_sdcard.o		\
+	  cmd_spi_flash.o	\
+	  cmd_usddrphy.o
 
 ifdef TERM_NO_HIST
 CFLAGS += -DTERM_NO_HIST
@@ -67,6 +75,9 @@ endif
 %.o: $(BIOS_DIRECTORY)/%.c
 	$(compile)
 
+%.o: $(BIOS_DIRECTORY)/commands/%.c
+	$(compile)
+
 %.o: $(BIOS_DIRECTORY)/%.S
 	$(assemble)
 
diff --git a/litex/soc/software/bios/command.h b/litex/soc/software/bios/command.h
new file mode 100644
index 000000000..247043895
--- /dev/null
+++ b/litex/soc/software/bios/command.h
@@ -0,0 +1,47 @@
+// This file is Copyright (c) 2020 Franck Jullien <franck.jullien@gmail.com>
+
+// SPDX-License-Identifier: BSD-Source-Code
+
+#ifndef __COMMAND_H__
+#define __COMMAND_H__
+
+#define MAX_PARAM	8
+
+#define MISC_CMDS	0
+#define SYSTEM_CMDS	1
+#define CACHE_CMDS	2
+#define BOOT_CMDS	3
+#define DRAM_CMDS	4
+#define MDIO_CMDS	5
+#define MEM_CMDS	6
+#define SD_CMDS		7
+#define SPIFLASH_CMDS	8
+#define DDR_CMDS	9
+#define NB_OF_GROUPS	10
+
+typedef void (*cmd_handler)(int nb_params, char **params);
+
+struct command_struct {
+	void (*func)(int nb_params, char **params);
+	const char *name;
+	const char *help;
+	int group;
+};
+
+extern struct command_struct *const __bios_cmd_start[];
+extern struct command_struct *const __bios_cmd_end[];
+
+#define define_command(cmd_name, handler, help_txt, group_id) \
+	struct command_struct s_##cmd_name = {					     \
+		.func = (cmd_handler)handler,					     \
+		.name = #cmd_name,						     \
+		.help = help_txt,						     \
+		.group = group_id,						     \
+	};									     \
+	const struct command_struct *__bios_cmd_##cmd_name __attribute__((__used__)) \
+	__attribute__((__section__(".bios_cmd"))) = &s_##cmd_name
+
+
+struct command_struct *command_dispatcher(char *command, int nb_params, char **params);
+
+#endif
diff --git a/litex/soc/software/bios/commands/cmd_bios.c b/litex/soc/software/bios/commands/cmd_bios.c
new file mode 100644
index 000000000..a5e704248
--- /dev/null
+++ b/litex/soc/software/bios/commands/cmd_bios.c
@@ -0,0 +1,125 @@
+// SPDX-License-Identifier: BSD-Source-Code
+
+#include <stdio.h>
+#include <stdlib.h>
+
+#include <id.h>
+#include <generated/csr.h>
+#include <crc.h>
+#include <system.h>
+
+#include "../command.h"
+#include "../helpers.h"
+
+/**
+ * Command "help"
+ *
+ * Print a list of available commands with their help text
+ *
+ */
+static void help_handler(int nb_params, char **params)
+{
+	struct command_struct * const *cmd;
+	int i, not_empty;
+
+	puts("\nLiteX BIOS, available commands:\n");
+
+	for (i = 0; i < NB_OF_GROUPS; i++) {
+		not_empty = 0;
+		for (cmd = __bios_cmd_start; cmd != __bios_cmd_end; cmd++) {
+			if ((*cmd)->group == i) {
+				printf("%-16s - %s\n", (*cmd)->name, (*cmd)->help ? (*cmd)->help : "-");
+				not_empty = 1;
+			}
+		}
+		if (not_empty)
+			printf("\n");
+	}
+}
+
+define_command(help, help_handler, "Print this help", MISC_CMDS);
+
+/**
+ * Command "ident"
+ *
+ * Print SoC identyifier if available
+ *
+ */
+static void ident_helper(int nb_params, char **params)
+{
+	char buffer[IDENT_SIZE];
+
+	get_ident(buffer);
+	printf("Ident: %s", *buffer ? buffer : "-");
+}
+
+define_command(ident, ident_helper, "Display identifier", SYSTEM_CMDS);
+
+/**
+ * Command "reboot"
+ *
+ * Reboot the system
+ *
+ */
+#ifdef CSR_CTRL_BASE
+static void reboot(int nb_params, char **params)
+{
+	ctrl_reset_write(1);
+}
+
+define_command(reboot, reboot, "Reset processor", SYSTEM_CMDS);
+#endif
+
+/**
+ * Command "crc"
+ *
+ * Compute CRC32 over an address range
+ *
+ */
+static void crc(int nb_params, char **params)
+{
+	char *c;
+	unsigned int addr;
+	unsigned int length;
+
+	if (nb_params < 2) {
+		printf("crc <address> <length>");
+		return;
+	}
+
+	addr = strtoul(params[0], &c, 0);
+	if (*c != 0) {
+		printf("Incorrect address");
+		return;
+	}
+
+	length = strtoul(params[1], &c, 0);
+	if (*c != 0) {
+		printf("Incorrect length");
+		return;
+	}
+
+	printf("CRC32: %08x", crc32((unsigned char *)addr, length));
+}
+
+define_command(crc, crc, "Compute CRC32 of a part of the address space", MISC_CMDS);
+
+/**
+ * Command "flush_cpu_dcache"
+ *
+ * Flush CPU data cache
+ *
+ */
+
+define_command(flush_cpu_dcache, flush_cpu_dcache, "Flush CPU data cache", CACHE_CMDS);
+
+/**
+ * Command "flush_l2_cache"
+ *
+ * Flush L2 cache
+ *
+ */
+#ifdef CONFIG_L2_SIZE
+define_command(flush_l2_cache, flush_l2_cache, "Flush L2 cache", CACHE_CMDS);
+#endif
+
diff --git a/litex/soc/software/bios/commands/cmd_boot.c b/litex/soc/software/bios/commands/cmd_boot.c
new file mode 100644
index 000000000..c9cb8a11d
--- /dev/null
+++ b/litex/soc/software/bios/commands/cmd_boot.c
@@ -0,0 +1,59 @@
+// SPDX-License-Identifier: BSD-Source-Code
+
+#include <stdio.h>
+#include <stdlib.h>
+
+#include <generated/csr.h>
+
+#include "../command.h"
+#include "../helpers.h"
+#include "../boot.h"
+
+/**
+ * Command "flashboot"
+ *
+ * Boot software from flash
+ *
+ */
+#ifdef FLASH_BOOT_ADDRESS
+define_command(flashboot, flashboot, "Boot from flash", BOOT_CMDS);
+#endif
+
+/**
+ * Command "romboot"
+ *
+ * Boot software from embedded rom
+ *
+ */
+#ifdef ROM_BOOT_ADDRESS
+define_command(romboot, romboot, "Boot from embedded rom", BOOT_CMDS);
+#endif
+
+/**
+ * Command "serialboot"
+ *
+ * Boot software from serial interface
+ *
+ */
+define_command(serialboot, serialboot, "Boot via SFL", BOOT_CMDS);
+
+/**
+ * Command "netboot"
+ *
+ * Boot software from TFTP server
+ *
+ */
+#ifdef CSR_ETHMAC_BASE
+define_command(netboot, netboot, "Boot via TFTP", BOOT_CMDS);
+#endif
+
+/**
+ * Command "spisdcardboot"
+ *
+ * Boot software from SDcard
+ *
+ */
+#ifdef CSR_SPISDCARD_BASE
+define_command(spisdcardboot, spisdcardboot, "Boot from SDCard via SPI hardware bitbang", BOOT_CMDS);
+#endif
+
diff --git a/litex/soc/software/bios/commands/cmd_dram.c b/litex/soc/software/bios/commands/cmd_dram.c
new file mode 100644
index 000000000..0d6fa1d46
--- /dev/null
+++ b/litex/soc/software/bios/commands/cmd_dram.c
@@ -0,0 +1,222 @@
+// SPDX-License-Identifier: BSD-Source-Code
+
+#include <stdio.h>
+#include <stdlib.h>
+
+#include <generated/csr.h>
+
+#include "../command.h"
+#include "../helpers.h"
+#include "../sdram.h"
+
+/**
+ * Command "sdrrow"
+ *
+ * Precharge/Activate row
+ *
+ */
+#ifdef CSR_SDRAM_BASE
+static void sdrrow_handler(int nb_params, char **params)
+{
+	char *c;
+	unsigned int row;
+
+	if (nb_params < 1) {
+		sdrrow(0);
+		printf("Precharged");
+	}
+	
+	row = strtoul(params[0], &c, 0);
+	if (*c != 0) {
+		printf("Incorrect row");
+		return;
+	}
+
+	sdrrow(row);
+	printf("Activated row %d", row);
+}
+define_command(sdrrow, sdrrow_handler, "Precharge/Activate row", DRAM_CMDS);
+#endif
+
+/**
+ * Command "sdrsw"
+ *
+ * Gives SDRAM control to SW
+ *
+ */
+#ifdef CSR_SDRAM_BASE
+define_command(sdrsw, sdrsw, "Gives SDRAM control to SW", DRAM_CMDS);
+#endif
+
+/**
+ * Command "sdrhw"
+ *
+ * Gives SDRAM control to HW
+ *
+ */
+#ifdef CSR_SDRAM_BASE
+define_command(sdrhw, sdrhw, "Gives SDRAM control to HW", DRAM_CMDS);
+#endif
+
+/**
+ * Command "sdrrdbuf"
+ *
+ * Dump SDRAM read buffer
+ *
+ */
+#ifdef CSR_SDRAM_BASE
+static void sdrrdbuf_handler(int nb_params, char **params)
+{
+	sdrrdbuf(-1);
+}
+
+define_command(sdrrdbuf, sdrrdbuf_handler, "Dump SDRAM read buffer", DRAM_CMDS);
+#endif
+
+/**
+ * Command "sdrrd"
+ *
+ * Read SDRAM data
+ *
+ */
+#ifdef CSR_SDRAM_BASE
+static void sdrrd_handler(int nb_params, char **params)
+{
+	unsigned int addr;
+	int dq;
+	char *c;
+
+	if (nb_params < 1) {
+		printf("sdrrd <address>");
+		return;
+	}
+
+	addr = strtoul(params[0], &c, 0);
+	if (*c != 0) {
+		printf("Incorrect address");
+		return;
+	}
+
+	if (nb_params < 2)
+		dq = -1;
+	else {
+		dq = strtoul(params[1], &c, 0);
+		if (*c != 0) {
+			printf("Incorrect DQ");
+			return;
+		}
+	}
+
+	sdrrd(addr, dq);
+}
+
+define_command(sdrrd, sdrrd_handler, "Read SDRAM data", DRAM_CMDS);
+#endif
+
+/**
+ * Command "sdrrderr"
+ *
+ * Print SDRAM read errors
+ *
+ */
+#ifdef CSR_SDRAM_BASE
+static void sdrrderr_handler(int nb_params, char **params)
+{
+	int count;
+	char *c;
+
+	if (nb_params < 1) {
+		printf("sdrrderr <count>");
+		return;
+	}
+
+	count = strtoul(params[0], &c, 0);
+	if (*c != 0) {
+		printf("Incorrect count");
+		return;
+	}
+
+	sdrrderr(count);
+}
+
+define_command(sdrrderr, sdrrderr_handler, "Print SDRAM read errors", DRAM_CMDS);
+#endif
+
+/**
+ * Command "sdrwr"
+ *
+ * Write SDRAM test data
+ *
+ */
+#ifdef CSR_SDRAM_BASE
+static void sdrwr_handler(int nb_params, char **params)
+{
+	unsigned int addr;
+	char *c;
+
+	if (nb_params < 1) {
+		printf("sdrwr <address>");
+		return;
+	}
+
+	addr = strtoul(params[0], &c, 0);
+	if (*c != 0) {
+		printf("Incorrect address");
+		return;
+	}
+
+	sdrwr(addr);
+}
+
+define_command(sdrwr, sdrwr_handler, "Write SDRAM test data", DRAM_CMDS);
+#endif
+
+/**
+ * Command "sdrinit"
+ *
+ * Start SDRAM initialisation
+ *
+ */
+#if defined(CSR_SDRAM_BASE) && defined(CSR_DDRPHY_BASE)
+define_command(sdrinit, sdrinit, "Start SDRAM initialisation", DRAM_CMDS);
+#endif
+
+/**
+ * Command "sdrwlon"
+ *
+ * Write leveling ON
+ *
+ */
+#if defined(CSR_DDRPHY_BASE) && defined(SDRAM_PHY_WRITE_LEVELING_CAPABLE) && defined(CSR_SDRAM_BASE)
+define_command(sdrwlon, sdrwlon, "Enable write leveling", DRAM_CMDS);
+#endif
+
+/**
+ * Command "sdrwloff"
+ *
+ * Write leveling OFF
+ *
+ */
+#if defined(CSR_DDRPHY_BASE) && defined(SDRAM_PHY_WRITE_LEVELING_CAPABLE) && defined(CSR_SDRAM_BASE)
+define_command(sdrwloff, sdrwloff, "Disable write leveling", DRAM_CMDS);
+#endif
+
+/**
+ * Command "sdrlevel"
+ *
+ * Perform read/write leveling
+ *
+ */
+#if defined(CSR_DDRPHY_BASE) && defined(CSR_SDRAM_BASE)
+define_command(sdrlevel, sdrlevel, "Perform read/write leveling", DRAM_CMDS);
+#endif
+
+/**
+ * Command "memtest"
+ *
+ * Run a memory test
+ *
+ */
+#ifdef CSR_SDRAM_BASE
+define_command(memtest, memtest, "Run a memory test", DRAM_CMDS);
+#endif
diff --git a/litex/soc/software/bios/commands/cmd_mdio.c b/litex/soc/software/bios/commands/cmd_mdio.c
new file mode 100644
index 000000000..9d28c5347
--- /dev/null
+++ b/litex/soc/software/bios/commands/cmd_mdio.c
@@ -0,0 +1,132 @@
+// SPDX-License-Identifier: BSD-Source-Code
+
+#include <stdio.h>
+#include <stdlib.h>
+
+#include <generated/csr.h>
+
+#include "../command.h"
+#include "../helpers.h"
+
+/**
+ * Command "mdiow"
+ *
+ * Write MDIO register
+ *
+ */
+#ifdef CSR_ETHPHY_MDIO_W_ADDR
+static void mdiow(int nb_params, char **params)
+{
+	char *c;
+	unsigned int phyadr2;
+	unsigned int reg2;
+	unsigned int val2;
+
+	if (nb_params < 3) {
+		printf("mdiow <phyadr> <reg> <value>");
+		return;
+	}
+
+	phyadr2 = strtoul(params[0], &c, 0);
+	if (*c != 0) {
+		printf("Incorrect phyadr");
+		return;
+	}
+
+	reg2 = strtoul(params[1], &c, 0);
+	if (*c != 0) {
+		printf("Incorrect reg");
+		return;
+	}
+
+	val2 = strtoul(params[2], &c, 0);
+	if (*c != 0) {
+		printf("Incorrect val");
+		return;
+	}
+
+	mdio_write(phyadr2, reg2, val2);
+}
+
+define_command(mdiow, mdiow, "Write MDIO register", MDIO_CMDS);
+#endif
+
+/**
+ * Command "mdior"
+ *
+ * Read MDIO register
+ *
+ */
+#ifdef CSR_ETHPHY_MDIO_W_ADDR
+static void mdior(int nb_params, char **params)
+{
+	char *c;
+	unsigned int phyadr2;
+	unsigned int reg2;
+	unsigned int val;
+
+	if (nb_params < 2) {
+		printf("mdior <phyadr> <reg>");
+		return;
+	}
+
+	phyadr2 = strtoul(params[0], &c, 0);
+	if (*c != 0) {
+		printf("Incorrect phyadr");
+		return;
+	}
+
+	reg2 = strtoul(params[1], &c, 0);
+	if (*c != 0) {
+		printf("Incorrect reg");
+		return;
+	}
+
+	val = mdio_read(phyadr2, reg2);
+	printf("Reg %d: 0x%04x", reg2, val);
+}
+
+define_command(mdior, mdior, "Read MDIO register", MDIO_CMDS);
+#endif
+
+/**
+ * Command "mdiod"
+ *
+ * Dump MDIO registers
+ *
+ */
+#ifdef CSR_ETHPHY_MDIO_W_ADDR
+static void mdiod(int nb_params, char **params)
+{
+	char *c;
+	unsigned int phyadr;
+	unsigned int count;
+	unsigned int val;
+	int i;
+
+	if (nb_params < 2) {
+		printf("mdiod <phyadr> <count>");
+		return;
+	}
+
+	phyadr = strtoul(params[0], &c, 0);
+	if (*c != 0) {
+		printf("Incorrect phyadr");
+		return;
+	}
+
+	count = strtoul(params[1], &c, 0);
+	if (*c != 0) {
+		printf("Incorrect count");
+		return;
+	}
+
+	printf("MDIO dump @0x%x:\n", phyadr);
+	for (i = 0; i < count; i++) {
+		val = mdio_read(phyadr, i);
+		printf("reg %d: 0x%04x", i, val);
+	}
+}
+
+define_command(mdiod, mdiod, "Dump MDIO registers", MDIO_CMDS);
+#endif
diff --git a/litex/soc/software/bios/commands/cmd_mem_access.c b/litex/soc/software/bios/commands/cmd_mem_access.c
new file mode 100644
index 000000000..8c63d4c44
--- /dev/null
+++ b/litex/soc/software/bios/commands/cmd_mem_access.c
@@ -0,0 +1,137 @@
+// SPDX-License-Identifier: BSD-Source-Code
+
+#include <stdio.h>
+#include <stdlib.h>
+
+#include "../command.h"
+#include "../helpers.h"
+
+/**
+ * Command "mr"
+ *
+ * Memory read
+ *
+ */
+static void mr(int nb_params, char **params)
+{
+	char *c;
+	unsigned int *addr;
+	unsigned int length;
+
+	if (nb_params < 1) {
+		printf("mr <address> [length]");
+		return;
+	}
+	addr = (unsigned int *)strtoul(params[0], &c, 0);
+	if (*c != 0) {
+		printf("Incorrect address");
+		return;
+	}
+	if (nb_params == 1) {
+		length = 4;
+	} else {
+		length = strtoul(params[1], &c, 0);
+		if(*c != 0) {
+			printf("\nIncorrect length");
+			return;
+		}
+	}
+
+	dump_bytes(addr, length, (unsigned long)addr);
+}
+
+define_command(mr, mr, "Read address space", MEM_CMDS);
+
+/**
+ * Command "mw"
+ *
+ * Memory write
+ *
+ */
+static void mw(int nb_params, char **params)
+{
+	char *c;
+	unsigned int *addr;
+	unsigned int value;
+	unsigned int count;
+	unsigned int i;
+
+	if (nb_params < 2) {
+		printf("mw <address> <value> [count]");
+		return;
+	}
+
+	addr = (unsigned int *)strtoul(params[0], &c, 0);
+	if (*c != 0) {
+		printf("Incorrect address");
+		return;
+	}
+
+	value = strtoul(params[1], &c, 0);
+	if(*c != 0) {
+		printf("Incorrect value");
+		return;
+	}
+
+	if (nb_params == 2) {
+		count = 1;
+	} else {
+		count = strtoul(params[2], &c, 0);
+		if(*c != 0) {
+			printf("Incorrect count");
+			return;
+		}
+	}
+
+	for (i = 0; i < count; i++)
+		*addr++ = value;
+}
+
+define_command(mw, mw, "Write address space", MEM_CMDS);
+
+/**
+ * Command "mc"
+ *
+ * Memory copy
+ *
+ */
+static void mc(int nb_params, char **params)
+{
+	char *c;
+	unsigned int *dstaddr;
+	unsigned int *srcaddr;
+	unsigned int count;
+	unsigned int i;
+
+	if (nb_params < 2) {
+		printf("mc <dst> <src> [count]");
+		return;
+	}
+
+	dstaddr = (unsigned int *)strtoul(params[0], &c, 0);
+	if (*c != 0) {
+		printf("Incorrect destination address");
+		return;
+	}
+
+	srcaddr = (unsigned int *)strtoul(params[1], &c, 0);
+	if (*c != 0) {
+		printf("Incorrect source address");
+		return;
+	}
+
+	if (nb_params == 2) {
+		count = 1;
+	} else {
+		count = strtoul(params[2], &c, 0);
+		if (*c != 0) {
+			printf("Incorrect count");
+			return;
+		}
+	}
+
+	for (i = 0; i < count; i++)
+		*dstaddr++ = *srcaddr++;
+}
+
+define_command(mc, mc, "Copy address space", MEM_CMDS);
diff --git a/litex/soc/software/bios/commands/cmd_sdcard.c b/litex/soc/software/bios/commands/cmd_sdcard.c
new file mode 100644
index 000000000..96f9fe64c
--- /dev/null
+++ b/litex/soc/software/bios/commands/cmd_sdcard.c
@@ -0,0 +1,85 @@
+// SPDX-License-Identifier: BSD-Source-Code
+
+#include <stdio.h>
+#include <stdlib.h>
+
+#include <generated/csr.h>
+
+#include "../command.h"
+#include "../helpers.h"
+#include "../sdcard.h"
+
+/**
+ * Command "sdclk"
+ *
+ * Configure SDcard clock frequency
+ *
+ */
+#ifdef CSR_SDCORE_BASE
+static void sdclk(int nb_params, char **params)
+{
+	unsigned int frequ;
+	char *c;
+
+	if (nb_params < 1) {
+		printf("sdclk <frequ>");
+		return;
+	}
+
+	frequ = strtoul(params[0], &c, 0);
+	if (*c != 0) {
+		printf("Incorrect frequency");
+		return;
+	}
+
+	sdclk_set_clk(frequ);
+}
+
+struct command_struct cmd_sdclk =
+{
+	.func = sdclk,
+	.name = "sdclk",
+	.help = "SDCard set clk frequency (Mhz)",
+};
+
+define_command(sdclk, sdclk, "SDCard set clk frequency (Mhz)", SD_CMDS);
+#endif
+
+/**
+ * Command "sdinit"
+ *
+ * Initialize SDcard
+ *
+ */
+#ifdef CSR_SDCORE_BASE
+define_command(sdinit, sdinit, "SDCard initialization", SD_CMDS);
+#endif
+
+/**
+ * Command "sdtest"
+ *
+ * Perform SDcard access tests
+ *
+ */
+#ifdef CSR_SDCORE_BASE
+static void sdtest(int nb_params, char **params)
+{
+	unsigned int loops;
+	char *c;
+
+	if (nb_params < 1) {
+		printf("sdtest <loops>");
+		return;
+	}
+
+	loops = strtoul(params[0], &c, 0);
+	if (*c != 0) {
+		printf("Incorrect number of loops");
+		return;
+	}
+
+	sdcard_test(loops);
+}
+
+define_command(sdtest, sdtest, "SDCard test", SD_CMDS);
+#endif
diff --git a/litex/soc/software/bios/commands/cmd_spi_flash.c b/litex/soc/software/bios/commands/cmd_spi_flash.c
new file mode 100644
index 000000000..e607a89df
--- /dev/null
+++ b/litex/soc/software/bios/commands/cmd_spi_flash.c
@@ -0,0 +1,75 @@
+// SPDX-License-Identifier: BSD-Source-Code
+
+#include <stdio.h>
+#include <stdlib.h>
+
+#include <generated/csr.h>
+
+#include "../command.h"
+#include "../helpers.h"
+
+/**
+ * Command "fw"
+ *
+ * Write data from a memory buffer to SPI flash
+ *
+ */
+#if (defined CSR_SPIFLASH_BASE && defined SPIFLASH_PAGE_SIZE)
+static void fw(int nb_params, char **params)
+{
+	char *c;
+	unsigned int addr;
+	unsigned int value;
+	unsigned int count;
+	unsigned int i;
+
+	if (nb_params < 2) {
+		printf("fw <offset> <value> [count]");
+		return;
+	}
+
+	addr = strtoul(params[0], &c, 0);
+	if (*c != 0) {
+		printf("Incorrect offset");
+		return;
+	}
+
+	value = strtoul(params[1], &c, 0);
+	if (*c != 0) {
+		printf("Incorrect value");
+		return;
+	}
+
+	if (nb_params == 2) {
+		count = 1;
+	} else {
+		count = strtoul(count, &c, 0);
+		if (*c != 0) {
+			printf("Incorrect count");
+			return;
+		}
+	}
+
+	for (i = 0; i < count; i++)
+		write_to_flash(addr + i * 4, (unsigned char *)&value, 4);
+}
+
+define_command(fw, fw, "Write to flash", SPIFLASH_CMDS);
+#endif
+
+/**
+ * Command "fe"
+ *
+ * Flash erase
+ *
+ */
+#if (defined CSR_SPIFLASH_BASE && defined SPIFLASH_PAGE_SIZE)
+static void fe(int nb_params, char **params)
+{
+	erase_flash();
+	printf("Flash erased\n");
+}
+
+define_command(fe, fe, "Erase whole flash", SPIFLASH_CMDS);
+#endif
+
diff --git a/litex/soc/software/bios/commands/cmd_usddrphy.c b/litex/soc/software/bios/commands/cmd_usddrphy.c
new file mode 100644
index 000000000..69c62fad0
--- /dev/null
+++ b/litex/soc/software/bios/commands/cmd_usddrphy.c
@@ -0,0 +1,128 @@
+// SPDX-License-Identifier: BSD-Source-Code
+
+#include <stdio.h>
+#include <stdlib.h>
+
+#include <generated/csr.h>
+
+#include "../command.h"
+#include "../helpers.h"
+#include "../sdram.h"
+
+/**
+ * Command "sdram_cdly"
+ *
+ * Set SDRAM clk/cmd delay
+ *
+ */
+#ifdef USDDRPHY_DEBUG
+static void sdram_cdly(int nb_params, char **params)
+{
+	unsigned int delay;
+	char *c;
+
+	if (nb_params < 1) {
+		printf("sdram_cdly <delay>");
+		return;
+	}
+
+	delay = strtoul(params[0], &c, 0);
+	if (*c != 0) {
+		printf("Incorrect delay");
+		return;
+	}
+
+	ddrphy_cdly(delay);
+}
+
+define_command(sdram_cdly, sdram_cdly, "Set SDRAM clk/cmd delay", DDR_CMDS);
+#endif
+
+/**
+ * Command "sdram_cdly"
+ *
+ * Run SDRAM calibration
+ *
+ */
+#ifdef USDDRPHY_DEBUG
+define_command(sdram_cal, sdram_cal, "Run SDRAM calibration", DDR_CMDS);
+#endif
+
+/**
+ * Command "sdram_mpr"
+ *
+ * Read SDRAM MPR
+ *
+ */
+#ifdef USDDRPHY_DEBUG
+define_command(sdram_mpr, sdram_mpr, "Read SDRAM MPR", DDR_CMDS);
+#endif
+
+
+/**
+ * Command "sdram_mrwr"
+ *
+ * Write SDRAM mode registers
+ *
+ */
+#ifdef USDDRPHY_DEBUG
+static void sdram_mrwr(int nb_params, char **params)
+{
+	unsigned int reg;
+	unsigned int value;
+	char *c;
+
+	if (nb_params < 2) {
+		printf("sdram_mrwr <reg> <value>");
+		return;
+	}
+
+	reg = strtoul(params[0], &c, 0);
+	if (*c != 0) {
+		printf("Incorrect register value");
+		return;
+	}
+
+	value = strtoul(params[1], &c, 0);
+	if (*c != 0) {
+		printf("Incorrect value");
+		return;
+	}
+
+	sdrsw();
+	printf("Writing 0x%04x to SDRAM mode register %d\n", value, reg);
+	sdrmrwr(reg, value);
+	sdrhw();
+}
+
+define_command(sdram_mrwr, sdram_mrwr, "Write SDRAM mode registers", DDR_CMDS);
+#endif
+
+/**
+ * Command "sdram_cdly_scan"
+ *
+ * Enable/disable cdly scan
+ *
+ */
+#ifdef USDDRPHY_DEBUG
+static void sdram_cdly_scan(int nb_params, char **params)
+{
+	unsigned int value;
+	char *c;
+
+	if (nb_params < 1) {
+		printf("sdram_cdly_scan <value>");
+		return;
+	}
+
+	value = strtoul(params[0], &c, 0);
+	if (*c != 0) {
+		printf("Incorrect value");
+		return;
+	}
+
+	sdr_cdly_scan(value);
+}
+
+define_command(sdram_cdly_scan, sdram_cdly_scan, "Enable/disable cdly scan", DDR_CMDS);
+#endif
diff --git a/litex/soc/software/bios/helpers.c b/litex/soc/software/bios/helpers.c
index 21eb6e1fc..535dd61b2 100644
--- a/litex/soc/software/bios/helpers.c
+++ b/litex/soc/software/bios/helpers.c
@@ -9,6 +9,7 @@
 
 #include "readline.h"
 #include "helpers.h"
+#include "command.h"
 
 extern unsigned int _ftext, _edata;
 
@@ -74,3 +75,54 @@ void crcbios(void)
 		printf(" The system will continue, but expect problems.\n");
 	}
 }
+
+int get_param(char *buf, char **cmd, char **params)
+{
+	int nb_param = 0;
+	int i;
+
+	for (i = 0; i < MAX_PARAM; i++)
+		params[i] = NULL;
+
+	*cmd = buf;
+
+	while ((*buf != ' ') && (*buf !=0))
+		buf++;
+
+	if (*buf == 0)
+		return nb_param;
+
+	*buf++ = 0;
+
+	while (1) {
+		while ((*buf == ' ') && (*buf !=0))
+			buf++;
+
+
+		if (*buf == 0)
+			return nb_param;
+
+		params[nb_param++] = buf;
+
+		while ((*buf != ' ') && (*buf !=0))
+			buf++;
+
+		if (*buf == 0)
+			return nb_param;
+		*buf++ = 0;
+	}
+}
+
+struct command_struct *command_dispatcher(char *command, int nb_params, char **params)
+{
+	struct command_struct * const *cmd;
+
+	for (cmd = __bios_cmd_start; cmd != __bios_cmd_end; cmd++) {
+		if (!strcmp(command, (*cmd)->name)) {
+			(*cmd)->func(nb_params, params);
+			return (*cmd);
+		}
+	}
+
+	return NULL;
+}
diff --git a/litex/soc/software/bios/helpers.h b/litex/soc/software/bios/helpers.h
index 227dcd174..6f1f2deeb 100644
--- a/litex/soc/software/bios/helpers.h
+++ b/litex/soc/software/bios/helpers.h
@@ -3,5 +3,7 @@
 
 void dump_bytes(unsigned int *ptr, int count, unsigned long addr);
 void crcbios(void);
+int get_param(char *buf, char **cmd, char **params);
+struct command_struct *command_dispatcher(char *command, int nb_params, char **params);
 
 #endif
diff --git a/litex/soc/software/bios/linker.ld b/litex/soc/software/bios/linker.ld
index 7760e551d..e0211a6b4 100644
--- a/litex/soc/software/bios/linker.ld
+++ b/litex/soc/software/bios/linker.ld
@@ -26,6 +26,13 @@ SECTIONS
 		_erodata = .;
 	} > rom
 
+	.commands :
+	{
+		PROVIDE_HIDDEN (__bios_cmd_start = .);
+		KEEP(*(.bios_cmd))
+		PROVIDE_HIDDEN (__bios_cmd_end = .);
+	} > rom
+
 	.data :
 	{
 		. = ALIGN(8);
diff --git a/litex/soc/software/bios/main.c b/litex/soc/software/bios/main.c
index 7f9187a31..e985dd5a3 100644
--- a/litex/soc/software/bios/main.c
+++ b/litex/soc/software/bios/main.c
@@ -45,446 +45,7 @@
 #include "boot.h"
 #include "readline.h"
 #include "helpers.h"
-
-/* General address space functions */
-
-static void mr(char *startaddr, char *len)
-{
-	char *c;
-	unsigned int *addr;
-	unsigned int length;
-
-	if(*startaddr == 0) {
-		printf("mr <address> [length]\n");
-		return;
-	}
-	addr = (unsigned *)strtoul(startaddr, &c, 0);
-	if(*c != 0) {
-		printf("incorrect address\n");
-		return;
-	}
-	if(*len == 0) {
-		length = 4;
-	} else {
-		length = strtoul(len, &c, 0);
-		if(*c != 0) {
-			printf("incorrect length\n");
-			return;
-		}
-	}
-
-	dump_bytes(addr, length, (unsigned long)addr);
-}
-
-static void mw(char *addr, char *value, char *count)
-{
-	char *c;
-	unsigned int *addr2;
-	unsigned int value2;
-	unsigned int count2;
-	unsigned int i;
-
-	if((*addr == 0) || (*value == 0)) {
-		printf("mw <address> <value> [count]\n");
-		return;
-	}
-	addr2 = (unsigned int *)strtoul(addr, &c, 0);
-	if(*c != 0) {
-		printf("incorrect address\n");
-		return;
-	}
-	value2 = strtoul(value, &c, 0);
-	if(*c != 0) {
-		printf("incorrect value\n");
-		return;
-	}
-	if(*count == 0) {
-		count2 = 1;
-	} else {
-		count2 = strtoul(count, &c, 0);
-		if(*c != 0) {
-			printf("incorrect count\n");
-			return;
-		}
-	}
-	for (i=0;i<count2;i++) *addr2++ = value2;
-}
-
-static void mc(char *dstaddr, char *srcaddr, char *count)
-{
-	char *c;
-	unsigned int *dstaddr2;
-	unsigned int *srcaddr2;
-	unsigned int count2;
-	unsigned int i;
-
-	if((*dstaddr == 0) || (*srcaddr == 0)) {
-		printf("mc <dst> <src> [count]\n");
-		return;
-	}
-	dstaddr2 = (unsigned int *)strtoul(dstaddr, &c, 0);
-	if(*c != 0) {
-		printf("incorrect destination address\n");
-		return;
-	}
-	srcaddr2 = (unsigned int *)strtoul(srcaddr, &c, 0);
-	if(*c != 0) {
-		printf("incorrect source address\n");
-		return;
-	}
-	if(*count == 0) {
-		count2 = 1;
-	} else {
-		count2 = strtoul(count, &c, 0);
-		if(*c != 0) {
-			printf("incorrect count\n");
-			return;
-		}
-	}
-	for (i=0;i<count2;i++) *dstaddr2++ = *srcaddr2++;
-}
-
-#if (defined CSR_SPIFLASH_BASE && defined SPIFLASH_PAGE_SIZE)
-static void fw(char *addr, char *value, char *count)
-{
-	char *c;
-	unsigned int addr2;
-	unsigned int value2;
-	unsigned int count2;
-	unsigned int i;
-
-	if((*addr == 0) || (*value == 0)) {
-		printf("fw <offset> <value> [count]\n");
-		return;
-	}
-	addr2 = strtoul(addr, &c, 0);
-	if(*c != 0) {
-		printf("incorrect offset\n");
-		return;
-	}
-	value2 = strtoul(value, &c, 0);
-	if(*c != 0) {
-		printf("incorrect value\n");
-		return;
-	}
-	if(*count == 0) {
-		count2 = 1;
-	} else {
-		count2 = strtoul(count, &c, 0);
-		if(*c != 0) {
-			printf("incorrect count\n");
-			return;
-		}
-	}
-	for (i=0;i<count2;i++) write_to_flash(addr2 + i * 4, (unsigned char *)&value2, 4);
-}
-
-static void fe(void)
-{
-	erase_flash();
-	printf("flash erased\n");
-}
-#endif
-
-#ifdef CSR_ETHPHY_MDIO_W_ADDR
-static void mdiow(char *phyadr, char *reg, char *val)
-{
-	char *c;
-	unsigned int phyadr2;
-	unsigned int reg2;
-	unsigned int val2;
-
-	if((*phyadr == 0) || (*reg == 0) || (*val == 0)) {
-		printf("mdiow <phyadr> <reg> <value>\n");
-		return;
-	}
-	phyadr2 = strtoul(phyadr, &c, 0);
-	if(*c != 0) {
-		printf("incorrect phyadr\n");
-		return;
-	}
-	reg2 = strtoul(reg, &c, 0);
-	if(*c != 0) {
-		printf("incorrect reg\n");
-		return;
-	}
-	val2 = strtoul(val, &c, 0);
-	if(*c != 0) {
-		printf("incorrect val\n");
-		return;
-	}
-	mdio_write(phyadr2, reg2, val2);
-}
-
-static void mdior(char *phyadr, char *reg)
-{
-	char *c;
-	unsigned int phyadr2;
-	unsigned int reg2;
-	unsigned int val;
-
-	if((*phyadr == 0) || (*reg == 0)) {
-		printf("mdior <phyadr> <reg>\n");
-		return;
-	}
-	phyadr2 = strtoul(phyadr, &c, 0);
-	if(*c != 0) {
-		printf("incorrect phyadr\n");
-		return;
-	}
-	reg2 = strtoul(reg, &c, 0);
-	if(*c != 0) {
-		printf("incorrect reg\n");
-		return;
-	}
-	val = mdio_read(phyadr2, reg2);
-	printf("reg %d: 0x%04x\n", reg2, val);
-}
-
-static void mdiod(char *phyadr, char *count)
-{
-	char *c;
-	unsigned int phyadr2;
-	unsigned int count2;
-	unsigned int val;
-	int i;
-
-	if((*phyadr == 0) || (*count == 0)) {
-		printf("mdiod <phyadr> <count>\n");
-		return;
-	}
-	phyadr2 = strtoul(phyadr, &c, 0);
-	if(*c != 0) {
-		printf("incorrect phyadr\n");
-		return;
-	}
-	count2 = strtoul(count, &c, 0);
-	if(*c != 0) {
-		printf("incorrect count\n");
-		return;
-	}
-	printf("MDIO dump @0x%x:\n", phyadr2);
-	for (i=0; i<count2; i++) {
-		val = mdio_read(phyadr2, i);
-		printf("reg %d: 0x%04x\n", i, val);
-	}
-}
-#endif
-
-static void crc(char *startaddr, char *len)
-{
-	char *c;
-	char *addr;
-	unsigned int length;
-
-	if((*startaddr == 0)||(*len == 0)) {
-		printf("crc <address> <length>\n");
-		return;
-	}
-	addr = (char *)strtoul(startaddr, &c, 0);
-	if(*c != 0) {
-		printf("incorrect address\n");
-		return;
-	}
-	length = strtoul(len, &c, 0);
-	if(*c != 0) {
-		printf("incorrect length\n");
-		return;
-	}
-
-	printf("CRC32: %08x\n", crc32((unsigned char *)addr, length));
-}
-
-static void ident(void)
-{
-	char buffer[IDENT_SIZE];
-
-	get_ident(buffer);
-	printf("Ident: %s\n", buffer);
-}
-
-/* Init + command line */
-
-static void help(void)
-{
-	puts("LiteX BIOS, available commands:");
-	puts("mr         - read address space");
-	puts("mw         - write address space");
-	puts("mc         - copy address space");
-#if (defined CSR_SPIFLASH_BASE && defined SPIFLASH_PAGE_SIZE)
-	puts("fe         - erase whole flash");
-	puts("fw         - write to flash");
-
-#endif
-#ifdef CSR_ETHPHY_MDIO_W_ADDR
-	puts("mdiow      - write MDIO register");
-	puts("mdior      - read MDIO register");
-	puts("mdiod      - dump MDIO registers");
-#endif
-	puts("");
-	puts("crc        - compute CRC32 of a part of the address space");
-	puts("ident      - display identifier");
-	puts("");
-	puts("flush_cpu_dcache - flush CPU data cache");
-#ifdef CONFIG_L2_SIZE
-	puts("flush_l2_cache   - flush L2 cache");
-#endif
-	puts("");
-#ifdef CSR_CTRL_BASE
-	puts("reboot     - reset processor");
-#endif
-#ifdef CSR_ETHMAC_BASE
-	puts("netboot    - boot via TFTP");
-#endif
-	puts("serialboot - boot via SFL");
-#ifdef FLASH_BOOT_ADDRESS
-	puts("flashboot  - boot from flash");
-#endif
-#ifdef ROM_BOOT_ADDRESS
-	puts("romboot    - boot from embedded rom");
-#endif
-	puts("");
-#ifdef CSR_SDRAM_BASE
-	puts("memtest    - run a memory test");
-#endif
-	puts("");
-#ifdef CSR_SDCORE_BASE
-	puts("sdclk <freq>   - SDCard set clk frequency (Mhz)");
-	puts("sdinit         - SDCard initialization");
-	puts("sdtest <loops> - SDCard test");
-#endif
-#ifdef USDDRPHY_DEBUG
-	puts("");
-	puts("sdram_cdly value                - Set SDRAM clk/cmd delay");
-	puts("sdram_cal                       - run SDRAM calibration");
-	puts("sdram_mpr                       - read SDRAM MPR");
-	puts("sdram_mrwr reg value            - write SDRAM mode registers");
-	puts("sdram_cdly_scan enabled         - enable/disable cdly scan");
-#endif
-#ifdef CSR_SPISDCARD_BASE
-        puts("spisdcardboot   - boot from SDCard via SPI hardware bitbang");
-#endif
-}
-
-static char *get_token(char **str)
-{
-	char *c, *d;
-
-	c = (char *)strchr(*str, ' ');
-	if(c == NULL) {
-		d = *str;
-		*str = *str+strlen(*str);
-		return d;
-	}
-	*c = 0;
-	d = *str;
-	*str = c+1;
-	return d;
-}
-
-#ifdef CSR_CTRL_BASE
-static void reboot(void)
-{
-	ctrl_reset_write(1);
-}
-#endif
-
-static void do_command(char *c)
-{
-	char *token;
-
-	token = get_token(&c);
-
-	if(strcmp(token, "mr") == 0) mr(get_token(&c), get_token(&c));
-	else if(strcmp(token, "mw") == 0) mw(get_token(&c), get_token(&c), get_token(&c));
-	else if(strcmp(token, "mc") == 0) mc(get_token(&c), get_token(&c), get_token(&c));
-#if (defined CSR_SPIFLASH_BASE && defined SPIFLASH_PAGE_SIZE)
-	else if(strcmp(token, "fw") == 0) fw(get_token(&c), get_token(&c), get_token(&c));
-	else if(strcmp(token, "fe") == 0) fe();
-#endif
-#ifdef CSR_ETHPHY_MDIO_W_ADDR
-	else if(strcmp(token, "mdiow") == 0) mdiow(get_token(&c), get_token(&c), get_token(&c));
-	else if(strcmp(token, "mdior") == 0) mdior(get_token(&c), get_token(&c));
-	else if(strcmp(token, "mdiod") == 0) mdiod(get_token(&c), get_token(&c));
-#endif
-	else if(strcmp(token, "crc") == 0) crc(get_token(&c), get_token(&c));
-	else if(strcmp(token, "ident") == 0) ident();
-
-	else if(strcmp(token, "flush_cpu_dcache") == 0) flush_cpu_dcache();
-#ifdef CONFIG_L2_SIZE
-	else if(strcmp(token, "flush_l2_cache") == 0) flush_l2_cache();
-#endif
-
-#ifdef CSR_CTRL_BASE
-	else if(strcmp(token, "reboot") == 0) reboot();
-#endif
-#ifdef FLASH_BOOT_ADDRESS
-	else if(strcmp(token, "flashboot") == 0) flashboot();
-#endif
-#ifdef ROM_BOOT_ADDRESS
-	else if(strcmp(token, "romboot") == 0) romboot();
-#endif
-	else if(strcmp(token, "serialboot") == 0) serialboot();
-#ifdef CSR_ETHMAC_BASE
-	else if(strcmp(token, "netboot") == 0) netboot();
-#endif
-
-	else if(strcmp(token, "help") == 0) help();
-
-#ifdef CSR_SDRAM_BASE
-	else if(strcmp(token, "sdrrow") == 0) sdrrow(get_token(&c));
-	else if(strcmp(token, "sdrsw") == 0) sdrsw();
-	else if(strcmp(token, "sdrhw") == 0) sdrhw();
-	else if(strcmp(token, "sdrrdbuf") == 0) sdrrdbuf(-1);
-	else if(strcmp(token, "sdrrd") == 0) sdrrd(get_token(&c), get_token(&c));
-	else if(strcmp(token, "sdrrderr") == 0) sdrrderr(get_token(&c));
-	else if(strcmp(token, "sdrwr") == 0) sdrwr(get_token(&c));
-#ifdef CSR_DDRPHY_BASE
-	else if(strcmp(token, "sdrinit") == 0) sdrinit();
-#ifdef SDRAM_PHY_WRITE_LEVELING_CAPABLE
-	else if(strcmp(token, "sdrwlon") == 0) sdrwlon();
-	else if(strcmp(token, "sdrwloff") == 0) sdrwloff();
-#endif
-	else if(strcmp(token, "sdrlevel") == 0) sdrlevel();
-#endif
-	else if(strcmp(token, "memtest") == 0) memtest();
-#endif
-
-#ifdef CSR_SDCORE_BASE
-	else if(strcmp(token, "sdclk") == 0) sdclk_set_clk(atoi(get_token(&c)));
-	else if(strcmp(token, "sdinit") == 0) sdcard_init();
-	else if(strcmp(token, "sdtest") == 0) sdcard_test(atoi(get_token(&c)));
-#endif
-#ifdef USDDRPHY_DEBUG
-	else if(strcmp(token, "sdram_cdly") == 0)
-		ddrphy_cdly(atoi(get_token(&c)));
-	else if(strcmp(token, "sdram_cal") == 0)
-		sdrcal();
-	else if(strcmp(token, "sdram_mpr") == 0)
-		sdrmpr();
-	else if(strcmp(token, "sdram_mrwr") == 0) {
-		unsigned int reg;
-		unsigned int value;
-		reg = atoi(get_token(&c));
-		value = atoi(get_token(&c));
-		sdrsw();
-		printf("Writing 0x%04x to SDRAM mode register %d\n", value, reg);
-		sdrmrwr(reg, value);
-		sdrhw();
-	}
-	else if(strcmp(token, "sdram_cdly_scan") == 0) {
-		unsigned int enabled;
-		enabled = atoi(get_token(&c));
-		sdr_cdly_scan(enabled);
-	}
-#endif
-#ifdef CSR_SPISDCARD_BASE
-        else if(strcmp(token, "spisdcardboot") == 0) spisdcardboot();
-#endif
-
-	else if(strcmp(token, "") != 0)
-		printf("Command not found\n");
-}
+#include "command.h"
 
 static void boot_sequence(void)
 {
@@ -511,7 +72,12 @@ static void boot_sequence(void)
 int main(int i, char **c)
 {
 	char buffer[CMD_LINE_BUFFER_SIZE];
+	char *params[MAX_PARAM];
+	char *command;
+	struct command_struct *cmd;
+	int nb_params;
 	int sdr_ok;
+
 #ifdef CONFIG_CPU_HAS_INTERRUPT
 	irq_setmask(0);
 	irq_setie(1);
@@ -600,7 +166,10 @@ int main(int i, char **c)
 		readline(buffer, CMD_LINE_BUFFER_SIZE);
 		if (buffer[0] != 0) {
 			printf("\n");
-			do_command(buffer);
+			nb_params = get_param(buffer, &command, params);
+			cmd = command_dispatcher(command, nb_params, params);
+			if (!cmd)
+				printf("Command not found");
 		}
 		printf("\n%s", PROMPT);
 	}
diff --git a/litex/soc/software/bios/sdram.c b/litex/soc/software/bios/sdram.c
index 513a12665..1e139d5d2 100644
--- a/litex/soc/software/bios/sdram.c
+++ b/litex/soc/software/bios/sdram.c
@@ -78,28 +78,18 @@ void sdrhw(void)
 	printf("SDRAM now under hardware control\n");
 }
 
-void sdrrow(char *_row)
+void sdrrow(unsigned int row)
 {
-	char *c;
-	unsigned int row;
-
-	if(*_row == 0) {
+	if(row == 0) {
 		sdram_dfii_pi0_address_write(0x0000);
 		sdram_dfii_pi0_baddress_write(0);
 		command_p0(DFII_COMMAND_RAS|DFII_COMMAND_WE|DFII_COMMAND_CS);
 		cdelay(15);
-		printf("Precharged\n");
 	} else {
-		row = strtoul(_row, &c, 0);
-		if(*c != 0) {
-			printf("incorrect row\n");
-			return;
-		}
 		sdram_dfii_pi0_address_write(row);
 		sdram_dfii_pi0_baddress_write(0);
 		command_p0(DFII_COMMAND_RAS|DFII_COMMAND_CS);
 		cdelay(15);
-		printf("Activated row %d\n", row);
 	}
 }
 
@@ -126,58 +116,23 @@ void sdrrdbuf(int dq)
 	printf("\n");
 }
 
-void sdrrd(char *startaddr, char *dq)
+void sdrrd(unsigned int addr, int dq)
 {
-	char *c;
-	unsigned int addr;
-	int _dq;
-
-	if(*startaddr == 0) {
-		printf("sdrrd <address>\n");
-		return;
-	}
-	addr = strtoul(startaddr, &c, 0);
-	if(*c != 0) {
-		printf("incorrect address\n");
-		return;
-	}
-	if(*dq == 0)
-		_dq = -1;
-	else {
-		_dq = strtoul(dq, &c, 0);
-		if(*c != 0) {
-			printf("incorrect DQ\n");
-			return;
-		}
-	}
-
 	sdram_dfii_pird_address_write(addr);
 	sdram_dfii_pird_baddress_write(0);
 	command_prd(DFII_COMMAND_CAS|DFII_COMMAND_CS|DFII_COMMAND_RDDATA);
 	cdelay(15);
-	sdrrdbuf(_dq);
+	sdrrdbuf(dq);
 }
 
-void sdrrderr(char *count)
+void sdrrderr(int count)
 {
 	int addr;
-	char *c;
-	int _count;
 	int i, j, p;
 	unsigned char prev_data[SDRAM_PHY_PHASES][DFII_PIX_DATA_BYTES];
 	unsigned char errs[SDRAM_PHY_PHASES][DFII_PIX_DATA_BYTES];
 	unsigned char new_data[DFII_PIX_DATA_BYTES];
 
-	if(*count == 0) {
-		printf("sdrrderr <count>\n");
-		return;
-	}
-	_count = strtoul(count, &c, 0);
-	if(*c != 0) {
-		printf("incorrect count\n");
-		return;
-	}
-
 	for(p=0;p<SDRAM_PHY_PHASES;p++)
 		for(i=0;i<DFII_PIX_DATA_BYTES;i++)
 			errs[p][i] = 0;
@@ -191,7 +146,7 @@ void sdrrderr(char *count)
 			csr_rd_buf_uint8(sdram_dfii_pix_rddata_addr[p],
 					 prev_data[p], DFII_PIX_DATA_BYTES);
 
-		for(j=0;j<_count;j++) {
+		for(j=0;j<count;j++) {
 			command_prd(DFII_COMMAND_CAS|DFII_COMMAND_CS|DFII_COMMAND_RDDATA);
 			cdelay(15);
 			for(p=0;p<SDRAM_PHY_PHASES;p++) {
@@ -215,23 +170,11 @@ void sdrrderr(char *count)
 	printf("\n");
 }
 
-void sdrwr(char *startaddr)
+void sdrwr(unsigned int addr)
 {
 	int i, p;
-	char *c;
-	unsigned int addr;
 	unsigned char buf[DFII_PIX_DATA_BYTES];
 
-	if(*startaddr == 0) {
-		printf("sdrwr <address>\n");
-		return;
-	}
-	addr = strtoul(startaddr, &c, 0);
-	if(*c != 0) {
-		printf("incorrect address\n");
-		return;
-	}
-
 	for(p=0;p<SDRAM_PHY_PHASES;p++) {
 		for(i=0;i<DFII_PIX_DATA_BYTES;i++)
 			buf[i] = 0x10*p + i;
diff --git a/litex/soc/software/bios/sdram.h b/litex/soc/software/bios/sdram.h
index a25711919..d777c22cf 100644
--- a/litex/soc/software/bios/sdram.h
+++ b/litex/soc/software/bios/sdram.h
@@ -5,11 +5,11 @@
 
 void sdrsw(void);
 void sdrhw(void);
-void sdrrow(char *_row);
+void sdrrow(unsigned int row);
 void sdrrdbuf(int dq);
-void sdrrd(char *startaddr, char *dq);
-void sdrrderr(char *count);
-void sdrwr(char *startaddr);
+void sdrrd(unsigned int addr, int dq);
+void sdrrderr(int count);
+void sdrwr(unsigned int addr);
 
 void sdrwlon(void);
 void sdrwloff(void);

From 74dc444b02ec437d13eae26aeb4939ee6bd6282b Mon Sep 17 00:00:00 2001
From: Franck Jullien <franck.jullien@gmail.com>
Date: Wed, 29 Apr 2020 21:57:13 +0200
Subject: [PATCH 54/95] bios: add auto completion for commands

---
 litex/soc/software/bios/Makefile   |   6 +
 litex/soc/software/bios/command.h  |   2 +
 litex/soc/software/bios/complete.c | 174 +++++++++++++++++++++++++++++
 litex/soc/software/bios/complete.h |   6 +
 litex/soc/software/bios/readline.c |  28 +++++
 5 files changed, 216 insertions(+)
 create mode 100644 litex/soc/software/bios/complete.c
 create mode 100644 litex/soc/software/bios/complete.h

diff --git a/litex/soc/software/bios/Makefile b/litex/soc/software/bios/Makefile
index c80e0a130..4b8c6a51c 100755
--- a/litex/soc/software/bios/Makefile
+++ b/litex/soc/software/bios/Makefile
@@ -26,6 +26,12 @@ OBJECTS = isr.o			\
 	  cmd_spi_flash.o	\
 	  cmd_usddrphy.o
 
+ifneq "$(or $(TERM_NO_COMPLETE),$(TERM_MINI))" ""
+CFLAGS += -DTERM_NO_COMPLETE
+else
+OBJECTS += complete.o
+endif
+
 ifdef TERM_NO_HIST
 CFLAGS += -DTERM_NO_HIST
 endif
diff --git a/litex/soc/software/bios/command.h b/litex/soc/software/bios/command.h
index 247043895..693d79825 100644
--- a/litex/soc/software/bios/command.h
+++ b/litex/soc/software/bios/command.h
@@ -7,6 +7,8 @@
 
 #define MAX_PARAM	8
 
+#define HIST_DEPTH	10	/* Used in string list, complete.c */
+
 #define MISC_CMDS	0
 #define SYSTEM_CMDS	1
 #define CACHE_CMDS	2
diff --git a/litex/soc/software/bios/complete.c b/litex/soc/software/bios/complete.c
new file mode 100644
index 000000000..e4283297f
--- /dev/null
+++ b/litex/soc/software/bios/complete.c
@@ -0,0 +1,174 @@
+// This file is Copyright (c) 2020 Franck Jullien <franck.jullien@gmail.com>
+//
+//     Largely inspired/copied from U-boot and Barebox projects wich are:
+//         Sascha Hauer, Pengutronix, <s.hauer@pengutronix.de>
+
+// License: BSD
+
+#include <stdlib.h>
+#include <stdio.h>
+#include <string.h>
+
+#include "readline.h"
+#include "helpers.h"
+#include "command.h"
+#include "complete.h"
+
+static int tab_pressed = 0;
+
+char sl[HIST_DEPTH][CMD_LINE_BUFFER_SIZE];
+int sl_idx = 0;
+
+char out[CMD_LINE_BUFFER_SIZE];
+
+static void string_list_init(void)
+{
+	int i;
+	for (i = 0; i < HIST_DEPTH; i++)
+		sl[i][0] = 0;
+}
+
+static int string_list_add(const char *string)
+{
+	int i;
+	for (i = 0; i < HIST_DEPTH; i++) {
+		if (sl[i][0] == 0) {
+			strncpy(&sl[i][0], string, CMD_LINE_BUFFER_SIZE);
+			return 0;
+		}
+	}
+	return -1;
+}
+
+static int string_list_empty(void)
+{
+	int i;
+	for (i = 0; i < HIST_DEPTH; i++)
+		if (sl[i][0] != 0)
+			return 0;
+	return 1;
+}
+
+static int string_list_count(void)
+{
+	int i, count = 0;
+	for (i = 0; i < HIST_DEPTH; i++)
+		if (sl[i][0] != 0)
+			count++;
+	return count;
+}
+
+static char *list_first_entry(void)
+{
+	int i;
+	for (i = 0; i < HIST_DEPTH; i++)
+		if (sl[i][0] != 0)
+			return &sl[i][0];
+	return NULL;
+}
+
+static void string_list_print_by_column(void)
+{
+	int len = 0, num, i, j;
+
+	for (i = 0; i < HIST_DEPTH; i++) {
+		if (sl[i][0] != 0) {
+			int l = strlen(&sl[i][0]) + 4;
+			if (l > len)
+				len = l;
+		}
+	}
+
+	if (!len)
+		return;
+
+	num = 80 / (len + 1);
+
+	for (j = 0; j < HIST_DEPTH; j++) {
+		if (sl[j][0] != 0) {
+			if (!(++i % num))
+				printf("%s\n", &sl[j][0]);
+			else
+				printf("%-*s", len, &sl[j][0]);
+		}
+	}
+	if (i % num)
+		printf("\n");
+}
+
+static void command_complete(char *instr)
+{
+	struct command_struct * const *cmd;
+
+	for (cmd = __bios_cmd_start; cmd != __bios_cmd_end; cmd++)
+		if (!strncmp(instr, (*cmd)->name, strlen(instr)))
+			string_list_add((*cmd)->name);
+}
+
+int complete(char *instr, char **outstr)
+{
+	int pos;
+	char ch;
+	int changed;
+	int outpos = 0;
+	int reprint = 0;
+	char *first_entry;
+	char *entry;
+	int i;
+
+	string_list_init();
+	command_complete(instr);
+
+	pos = strlen(instr);
+
+	*outstr = "";
+	if (string_list_empty())
+		reprint = 0;
+	else
+	{
+		out[0] = 0;
+
+		first_entry = list_first_entry();
+
+		while (1) {
+			entry = first_entry;
+			ch = entry[pos];
+			if (!ch)
+				break;
+
+			changed = 0;
+			for (i = 0; i < HIST_DEPTH; i++) {
+				if (sl[i][0] != 0) {
+					if (!sl[i][pos])
+						break;
+					if (ch != sl[i][pos]) {
+						changed = 1;
+						break;
+					}
+				}
+			}
+
+			if (changed)
+				break;
+			out[outpos++] = ch;
+			pos++;
+		}
+
+		if ((string_list_count() != 1) && !outpos && tab_pressed) {
+			printf("\n");
+			string_list_print_by_column();
+			reprint = 1;
+			tab_pressed = 0;
+		}
+
+		out[outpos++] = 0;
+		*outstr = out;
+
+		if (*out == 0)
+			tab_pressed = 1;
+		else
+			tab_pressed = 0;
+	}
+
+	return reprint;
+}
diff --git a/litex/soc/software/bios/complete.h b/litex/soc/software/bios/complete.h
new file mode 100644
index 000000000..b615df76a
--- /dev/null
+++ b/litex/soc/software/bios/complete.h
@@ -0,0 +1,6 @@
+#ifndef __COMPLETE_H__
+#define __COMPLETE_H__
+
+int complete(char *instr, char **outstr);
+
+#endif
diff --git a/litex/soc/software/bios/readline.c b/litex/soc/software/bios/readline.c
index 998ebc0ef..48d8f1a6c 100644
--- a/litex/soc/software/bios/readline.c
+++ b/litex/soc/software/bios/readline.c
@@ -17,6 +17,7 @@
 #include <uart.h>
 
 #include "readline.h"
+#include "complete.h"
 
 #ifndef TERM_NO_HIST
 static int hist_max = 0;
@@ -191,6 +192,12 @@ int readline(char *buf, int len)
 	int insert = 1;
 	char ichar;
 
+#ifndef TERM_NO_COMPLETE
+	char tmp;
+	int reprint, i;
+	char *completestr;
+#endif
+
 	while (1) {
 
 		ichar = read_key();
@@ -200,6 +207,27 @@ int readline(char *buf, int len)
 
 		switch (ichar) {
 		case '\t':
+#ifndef TERM_NO_COMPLETE
+			buf[eol_num] = 0;
+			tmp = buf[num];
+
+			buf[num] = 0;
+			reprint = complete(buf, &completestr);
+			buf[num] = tmp;
+
+			if (reprint) {
+				printf("%s%s", PROMPT, buf);
+
+				if (tmp)
+					for (i = 0; i < eol_num - num; i++)
+						getcmd_putch(CTL_BACKSPACE);
+			}
+
+			i = 0;
+			while (completestr[i])
+				cread_add_char(completestr[i++], insert, &num,
+						&eol_num, buf, len);
+#endif
 			break;
 
 		case KEY_HOME:

From 3c70c83f9b31549a1fb48091dcaef5fb0993b6bc Mon Sep 17 00:00:00 2001
From: Florent Kermarrec <florent@enjoy-digital.fr>
Date: Fri, 1 May 2020 12:35:12 +0200
Subject: [PATCH 55/95] cpu/software: move flush_cpu_icache/flush_cpu_dcache
 functions to CPUs.

---
 litex/soc/cores/cpu/blackparrot/system.h      |   5 +-
 litex/soc/cores/cpu/lm32/system.h             |  21 +++-
 litex/soc/cores/cpu/microwatt/system.h        |   4 +-
 litex/soc/cores/cpu/minerva/system.h          |   5 +-
 .../base => cores/cpu/mor1kx}/spr-defs.h      |  10 +-
 litex/soc/cores/cpu/mor1kx/system.h           |  51 ++++++--
 litex/soc/cores/cpu/picorv32/system.h         |   4 +-
 litex/soc/cores/cpu/rocket/system.h           |   4 +-
 litex/soc/cores/cpu/serv/system.h             |   4 +-
 litex/soc/cores/cpu/vexriscv/system.h         |  27 ++++-
 litex/soc/software/libbase/system.c           | 111 ------------------
 11 files changed, 105 insertions(+), 141 deletions(-)
 rename litex/soc/{software/include/base => cores/cpu/mor1kx}/spr-defs.h (99%)

diff --git a/litex/soc/cores/cpu/blackparrot/system.h b/litex/soc/cores/cpu/blackparrot/system.h
index cccdb54d2..079c7cfd7 100644
--- a/litex/soc/cores/cpu/blackparrot/system.h
+++ b/litex/soc/cores/cpu/blackparrot/system.h
@@ -5,10 +5,9 @@
 extern "C" {
 #endif
 
-void flush_cpu_icache(void);
-void flush_cpu_dcache(void);
+__attribute__((unused)) static void flush_cpu_icache(void){};  /* FIXME: do something useful here! */
+__attribute__((unused)) static void flush_cpu_dcache(void){};  /* FIXME: do something useful here! */
 void flush_l2_cache(void);
-
 void busy_wait(unsigned int ms);
 
 #include <csr-defs.h>
diff --git a/litex/soc/cores/cpu/lm32/system.h b/litex/soc/cores/cpu/lm32/system.h
index 989c9c621..1272cf1ae 100644
--- a/litex/soc/cores/cpu/lm32/system.h
+++ b/litex/soc/cores/cpu/lm32/system.h
@@ -5,8 +5,25 @@
 extern "C" {
 #endif
 
-void flush_cpu_icache(void);
-void flush_cpu_dcache(void);
+__attribute__((unused)) static void flush_cpu_icache(void)
+{
+	asm volatile(
+		"wcsr ICC, r0\n"
+		"nop\n"
+		"nop\n"
+		"nop\n"
+		"nop\n"
+	);
+}
+
+__attribute__((unused)) static void flush_cpu_dcache(void)
+{
+	asm volatile(
+		"wcsr DCC, r0\n"
+		"nop\n"
+	);
+}
+
 void flush_l2_cache(void);
 
 void busy_wait(unsigned int ms);
diff --git a/litex/soc/cores/cpu/microwatt/system.h b/litex/soc/cores/cpu/microwatt/system.h
index 989c9c621..941dc5644 100644
--- a/litex/soc/cores/cpu/microwatt/system.h
+++ b/litex/soc/cores/cpu/microwatt/system.h
@@ -5,8 +5,8 @@
 extern "C" {
 #endif
 
-void flush_cpu_icache(void);
-void flush_cpu_dcache(void);
+__attribute__((unused)) static void flush_cpu_icache(void){}; /* FIXME: do something useful here! */
+__attribute__((unused)) static void flush_cpu_dcache(void){}; /* FIXME: do something useful here! */
 void flush_l2_cache(void);
 
 void busy_wait(unsigned int ms);
diff --git a/litex/soc/cores/cpu/minerva/system.h b/litex/soc/cores/cpu/minerva/system.h
index cccdb54d2..408ab3659 100644
--- a/litex/soc/cores/cpu/minerva/system.h
+++ b/litex/soc/cores/cpu/minerva/system.h
@@ -5,10 +5,9 @@
 extern "C" {
 #endif
 
-void flush_cpu_icache(void);
-void flush_cpu_dcache(void);
+__attribute__((unused)) static void flush_cpu_icache(void){}; /* FIXME: do something useful here! */
+__attribute__((unused)) static void flush_cpu_dcache(void){}; /* FIXME: do something useful here! */
 void flush_l2_cache(void);
-
 void busy_wait(unsigned int ms);
 
 #include <csr-defs.h>
diff --git a/litex/soc/software/include/base/spr-defs.h b/litex/soc/cores/cpu/mor1kx/spr-defs.h
similarity index 99%
rename from litex/soc/software/include/base/spr-defs.h
rename to litex/soc/cores/cpu/mor1kx/spr-defs.h
index e073a5068..4dbc3b1c7 100644
--- a/litex/soc/software/include/base/spr-defs.h
+++ b/litex/soc/cores/cpu/mor1kx/spr-defs.h
@@ -1,8 +1,8 @@
 /* spr-defs.h - Special purpose registers definitions file
-	
+
    Copyright (C) 2000 Damjan Lampret
    Copyright (C) 2008, 2010 Embecosm Limited
-   
+
    Contributor Damjan Lampret <lampret@opencores.org>
    Contributor Jeremy Bennett <jeremy.bennett@embecosm.com>
 
@@ -184,10 +184,10 @@
 #define SPR_CPUCFGR_OV64S  0x00000200  /* ORVDX64 supported */
 #define SPR_CPUCFGR_ND     0x00000400  /* No delay-slot */
 #define SPR_CPUCFGR_AVRP   0x00000800  /* Architecture version register present */
-#define SPR_CPUCFGR_EVBARP 0x00001000  /* Exception vector base address register 
+#define SPR_CPUCFGR_EVBARP 0x00001000  /* Exception vector base address register
 					  present */
 #define SPR_CPUCFGR_ISRP   0x00002000  /* Implementation-specific registers present */
-#define SPR_CPUCFGR_AECSRP 0x00004000  /* Arithmetic exception control/status 
+#define SPR_CPUCFGR_AECSRP 0x00004000  /* Arithmetic exception control/status
 					  registers present */
 #define SPR_CPUCFGR_RES	   0xffff8000  /* Reserved */
 
@@ -628,7 +628,7 @@
 #define SPR_PCMR_DDS	0x00004000  /* Data dependency stall event */
 #define SPR_PCMR_WPE	0x03ff8000  /* Watchpoint events */
 
-/* 
+/*
  * Bit definitions for the Power management register
  *
  */
diff --git a/litex/soc/cores/cpu/mor1kx/system.h b/litex/soc/cores/cpu/mor1kx/system.h
index 004a00e3c..77366810a 100644
--- a/litex/soc/cores/cpu/mor1kx/system.h
+++ b/litex/soc/cores/cpu/mor1kx/system.h
@@ -1,17 +1,12 @@
 #ifndef __SYSTEM_H
 #define __SYSTEM_H
 
+#include <spr-defs.h>
+
 #ifdef __cplusplus
 extern "C" {
 #endif
 
-void flush_cpu_icache(void);
-void flush_cpu_dcache(void);
-void flush_l2_cache(void);
-
-void busy_wait(unsigned int ms);
-
-#include <spr-defs.h>
 static inline unsigned long mfspr(unsigned long add)
 {
 	unsigned long ret;
@@ -26,6 +21,48 @@ static inline void mtspr(unsigned long add, unsigned long val)
 	__asm__ __volatile__ ("l.mtspr %0,%1,0" : : "r" (add), "r" (val));
 }
 
+__attribute__((unused)) static void flush_cpu_icache(void)
+{
+	unsigned long iccfgr;
+	unsigned long cache_set_size;
+	unsigned long cache_ways;
+	unsigned long cache_block_size;
+	unsigned long cache_size;
+	int i;
+
+	iccfgr = mfspr(SPR_ICCFGR);
+	cache_ways = 1 << (iccfgr & SPR_ICCFGR_NCW);
+	cache_set_size = 1 << ((iccfgr & SPR_ICCFGR_NCS) >> 3);
+	cache_block_size = (iccfgr & SPR_ICCFGR_CBS) ? 32 : 16;
+	cache_size = cache_set_size * cache_ways * cache_block_size;
+
+	for (i = 0; i < cache_size; i += cache_block_size)
+		mtspr(SPR_ICBIR, i);
+}
+
+__attribute__((unused)) static void flush_cpu_dcache(void)
+{
+	unsigned long dccfgr;
+	unsigned long cache_set_size;
+	unsigned long cache_ways;
+	unsigned long cache_block_size;
+	unsigned long cache_size;
+	int i;
+
+	dccfgr = mfspr(SPR_DCCFGR);
+	cache_ways = 1 << (dccfgr & SPR_ICCFGR_NCW);
+	cache_set_size = 1 << ((dccfgr & SPR_DCCFGR_NCS) >> 3);
+	cache_block_size = (dccfgr & SPR_DCCFGR_CBS) ? 32 : 16;
+	cache_size = cache_set_size * cache_ways * cache_block_size;
+
+	for (i = 0; i < cache_size; i += cache_block_size)
+		mtspr(SPR_DCBIR, i);
+}
+
+void flush_l2_cache(void);
+
+void busy_wait(unsigned int ms);
+
 #ifdef __cplusplus
 }
 #endif
diff --git a/litex/soc/cores/cpu/picorv32/system.h b/litex/soc/cores/cpu/picorv32/system.h
index 989c9c621..afa56d677 100644
--- a/litex/soc/cores/cpu/picorv32/system.h
+++ b/litex/soc/cores/cpu/picorv32/system.h
@@ -5,8 +5,8 @@
 extern "C" {
 #endif
 
-void flush_cpu_icache(void);
-void flush_cpu_dcache(void);
+__attribute__((unused)) static void flush_cpu_icache(void){}; /* No instruction cache */
+__attribute__((unused)) static void flush_cpu_dcache(void){}; /* No instruction cache */
 void flush_l2_cache(void);
 
 void busy_wait(unsigned int ms);
diff --git a/litex/soc/cores/cpu/rocket/system.h b/litex/soc/cores/cpu/rocket/system.h
index cccdb54d2..d3e98e1db 100644
--- a/litex/soc/cores/cpu/rocket/system.h
+++ b/litex/soc/cores/cpu/rocket/system.h
@@ -5,8 +5,8 @@
 extern "C" {
 #endif
 
-void flush_cpu_icache(void);
-void flush_cpu_dcache(void);
+__attribute__((unused)) static void flush_cpu_icache(void){}  /* FIXME: do something useful here! */
+__attribute__((unused)) static void flush_cpu_dcache(void){}; /* FIXME: do something useful here! */
 void flush_l2_cache(void);
 
 void busy_wait(unsigned int ms);
diff --git a/litex/soc/cores/cpu/serv/system.h b/litex/soc/cores/cpu/serv/system.h
index 989c9c621..afa56d677 100644
--- a/litex/soc/cores/cpu/serv/system.h
+++ b/litex/soc/cores/cpu/serv/system.h
@@ -5,8 +5,8 @@
 extern "C" {
 #endif
 
-void flush_cpu_icache(void);
-void flush_cpu_dcache(void);
+__attribute__((unused)) static void flush_cpu_icache(void){}; /* No instruction cache */
+__attribute__((unused)) static void flush_cpu_dcache(void){}; /* No instruction cache */
 void flush_l2_cache(void);
 
 void busy_wait(unsigned int ms);
diff --git a/litex/soc/cores/cpu/vexriscv/system.h b/litex/soc/cores/cpu/vexriscv/system.h
index cccdb54d2..952b5b326 100644
--- a/litex/soc/cores/cpu/vexriscv/system.h
+++ b/litex/soc/cores/cpu/vexriscv/system.h
@@ -1,12 +1,35 @@
 #ifndef __SYSTEM_H
 #define __SYSTEM_H
 
+#include <csr-defs.h>
+
 #ifdef __cplusplus
 extern "C" {
 #endif
 
-void flush_cpu_icache(void);
-void flush_cpu_dcache(void);
+__attribute__((unused)) static void flush_cpu_icache(void)
+{
+  asm volatile(
+    ".word(0x400F)\n"
+    "nop\n"
+    "nop\n"
+    "nop\n"
+    "nop\n"
+    "nop\n"
+  );
+}
+
+__attribute__((unused)) static void flush_cpu_dcache(void)
+{
+  unsigned long cache_info;
+  asm volatile ("csrr %0, %1" : "=r"(cache_info) : "i"(CSR_DCACHE_INFO));
+  unsigned long cache_way_size = cache_info & 0xFFFFF;
+  unsigned long cache_line_size = (cache_info >> 20) & 0xFFF;
+  for(register unsigned long idx = 0;idx < cache_way_size;idx += cache_line_size){
+    asm volatile("mv x10, %0 \n .word(0b01110000000001010101000000001111)"::"r"(idx));
+  }
+}
+
 void flush_l2_cache(void);
 
 void busy_wait(unsigned int ms);
diff --git a/litex/soc/software/libbase/system.c b/litex/soc/software/libbase/system.c
index 49d23ac6d..f9e37eb28 100644
--- a/litex/soc/software/libbase/system.c
+++ b/litex/soc/software/libbase/system.c
@@ -12,117 +12,6 @@
 #include <generated/mem.h>
 #include <generated/csr.h>
 
-void flush_cpu_icache(void)
-{
-#if defined (__lm32__)
-	asm volatile(
-		"wcsr ICC, r0\n"
-		"nop\n"
-		"nop\n"
-		"nop\n"
-		"nop\n"
-	);
-#elif defined (__or1k__)
-	unsigned long iccfgr;
-	unsigned long cache_set_size;
-	unsigned long cache_ways;
-	unsigned long cache_block_size;
-	unsigned long cache_size;
-	int i;
-
-	iccfgr = mfspr(SPR_ICCFGR);
-	cache_ways = 1 << (iccfgr & SPR_ICCFGR_NCW);
-	cache_set_size = 1 << ((iccfgr & SPR_ICCFGR_NCS) >> 3);
-	cache_block_size = (iccfgr & SPR_ICCFGR_CBS) ? 32 : 16;
-	cache_size = cache_set_size * cache_ways * cache_block_size;
-
-	for (i = 0; i < cache_size; i += cache_block_size)
-		mtspr(SPR_ICBIR, i);
-#elif defined (__picorv32__)
-	/* no instruction cache */
-	asm volatile("nop");
-#elif defined (__vexriscv__)
-	asm volatile(
-		".word(0x400F)\n"
-		"nop\n"
-		"nop\n"
-		"nop\n"
-		"nop\n"
-		"nop\n"
-	);
-#elif defined (__minerva__)
-	/* no instruction cache */
-	asm volatile("nop");
-#elif defined (__rocket__)
-	/* FIXME: do something useful here! */
-	asm volatile("nop");
-#elif defined (__microwatt__)
-	/* FIXME: do something useful here! */
-        asm volatile("nop");
-#elif defined (__blackparrot__)
-	/* TODO: BP do something useful here! */
-	asm volatile("nop");
-#elif defined (__serv__)
-	/* no instruction cache */
-#else
-#error Unsupported architecture
-#endif
-}
-
-void flush_cpu_dcache(void)
-{
-#if defined (__lm32__)
-	asm volatile(
-		"wcsr DCC, r0\n"
-		"nop\n"
-	);
-#elif defined (__or1k__)
-	unsigned long dccfgr;
-	unsigned long cache_set_size;
-	unsigned long cache_ways;
-	unsigned long cache_block_size;
-	unsigned long cache_size;
-	int i;
-
-	dccfgr = mfspr(SPR_DCCFGR);
-	cache_ways = 1 << (dccfgr & SPR_ICCFGR_NCW);
-	cache_set_size = 1 << ((dccfgr & SPR_DCCFGR_NCS) >> 3);
-	cache_block_size = (dccfgr & SPR_DCCFGR_CBS) ? 32 : 16;
-	cache_size = cache_set_size * cache_ways * cache_block_size;
-
-	for (i = 0; i < cache_size; i += cache_block_size)
-		mtspr(SPR_DCBIR, i);
-#elif defined (__picorv32__)
-	/* no data cache */
-	asm volatile("nop");
-#elif defined (__vexriscv__)
-	unsigned long cache_info;
-	asm volatile ("csrr %0, %1" : "=r"(cache_info) : "i"(CSR_DCACHE_INFO));
-	unsigned long cache_way_size = cache_info & 0xFFFFF;
-	unsigned long cache_line_size = (cache_info >> 20) & 0xFFF;
-	for(register unsigned long idx = 0;idx < cache_way_size;idx += cache_line_size){
-		asm volatile("mv x10, %0 \n .word(0b01110000000001010101000000001111)"::"r"(idx));
-	}
-#elif defined (__minerva__)
-	/* no data cache */
-	asm volatile("nop");
-#elif defined (__rocket__)
-	/* FIXME: do something useful here! */
-	asm volatile("nop");
-#elif defined (__microwatt__)
-	/* FIXME: do something useful here! */
-	asm volatile("nop");
-/*SC_add: What BB does here?*/
-#elif defined (__blackparrot__)
-	/* FIXME: do something useful here! */
-	asm volatile("nop");
-#elif defined (__serv__)
-	/* no data cache */
-#else
-#error Unsupported architecture
-#endif
-}
-
 #ifdef CONFIG_L2_SIZE
 void flush_l2_cache(void)
 {

From c8e3bba4b7f4bcfc683ac162d7983cddf929b2db Mon Sep 17 00:00:00 2001
From: Gabriel Somlo <gsomlo@gmail.com>
Date: Fri, 1 May 2020 09:45:42 -0400
Subject: [PATCH 56/95] software: spisdcard: cosmetic: avoid filling screen
 with cluster numbers

Signed-off-by: Gabriel Somlo <gsomlo@gmail.com>
---
 litex/soc/software/libbase/spisdcard.c | 7 +++----
 1 file changed, 3 insertions(+), 4 deletions(-)

diff --git a/litex/soc/software/libbase/spisdcard.c b/litex/soc/software/libbase/spisdcard.c
index ab6cbe039..ae3ec7305 100644
--- a/litex/soc/software/libbase/spisdcard.c
+++ b/litex/soc/software/libbase/spisdcard.c
@@ -567,10 +567,9 @@ uint8_t spi_sdcard_readFile(char *filename, char *ext, unsigned long address)
 
     // Read each cluster sector by sector, i being number of clusters
     bytesRemaining=fileLength;
-    printf("Clusters: ");
     // Calculate number of clusters (always >1)
     for(i=0; i<1+((fileLength/sdCardFatBootSector.sectors_per_cluster)/sdCardFatBootSector.sector_size); i++) {
-        printf("%d ",fileClusterStart);
+        printf("\rCluster: %d",fileClusterStart);
 
         // Locate start of cluster on SD CARD and read appropraite number of sectors
         clusterSectorStart=rootDirSectorStart+(fileClusterStart-1)*sdCardFatBootSector.sectors_per_cluster;
@@ -580,14 +579,14 @@ uint8_t spi_sdcard_readFile(char *filename, char *ext, unsigned long address)
             // Otherwise, read to sdCardSector buffer and transfer appropriate number of bytes
             if(bytesRemaining>sdCardFatBootSector.sector_size) {
                 if( readSector(clusterSectorStart+sector,(uint8_t *)address) == FAILURE ) {
-                    printf("Read Error\n");
+                    printf("\nRead Error\n");
                     return FAILURE;
                 }
                 bytesRemaining=bytesRemaining-sdCardFatBootSector.sector_size;
                 address=address+sdCardFatBootSector.sector_size;
             } else {
                 if( readSector(clusterSectorStart+sector,sdCardSector) == FAILURE ) {
-                    printf("Read Error\n");
+                    printf("\nRead Error\n");
                     return FAILURE;
                 }
                 memcpy((uint8_t *)address, sdCardSector, bytesRemaining);

From d3e3ca06185a7af193fb9dd2c6b487c2477996ad Mon Sep 17 00:00:00 2001
From: Florent Kermarrec <florent@enjoy-digital.fr>
Date: Fri, 1 May 2020 19:07:43 +0200
Subject: [PATCH 57/95] CHANGES: start listing changes for next release.

---
 CHANGES | 16 ++++++++++++++++
 1 file changed, 16 insertions(+)

diff --git a/CHANGES b/CHANGES
index 221c91be1..e16d7091b 100644
--- a/CHANGES
+++ b/CHANGES
@@ -1,3 +1,19 @@
+[> 2020.XX, planned for July 2020
+---------------------------------
+
+	[> Issues resolved
+	------------------
+	- NA
+
+	[> Added Features
+	------------------
+	- Pluggable CPUs.
+
+	[> API changes/Deprecation
+	--------------------------
+	- NA
+
+
 [> 2020.04, released April 28th, 2020
 -------------------------------------
 

From e4a4659d4d75f82304ed2847748f33b534fc84a7 Mon Sep 17 00:00:00 2001
From: Florent Kermarrec <florent@enjoy-digital.fr>
Date: Fri, 1 May 2020 19:09:32 +0200
Subject: [PATCH 58/95] litex_setup: add nmigen dependency (used to generate
 Minerva CPU).

This also requires Yosys, but Yosys is already expected to be installed separately.
---
 litex_setup.py | 1 +
 1 file changed, 1 insertion(+)

diff --git a/litex_setup.py b/litex_setup.py
index f2502abc0..b0ef1f137 100755
--- a/litex_setup.py
+++ b/litex_setup.py
@@ -17,6 +17,7 @@ current_path = os.path.abspath(os.curdir)
 repos = [
     # HDL
     ("migen",        ("https://github.com/m-labs/",        True,  True)),
+    ("nmigen",       ("https://github.com/nmigen/",        True,  True)),
 
     # LiteX SoC builder
     ("pythondata-software-compiler_rt", ("https://github.com/litex-hub/",     False, True)),

From bd8a4100477a8026baa0f104f6685dde4f47f42c Mon Sep 17 00:00:00 2001
From: Florent Kermarrec <florent@enjoy-digital.fr>
Date: Fri, 1 May 2020 20:12:02 +0200
Subject: [PATCH 59/95] cpu/minerva: add pythondata and use it to compile the
 sources.

---
 litex/soc/cores/cpu/minerva/core.py | 5 +++--
 litex_setup.py                      | 1 +
 2 files changed, 4 insertions(+), 2 deletions(-)

diff --git a/litex/soc/cores/cpu/minerva/core.py b/litex/soc/cores/cpu/minerva/core.py
index a4b63e629..b703f2f13 100644
--- a/litex/soc/cores/cpu/minerva/core.py
+++ b/litex/soc/cores/cpu/minerva/core.py
@@ -7,6 +7,7 @@ import subprocess
 
 from migen import *
 
+from litex import get_data_mod
 from litex.soc.interconnect import wishbone
 from litex.soc.cores.cpu import CPU
 
@@ -98,8 +99,8 @@ class Minerva(CPU):
             cli_params.append("--with-dcache")
         if with_muldiv:
             cli_params.append("--with-muldiv")
-        os.system("git clone http://github.com/lambdaconcept/minerva") # FIXME: create pythondata.
-        if subprocess.call(["python3", os.path.join("minerva", "cli.py"), *cli_params, "generate"],
+        sdir = get_data_mod("cpu", "minerva").data_location
+        if subprocess.call(["python3", os.path.join(sdir, "cli.py"), *cli_params, "generate"],
             stdout=open(verilog_filename, "w")):
             raise OSError("Unable to elaborate Minerva CPU, please check your nMigen/Yosys install")
 
diff --git a/litex_setup.py b/litex_setup.py
index b0ef1f137..f6d6b3937 100755
--- a/litex_setup.py
+++ b/litex_setup.py
@@ -46,6 +46,7 @@ repos = [
     ("pythondata-cpu-serv",        ("https://github.com/litex-hub/", False, True)),
     ("pythondata-cpu-vexriscv",    ("https://github.com/litex-hub/", False, True)),
     ("pythondata-cpu-rocket",      ("https://github.com/litex-hub/", False, True)),
+    ("pythondata-cpu-minerva",     ("https://github.com/litex-hub/", False, True)),
 ]
 
 repos = OrderedDict(repos)

From 10371a33f901515600f5c909e947615ff35ad587 Mon Sep 17 00:00:00 2001
From: Florent Kermarrec <florent@enjoy-digital.fr>
Date: Fri, 1 May 2020 20:13:05 +0200
Subject: [PATCH 60/95] CHANGES: update.

---
 CHANGES | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/CHANGES b/CHANGES
index e16d7091b..64bd257e0 100644
--- a/CHANGES
+++ b/CHANGES
@@ -8,6 +8,8 @@
 	[> Added Features
 	------------------
 	- Pluggable CPUs.
+	- Add nMigen dependency.
+	- Properly integrate Minerva CPU.
 
 	[> API changes/Deprecation
 	--------------------------

From b5978b214dee35cd184ab731eaa98471a3d18317 Mon Sep 17 00:00:00 2001
From: Florent Kermarrec <florent@enjoy-digital.fr>
Date: Fri, 1 May 2020 21:13:12 +0200
Subject: [PATCH 61/95] .travis.yml: disable python3.5 test (nMigen requires
 3.6+).

As discussed in #479.
---
 .travis.yml | 4 ----
 1 file changed, 4 deletions(-)

diff --git a/.travis.yml b/.travis.yml
index f461f48c9..8f491ae73 100644
--- a/.travis.yml
+++ b/.travis.yml
@@ -1,9 +1,5 @@
 jobs:
   include:
-    - os: linux
-      dist: xenial
-      language: python
-      python: "3.5"
     - os: linux
       dist: xenial
       language: python

From 74140587c8ab4283a4e474d0ce505bfe79c0064e Mon Sep 17 00:00:00 2001
From: Sadullah Canakci <sadullahcanakci@gmail.com>
Date: Tue, 10 Mar 2020 16:47:26 -0400
Subject: [PATCH 62/95] Create GETTING STARTED

Rename GETTING STARTED to GETTING STARTED.md

Update GETTING STARTED.md

Update GETTING STARTED.md

Update GETTING STARTED.md
---
 .../cores/cpu/blackparrot/GETTING STARTED.md  | 23 +++++++++++++++++++
 1 file changed, 23 insertions(+)
 create mode 100644 litex/soc/cores/cpu/blackparrot/GETTING STARTED.md

diff --git a/litex/soc/cores/cpu/blackparrot/GETTING STARTED.md b/litex/soc/cores/cpu/blackparrot/GETTING STARTED.md
new file mode 100644
index 000000000..47ea73734
--- /dev/null
+++ b/litex/soc/cores/cpu/blackparrot/GETTING STARTED.md	
@@ -0,0 +1,23 @@
+# Getting started
+
+## Running BP in LiteX
+
+cd $LITEX/litex/tools  # the folder where litex simulator resides
+
+./litex_sim.py --cpu-type blackparrot --cpu-variant standard --integrated-rom-size 40960 --output-dir build/BP --threads 4 --opt-level=O0 --trace --trace-start 0
+
+#The above command will generate a dut.vcd file under build/BP/gateware folder. gtkwave works fine with the generated dut.vcd.
+
+## Additional Information
+
+The BlackParrot resides in $BP/pre-alpha-release/
+
+core.py in $BP folder is the wrapper that integrates BP into LiteX.
+
+flist.verilator in $BP is all the files that litex_sim fetches for simulation.
+
+The top module is $BP_FPGA_DIR/ExampleBlackParrotSystem.v
+
+The transducer for wishbone communication is $BP_FPGA_DIR/bp2wb_convertor.v
+
+  

From b7b9a1f0fb6086a2141042896e4713159c7c0362 Mon Sep 17 00:00:00 2001
From: sadullah <sadullahcanakci@gmail.com>
Date: Mon, 27 Apr 2020 23:03:36 -0400
Subject: [PATCH 63/95] Linux works, LiteDRAM works (need cleaning, temporary
 push)

---
 litex/boards/targets/genesys2.py              |  3 +-
 .../bp_fpga/ExampleBlackParrotSystem.v        |  4 +-
 litex/soc/cores/cpu/blackparrot/core.py       | 66 +++++++++----------
 .../cpu/blackparrot/flist_litex.verilator     |  5 +-
 .../cores/cpu/blackparrot/setEnvironment.sh   |  3 +-
 litex/soc/software/bios/Makefile              |  2 +-
 litex/soc/software/bios/boot.c                | 11 ++++
 litex/soc/software/bios/sdram.c               |  2 +-
 litex/soc/software/include/base/ctype.h       |  6 +-
 litex/soc/software/libbase/libc.c             |  7 +-
 litex/soc/software/libnet/tftp.c              | 10 ++-
 litex/tools/litex_sim.py                      |  3 +-
 12 files changed, 76 insertions(+), 46 deletions(-)

diff --git a/litex/boards/targets/genesys2.py b/litex/boards/targets/genesys2.py
index d97b68a36..6b9c2c9c5 100755
--- a/litex/boards/targets/genesys2.py
+++ b/litex/boards/targets/genesys2.py
@@ -46,10 +46,11 @@ class BaseSoC(SoCCore):
 
         # SoCCore ----------------------------------------------------------------------------------
         SoCCore.__init__(self, platform, clk_freq=sys_clk_freq, **kwargs)
+        sys_clk_freq = int(50e6)
 
         # CRG --------------------------------------------------------------------------------------
         self.submodules.crg = _CRG(platform, sys_clk_freq)
-
+        self.add_constant("UART_POLLING",None)
         # DDR3 SDRAM -------------------------------------------------------------------------------
         if not self.integrated_main_ram_size:
             self.submodules.ddrphy = s7ddrphy.K7DDRPHY(platform.request("ddram"),
diff --git a/litex/soc/cores/cpu/blackparrot/bp_fpga/ExampleBlackParrotSystem.v b/litex/soc/cores/cpu/blackparrot/bp_fpga/ExampleBlackParrotSystem.v
index cdd1a95e0..9eb86cb58 100644
--- a/litex/soc/cores/cpu/blackparrot/bp_fpga/ExampleBlackParrotSystem.v
+++ b/litex/soc/cores/cpu/blackparrot/bp_fpga/ExampleBlackParrotSystem.v
@@ -171,7 +171,7 @@ bp_chip
        );
 
 
-  bind bp_be_top
+/*  bind bp_be_top
     bp_be_nonsynth_tracer
      #(.cfg_p(cfg_p))
      tracer
@@ -207,7 +207,7 @@ bp_chip
        ,.priv_mode_i(be_mem.csr.priv_mode_n)
        ,.mpp_i(be_mem.csr.mstatus_n.mpp)
        );
-
+*/
 /*bind bp_be_top
   bp_be_nonsynth_perf
    #(.cfg_p(cfg_p))
diff --git a/litex/soc/cores/cpu/blackparrot/core.py b/litex/soc/cores/cpu/blackparrot/core.py
index e9ad41643..ccce090c2 100644
--- a/litex/soc/cores/cpu/blackparrot/core.py
+++ b/litex/soc/cores/cpu/blackparrot/core.py
@@ -40,9 +40,9 @@ from litex.soc.cores.cpu import CPU
 CPU_VARIANTS = {
     "standard": "freechips.rocketchip.system.LitexConfig",
 }
-
+# -mcmodel=medany
 GCC_FLAGS = {
-    "standard": "-march=rv64ia   -mabi=lp64 -O0 ",
+    "standard": "-march=rv64ia -mabi=lp64 -O0  ",
 }
 
 class BlackParrotRV64(CPU):
@@ -52,15 +52,15 @@ class BlackParrotRV64(CPU):
     gcc_triple           = ("riscv64-unknown-elf", "riscv64-linux", "riscv-sifive-elf",
                             "riscv64-none-elf")
     linker_output_format = "elf64-littleriscv"
-    io_regions           = {0x30000000: 0x20000000} # origin, length
-
+    io_regions           = {0x50000000: 0x10000000} # origin, length
+   
     @property
     def mem_map(self):
         return {
-            "ethmac"   : 0x30000000,
-            "csr"      : 0x40000000,
-            "rom"      : 0x50000000,
-            "sram"     : 0x51000000,
+            "csr"      : 0x50000000,
+#            "ethmac"   : 0x55000000,
+            "rom"      : 0x70000000,
+            "sram"     : 0x71000000,
             "main_ram" : 0x80000000,
         }
 
@@ -81,33 +81,33 @@ class BlackParrotRV64(CPU):
         self.idbus        = idbus = wishbone.Interface(data_width=64, adr_width=37)
         self.periph_buses = [idbus]
         self.memory_buses = []
-
-        # # #
+        self.buses     = [wbn]
 
         self.cpu_params = dict(
             # clock, reset
-            i_clk_i      = ClockSignal(),
-            i_reset_i    = ResetSignal() | self.reset,
+            i_clk_i = ClockSignal(),
+            i_reset_i = ResetSignal() | self.reset,
+            
+            # irq           
+            #i_interrupts = self.interrupt,
+            
+            #wishbone
+            i_wbm_dat_i = wbn.dat_r,
+            o_wbm_dat_o = wbn.dat_w,
+            i_wbm_ack_i = wbn.ack,
+            i_wbm_err_i = wbn.err,
+            #i_wbm_rty_i = 0,
+            o_wbm_adr_o = wbn.adr,
+            o_wbm_stb_o = wbn.stb,
+            o_wbm_cyc_o = wbn.cyc,
+            o_wbm_sel_o = wbn.sel,
+            o_wbm_we_o = wbn.we,
+            o_wbm_cti_o = wbn.cti,
+            o_wbm_bte_o = wbn.bte,
 
-            # irq
-            i_interrupts = self.interrupt,
-
-            # wishbone
-            i_wbm_dat_i  = idbus.dat_r,
-            o_wbm_dat_o  = idbus.dat_w,
-            i_wbm_ack_i  = idbus.ack,
-            i_wbm_err_i  = 0,
-            i_wbm_rty_i  = 0,
-            o_wbm_adr_o  = idbus.adr,
-            o_wbm_stb_o  = idbus.stb,
-            o_wbm_cyc_o  = idbus.cyc,
-            o_wbm_sel_o  = idbus.sel,
-            o_wbm_we_o   = idbus.we,
-            o_wbm_cti_o  = idbus.cti,
-            o_wbm_bte_o  = idbus.bte,
-        )
-
-        # add verilog sources
+            )
+     
+           # add verilog sources
         self.add_sources(platform, variant)
 
     def set_reset_address(self, reset_address):
@@ -131,7 +131,7 @@ class BlackParrotRV64(CPU):
                     a = os.popen('echo '+ str(dir_))
                     dir_start = a.read()
                     vdir = dir_start[:-1] + line[s2:-1]
-                    print("INCDIR" + vdir)
+                    #print("INCDIR" + vdir)
                     platform.add_verilog_include_path(vdir)  #this line might be changed
                 elif (temp[0]=='$') :
                     s2 = line.find('/')
@@ -139,7 +139,7 @@ class BlackParrotRV64(CPU):
                     a = os.popen('echo '+ str(dir_))
                     dir_start = a.read()
                     vdir = dir_start[:-1]+ line[s2:-1]
-                    print(vdir)
+                    #print(vdir)
                     platform.add_source(vdir) #this line might be changed
                 elif (temp[0] == '/'):
                     assert("No support for absolute path for now")
diff --git a/litex/soc/cores/cpu/blackparrot/flist_litex.verilator b/litex/soc/cores/cpu/blackparrot/flist_litex.verilator
index 65e8e1c4e..ba656dc14 100644
--- a/litex/soc/cores/cpu/blackparrot/flist_litex.verilator
+++ b/litex/soc/cores/cpu/blackparrot/flist_litex.verilator
@@ -203,7 +203,7 @@ $BP_COMMON_DIR/src/v/bp_addr_map.v
 // bsg_ip_cores files
 $BASEJUMP_STL_DIR/bsg_fsb/bsg_fsb_node_trace_replay.v
 // be files
-$BP_BE_DIR/test/common/bp_be_nonsynth_tracer.v
+//$BP_BE_DIR/test/common/bp_be_nonsynth_tracer.v
 // $BP_BE_DIR/test/common/bp_be_nonsynth_perf.v
 // me files
 // $BP_ME_DIR/test/common/bp_mem.v
@@ -218,9 +218,10 @@ $BP_ME_DIR/test/common/bp_cce_mmio_cfg_loader.v
 // top files
 $BP_TOP_DIR/test/common/bp_nonsynth_host.v
 // $BP_TOP_DIR/test/common/bp_nonsynth_if_verif.v
-$BP_TOP_DIR/test/common/bp_nonsynth_commit_tracer.v
+//$BP_TOP_DIR/test/common/bp_nonsynth_commit_tracer.v
 // /home/scanakci/Research_sado/litex/litex/litex/soc/cores/cpu/blackparrot/pre-alpha-release/bp_top/syn/results/verilator/bp_top_trace_demo.e_bp_single_core_cfg.build/wrapper.v
 // /home/scanakci/Research_sado/litex/litex/litex/soc/cores/cpu/blackparrot/pre-alpha-release/bp_top/syn/results/verilator/bp_top_trace_demo.e_bp_single_core_cfg.build/test_bp.cpp
+$BP_TOP_DIR/test/common/bp_monitor.cpp
 $BP_FPGA_DIR/bp2wb_convertor.v
 $BP_FPGA_DIR/ExampleBlackParrotSystem.v
 $BP_FPGA_DIR/bsg_mem_1rw_sync_mask_write_bit.v
diff --git a/litex/soc/cores/cpu/blackparrot/setEnvironment.sh b/litex/soc/cores/cpu/blackparrot/setEnvironment.sh
index d818ec52b..079bb17f7 100755
--- a/litex/soc/cores/cpu/blackparrot/setEnvironment.sh
+++ b/litex/soc/cores/cpu/blackparrot/setEnvironment.sh
@@ -38,7 +38,8 @@ export SYSTEMC_INCLUDE=$BP_EXTERNAL_DIR/include
 export SYSTEMC_LIBDIR=$BP_EXTERNAL_DIR/lib-linux64
 
 ## Add external tools and libraries to environment
-export LD_LIBRARY_PATH=$SYSTEMC_LIBDIR:$LD_LIBRARY_PATH
+export LD_LIBRARY_PATH=$SYSTEMC_LIBDIR
+#:$LD_LIBRARY_PATH
 #export PATH=$(BP_EXTERNAL_DIR)/bin:$(PATH)
 #export SYN_PATH=$(BP_TOP_DIR)/syn
 #export TB_PATH=$(BP_TOP_DIR)/test/tb
diff --git a/litex/soc/software/bios/Makefile b/litex/soc/software/bios/Makefile
index cc3b973aa..98dc44d52 100755
--- a/litex/soc/software/bios/Makefile
+++ b/litex/soc/software/bios/Makefile
@@ -2,7 +2,7 @@ include ../include/generated/variables.mak
 include $(SOC_DIRECTORY)/software/common.mak
 
 ifeq ($(CPU),blackparrot)
-BP_LIBS  = -L$(BP_EXTERNAL_DIR)/lib/gcc/riscv64-unknown-elf/8.3.0
+BP_LIBS =  -L$(BP_EXTERNAL_DIR)/lib/gcc/riscv64-unknown-elf/9.2.0/ 
 BP_FLAGS = -lgcc
 endif
 # Permit TFTP_SERVER_PORT override from shell environment / command line
diff --git a/litex/soc/software/bios/boot.c b/litex/soc/software/bios/boot.c
index 08b3be4a8..274cd789f 100644
--- a/litex/soc/software/bios/boot.c
+++ b/litex/soc/software/bios/boot.c
@@ -32,6 +32,8 @@
 #include "sfl.h"
 #include "boot.h"
 
+#define MEMTEST_DATA_SIZE2 (589824*4)
+
 extern void boot_helper(unsigned long r1, unsigned long r2, unsigned long r3, unsigned long addr);
 
 static void __attribute__((noreturn)) boot(unsigned long r1, unsigned long r2, unsigned long r3, unsigned long addr)
@@ -59,7 +61,16 @@ static void __attribute__((noreturn)) boot(unsigned long r1, unsigned long r2, u
 	mtspr(SPR_EVBAR, addr);
 	addr += 0x100;
 #endif
+          
 
+/*        volatile unsigned int *array = (unsigned int *)MAIN_RAM_BASE;
+        int i;
+        unsigned int rdata;
+        for(i=0;i<MEMTEST_DATA_SIZE2/4;i++) {
+                rdata = array[i];
+                printf("[data 0x%0x]: 0x%08x\n",i,rdata);
+         }
+*/
 	boot_helper(r1, r2, r3, addr);
 	while(1);
 }
diff --git a/litex/soc/software/bios/sdram.c b/litex/soc/software/bios/sdram.c
index 513a12665..7798d3013 100644
--- a/litex/soc/software/bios/sdram.c
+++ b/litex/soc/software/bios/sdram.c
@@ -1005,7 +1005,7 @@ int memtest(void)
 		return 0;
 	else {
 		printf("Memtest OK\n");
-		memspeed();
+		//memspeed();
 		return 1;
 	}
 }
diff --git a/litex/soc/software/include/base/ctype.h b/litex/soc/software/include/base/ctype.h
index 693685933..7542e4402 100644
--- a/litex/soc/software/include/base/ctype.h
+++ b/litex/soc/software/include/base/ctype.h
@@ -26,7 +26,11 @@ extern const unsigned char _ctype[];
 #define isalnum(c)	((__ismask(c)&(_U|_L|_D)) != 0)
 #define isalpha(c)	((__ismask(c)&(_U|_L)) != 0)
 #define iscntrl(c)	((__ismask(c)&(_C)) != 0)
-#define isdigit(c)	((__ismask(c)&(_D)) != 0)
+//#define isdigit(c)	((__ismask(c)&(_D)) != 0)
+static int isdigit(char c){
+  if ((c>='0') && (c<='9')) return 1;
+    return 0;
+}
 #define isgraph(c)	((__ismask(c)&(_P|_U|_L|_D)) != 0)
 #define islower(c)	((__ismask(c)&(_L)) != 0)
 #define isprint(c)	((__ismask(c)&(_P|_U|_L|_D|_SP)) != 0)
diff --git a/litex/soc/software/libbase/libc.c b/litex/soc/software/libbase/libc.c
index be48cf651..698ec59cc 100644
--- a/litex/soc/software/libbase/libc.c
+++ b/litex/soc/software/libbase/libc.c
@@ -23,7 +23,7 @@
 #include <string.h>
 #include <limits.h>
 #include <inet.h>
-
+#include <errno.h>
 /**
  * strchr - Find the first occurrence of a character in a string
  * @s: The string to be searched
@@ -375,7 +375,7 @@ void *memchr(const void *s, int c, size_t n)
  * @base: The number base to use
  */
 unsigned long strtoul(const char *nptr, char **endptr, int base)
-{
+{       printf("HI\n");
 	unsigned long result = 0,value;
 
 	if (!base) {
@@ -392,11 +392,14 @@ unsigned long strtoul(const char *nptr, char **endptr, int base)
 		if (nptr[0] == '0' && toupper(nptr[1]) == 'X')
 			nptr += 2;
 	}
+        printf("HI2\n");
 	while (isxdigit(*nptr) &&
 	       (value = isdigit(*nptr) ? *nptr-'0' : toupper(*nptr)-'A'+10) < base) {
 		result = result*base + value;
 		nptr++;
+                printf("HI4\n");
 	}
+        printf("HI3\n");
 	if (endptr)
 		*endptr = (char *)nptr;
 	return result;
diff --git a/litex/soc/software/libnet/tftp.c b/litex/soc/software/libnet/tftp.c
index 439b3e075..d51107388 100644
--- a/litex/soc/software/libnet/tftp.c
+++ b/litex/soc/software/libnet/tftp.c
@@ -117,10 +117,11 @@ int tftp_get(uint32_t ip, uint16_t server_port, const char *filename,
 	int i;
 	int length_before;
 	int spin = 0;
+        printf("DEBUGWTH?\n");
 
 	if(!microudp_arp_resolve(ip))
 		return -1;
-
+        printf("DEBUG0\n");
 	microudp_set_callback(rx_callback);
 
 	dst_buffer = buffer;
@@ -129,6 +130,8 @@ int tftp_get(uint32_t ip, uint16_t server_port, const char *filename,
 	transfer_finished = 0;
 	tries = 5;
 	while(1) {
+                
+                printf("DEBUG1\n");
 		packet_data = microudp_get_tx_buffer();
 		len = format_request(packet_data, TFTP_RRQ, filename);
 		microudp_send(PORT_IN, server_port, len);
@@ -136,6 +139,8 @@ int tftp_get(uint32_t ip, uint16_t server_port, const char *filename,
 			microudp_service();
 			if((total_length > 0) || transfer_finished) break;
 		}
+
+                printf("DEBUG2\n");
 		if((total_length > 0) || transfer_finished) break;
 		tries--;
 		if(tries == 0) {
@@ -144,6 +149,7 @@ int tftp_get(uint32_t ip, uint16_t server_port, const char *filename,
 		}
 	}
 
+        printf("DEBUG3\n");
 	i = 12000000;
 	length_before = total_length;
 	while(!transfer_finished) {
@@ -162,8 +168,10 @@ int tftp_get(uint32_t ip, uint16_t server_port, const char *filename,
 		microudp_service();
 	}
 
+        printf("DEBUG4\n");
 	microudp_set_callback(NULL);
 
+        printf("DEBUG5\n");
 	return total_length;
 }
 
diff --git a/litex/tools/litex_sim.py b/litex/tools/litex_sim.py
index 987681d33..ebba204bd 100755
--- a/litex/tools/litex_sim.py
+++ b/litex/tools/litex_sim.py
@@ -177,6 +177,7 @@ class SimSoC(SoCSDRAM):
             ident               = "LiteX Simulation", ident_version=True,
             l2_reverse          = False,
             **kwargs)
+        self.add_constant("UART_POLLING",None)
         # CRG --------------------------------------------------------------------------------------
         self.submodules.crg = CRG(platform.request("sys_clk"))
 
@@ -353,7 +354,7 @@ def main():
         sdram_init     = [] if args.sdram_init is None else get_mem_data(args.sdram_init, cpu_endianness),
         **soc_kwargs)
     if args.ram_init is not None:
-        soc.add_constant("ROM_BOOT_ADDRESS", 0x40000000)
+        soc.add_constant("ROM_BOOT_ADDRESS", 0x80000000)
     if args.with_ethernet:
         for i in range(4):
             soc.add_constant("LOCALIP{}".format(i+1), int(args.local_ip.split(".")[i]))

From cf01ea65f308f58f82da40d43cd40d8baae39a34 Mon Sep 17 00:00:00 2001
From: sadullah <sadullahcanakci@gmail.com>
Date: Mon, 27 Apr 2020 23:56:51 -0400
Subject: [PATCH 64/95] rebased, minor changes in core.py

---
 litex/soc/cores/cpu/blackparrot/core.py | 27 +++++++++++++------------
 1 file changed, 14 insertions(+), 13 deletions(-)

diff --git a/litex/soc/cores/cpu/blackparrot/core.py b/litex/soc/cores/cpu/blackparrot/core.py
index ccce090c2..ab4db8ad5 100644
--- a/litex/soc/cores/cpu/blackparrot/core.py
+++ b/litex/soc/cores/cpu/blackparrot/core.py
@@ -81,7 +81,7 @@ class BlackParrotRV64(CPU):
         self.idbus        = idbus = wishbone.Interface(data_width=64, adr_width=37)
         self.periph_buses = [idbus]
         self.memory_buses = []
-        self.buses     = [wbn]
+#        self.buses     = [wbn]
 
         self.cpu_params = dict(
             # clock, reset
@@ -92,18 +92,18 @@ class BlackParrotRV64(CPU):
             #i_interrupts = self.interrupt,
             
             #wishbone
-            i_wbm_dat_i = wbn.dat_r,
-            o_wbm_dat_o = wbn.dat_w,
-            i_wbm_ack_i = wbn.ack,
-            i_wbm_err_i = wbn.err,
+            i_wbm_dat_i = idbus.dat_r,
+            o_wbm_dat_o = idbus.dat_w,
+            i_wbm_ack_i = idbus.ack,
+            i_wbm_err_i = idbus.err,
             #i_wbm_rty_i = 0,
-            o_wbm_adr_o = wbn.adr,
-            o_wbm_stb_o = wbn.stb,
-            o_wbm_cyc_o = wbn.cyc,
-            o_wbm_sel_o = wbn.sel,
-            o_wbm_we_o = wbn.we,
-            o_wbm_cti_o = wbn.cti,
-            o_wbm_bte_o = wbn.bte,
+            o_wbm_adr_o = idbus.adr,
+            o_wbm_stb_o = idbus.stb,
+            o_wbm_cyc_o = idbus.cyc,
+            o_wbm_sel_o = idbus.sel,
+            o_wbm_we_o = idbus.we,
+            o_wbm_cti_o = idbus.cti,
+            o_wbm_bte_o = idbus.bte,
 
             )
      
@@ -113,7 +113,8 @@ class BlackParrotRV64(CPU):
     def set_reset_address(self, reset_address):
         assert not hasattr(self, "reset_address")
         self.reset_address = reset_address
-        assert reset_address == 0x00000000, "cpu_reset_addr hardcoded to 0x00000000!"
+        #FIXME: set reset addr to 0x70000000
+        #assert reset_address == 0x00000000, "cpu_reset_addr hardcoded to 0x00000000!"
 
     @staticmethod
     def add_sources(platform, variant="standard"):

From bf864d335b267b6ac83aed8acae405959936b7d4 Mon Sep 17 00:00:00 2001
From: sadullah <sadullahcanakci@gmail.com>
Date: Thu, 30 Apr 2020 22:39:05 -0400
Subject: [PATCH 65/95] Fix memory transducer bug, --with-sdram for BIOS works,
 memspeed works

---
 litex/boards/targets/genesys2.py              |   4 +-
 .../bp_fpga/ExampleBlackParrotSystem.v        | 434 ------------------
 .../cpu/blackparrot/bp_fpga/bp2wb_convertor.v | 191 +++++---
 litex/soc/cores/cpu/blackparrot/core.py       |  11 +-
 litex/soc/cores/cpu/blackparrot/crt0.S        |   2 +-
 litex/soc/software/bios/isr.c                 |   4 +-
 litex/soc/software/bios/sdram.c               |   2 +-
 litex/tools/litex_sim.py                      |   4 +-
 8 files changed, 139 insertions(+), 513 deletions(-)
 delete mode 100644 litex/soc/cores/cpu/blackparrot/bp_fpga/ExampleBlackParrotSystem.v

diff --git a/litex/boards/targets/genesys2.py b/litex/boards/targets/genesys2.py
index 6b9c2c9c5..52023e535 100755
--- a/litex/boards/targets/genesys2.py
+++ b/litex/boards/targets/genesys2.py
@@ -46,11 +46,11 @@ class BaseSoC(SoCCore):
 
         # SoCCore ----------------------------------------------------------------------------------
         SoCCore.__init__(self, platform, clk_freq=sys_clk_freq, **kwargs)
-        sys_clk_freq = int(50e6)
+#        sys_clk_freq = int(50e6)
 
         # CRG --------------------------------------------------------------------------------------
         self.submodules.crg = _CRG(platform, sys_clk_freq)
-        self.add_constant("UART_POLLING",None)
+#        self.add_constant("UART_POLLING",None)
         # DDR3 SDRAM -------------------------------------------------------------------------------
         if not self.integrated_main_ram_size:
             self.submodules.ddrphy = s7ddrphy.K7DDRPHY(platform.request("ddram"),
diff --git a/litex/soc/cores/cpu/blackparrot/bp_fpga/ExampleBlackParrotSystem.v b/litex/soc/cores/cpu/blackparrot/bp_fpga/ExampleBlackParrotSystem.v
deleted file mode 100644
index 9eb86cb58..000000000
--- a/litex/soc/cores/cpu/blackparrot/bp_fpga/ExampleBlackParrotSystem.v
+++ /dev/null
@@ -1,434 +0,0 @@
-/**
-  *
-  * ExampleBlackParrotSystem For Simulating With Litex
-  *
-  */
-  
-`include "bsg_noc_links.vh"
-
-module ExampleBlackParrotSystem
- import bp_common_pkg::*;
- import bp_common_aviary_pkg::*;
- import bp_be_pkg::*;
- import bp_common_rv64_pkg::*;
- import bp_cce_pkg::*;
- import bp_cfg_link_pkg::*;
- #(parameter bp_cfg_e cfg_p = e_bp_single_core_cfg // Replaced by the flow with a specific bp_cfg
-   `declare_bp_proc_params(cfg_p)
-   `declare_bp_me_if_widths(paddr_width_p, cce_block_width_p, num_lce_p, lce_assoc_p)
-
-   // Tracing parameters
-   , parameter calc_trace_p                = 1
-   , parameter cce_trace_p                 = 0
-   , parameter cmt_trace_p                 = 0
-   , parameter dram_trace_p                = 0
-   , parameter skip_init_p                 = 0
-
-   , parameter mem_load_p         = 1
-   , parameter mem_file_p         = "prog.mem"
-   , parameter mem_cap_in_bytes_p = 2**20
-   , parameter [paddr_width_p-1:0] mem_offset_p = paddr_width_p'(32'h8000_0000)
-
-   )
-  (input clk_i
-   , input reset_i
-   //Wishbone interface 
-   , input  [63:0]  wbm_dat_i
-   , output [63:0]  wbm_dat_o
-   , input          wbm_ack_i
-  // , input          wbm_err_i
-  // , input          wbm_rty_i
-   , output [36:0]  wbm_adr_o //TODO parametrize this
-   , output         wbm_stb_o
-   , output         wbm_cyc_o
-   , output         wbm_sel_o //TODO: how many bits ? check 3.5 table 3-1
-   , output         wbm_we_o
-   , output [2:0]   wbm_cti_o //TODO: hardwire in Litex
-   , output [1:0]   wbm_bte_o //TODO: hardwire in Litex
-   , output         all_finished_debug_o //SC_add
-   , output         core_passed_debug
-   , output         core_failed_debug
-   , input  [3:0]   interrupts 
-  );
-
-`declare_bsg_ready_and_link_sif_s(mem_noc_flit_width_p, bsg_ready_and_link_sif_s);
-`declare_bp_me_if(paddr_width_p, cce_block_width_p, num_lce_p, lce_assoc_p)
-
-bsg_ready_and_link_sif_s cmd_link_li, cmd_link_lo;
-bsg_ready_and_link_sif_s resp_link_li, resp_link_lo;
-
-bsg_ready_and_link_sif_s mem_cmd_link_li, mem_cmd_link_lo, mem_resp_link_li, mem_resp_link_lo;
-bsg_ready_and_link_sif_s cfg_cmd_link_li, cfg_cmd_link_lo, cfg_resp_link_li, cfg_resp_link_lo;
-
-assign mem_cmd_link_li = cmd_link_li;
-assign cfg_cmd_link_li = '{ready_and_rev: cmd_link_li.ready_and_rev, default: '0};
-assign cmd_link_lo = '{data: cfg_cmd_link_lo.data
-                       ,v  : cfg_cmd_link_lo.v
-                       ,ready_and_rev: mem_cmd_link_lo.ready_and_rev
-                       };
-
-assign mem_resp_link_li = '{ready_and_rev: resp_link_li.ready_and_rev, default: '0};
-assign cfg_resp_link_li = resp_link_li;
-assign resp_link_lo = '{data: mem_resp_link_lo.data
-                        ,v  : mem_resp_link_lo.v
-                        ,ready_and_rev: cfg_resp_link_lo.ready_and_rev
-                        };
-
-bp_cce_mem_msg_s       mem_resp_li;
-logic                  mem_resp_v_li, mem_resp_ready_lo;
-bp_cce_mem_msg_s       mem_cmd_lo;
-logic                  mem_cmd_v_lo, mem_cmd_yumi_li;
-
-bp_cce_mem_msg_s       dram_resp_lo;
-logic                  dram_resp_v_lo, dram_resp_ready_li;
-bp_cce_mem_msg_s       dram_cmd_li;
-logic                  dram_cmd_v_li, dram_cmd_yumi_lo;
-
-bp_cce_mem_msg_s       host_resp_lo;
-logic                  host_resp_v_lo, host_resp_ready_li;
-bp_cce_mem_msg_s       host_cmd_li;
-logic                  host_cmd_v_li, host_cmd_yumi_lo;
-
-bp_cce_mem_msg_s       cfg_cmd_lo;
-logic                  cfg_cmd_v_lo, cfg_cmd_ready_li;
-bp_cce_mem_msg_s       cfg_resp_li;
-logic                  cfg_resp_v_li, cfg_resp_ready_lo;
-
-logic [mem_noc_cord_width_p-1:0] dram_cord_lo, mmio_cord_lo, host_cord_lo;
-logic [num_core_p-1:0][mem_noc_cord_width_p-1:0] tile_cord_lo;
-logic [num_mem_p-1:0][mem_noc_cord_width_p-1:0] mem_cord_lo;
-
-assign mmio_cord_lo[0+:mem_noc_x_cord_width_p]                      = mmio_x_pos_p;
-assign mmio_cord_lo[mem_noc_x_cord_width_p+:mem_noc_y_cord_width_p] = '0;
-assign dram_cord_lo[0+:mem_noc_x_cord_width_p]                      = mem_noc_x_dim_p+2;
-assign dram_cord_lo[mem_noc_x_cord_width_p+:mem_noc_y_cord_width_p] = '0;
-assign host_cord_lo[0+:mem_noc_x_cord_width_p]                      = mem_noc_x_dim_p+2;
-assign host_cord_lo[mem_noc_x_cord_width_p+:mem_noc_y_cord_width_p] = '0;
-
-for (genvar j = 0; j < mem_noc_y_dim_p; j++)
-  begin : y
-    for (genvar i = 0; i < mem_noc_x_dim_p; i++)
-      begin : x
-        localparam idx = j*mem_noc_x_dim_p + i;
-        assign tile_cord_lo[idx][0+:mem_noc_x_cord_width_p] = i+1;
-        assign tile_cord_lo[idx][mem_noc_x_cord_width_p+:mem_noc_y_cord_width_p] = j+1;
-      end
-  end
-for (genvar i = 0; i < num_mem_p; i++)
-  begin : x
-    assign mem_cord_lo[i][0+:mem_noc_x_cord_width_p] = i;
-    assign mem_cord_lo[i][mem_noc_x_cord_width_p+:mem_noc_y_cord_width_p] = '0;
-  end
-
-// Chip
-bp_chip
- #(.cfg_p(cfg_p))
- chip
-  (.core_clk_i(clk_i)
-   ,.core_reset_i(reset_i)
-   
-   ,.coh_clk_i(clk_i)
-   ,.coh_reset_i(reset_i)
-
-   ,.mem_clk_i(clk_i)
-   ,.mem_reset_i(reset_i)
-
-   ,.mem_cord_i(mem_cord_lo)
-   ,.tile_cord_i(tile_cord_lo)
-   ,.dram_cord_i(dram_cord_lo)
-   ,.mmio_cord_i(mmio_cord_lo)
-   ,.host_cord_i(host_cord_lo)
-
-   ,.prev_cmd_link_i('0)
-   ,.prev_cmd_link_o()
-
-   ,.prev_resp_link_i('0)
-   ,.prev_resp_link_o()
-
-   ,.next_cmd_link_i(cmd_link_lo)
-   ,.next_cmd_link_o(cmd_link_li)
-
-   ,.next_resp_link_i(resp_link_lo)
-   ,.next_resp_link_o(resp_link_li)
-   );
-
-  bind bp_be_top
-    bp_nonsynth_commit_tracer
-     #(.cfg_p(cfg_p))
-     commit_tracer
-      (.clk_i(clk_i & (ExampleBlackParrotSystem.cmt_trace_p == 1))
-       ,.reset_i(reset_i)
-
-       ,.mhartid_i('0)
-
-       ,.commit_v_i(be_calculator.instret_mem3_o)
-       ,.commit_pc_i(be_calculator.pc_mem3_o)
-       ,.commit_instr_i(be_calculator.instr_mem3_o)
-
-       ,.rd_w_v_i(be_calculator.int_regfile.rd_w_v_i)
-       ,.rd_addr_i(be_calculator.int_regfile.rd_addr_i)
-       ,.rd_data_i(be_calculator.int_regfile.rd_data_i)
-       );
-
-
-/*  bind bp_be_top
-    bp_be_nonsynth_tracer
-     #(.cfg_p(cfg_p))
-     tracer
-       // Workaround for verilator binding by accident
-       // TODO: Figure out why tracing is always enabled
-      (.clk_i(clk_i & (ExampleBlackParrotSystem.calc_trace_p == 1))
-       ,.reset_i(reset_i)
-  
-       ,.mhartid_i(be_calculator.proc_cfg.core_id)
-
-       ,.issue_pkt_i(be_calculator.issue_pkt)
-       ,.issue_pkt_v_i(be_calculator.issue_pkt_v_i)
-  
-       ,.fe_nop_v_i(be_calculator.fe_nop_v)
-       ,.be_nop_v_i(be_calculator.be_nop_v)
-       ,.me_nop_v_i(be_calculator.me_nop_v)
-       ,.dispatch_pkt_i(be_calculator.dispatch_pkt)
-  
-       ,.ex1_br_tgt_i(be_calculator.calc_status.int1_br_tgt)
-       ,.ex1_btaken_i(be_calculator.calc_status.int1_btaken)
-       ,.iwb_result_i(be_calculator.comp_stage_n[3])
-       ,.fwb_result_i(be_calculator.comp_stage_n[4])
-  
-       ,.cmt_trace_exc_i(be_calculator.exc_stage_n[1+:5])
-  
-       ,.trap_v_i(be_mem.csr.trap_v_o)
-       ,.mtvec_i(be_mem.csr.mtvec_n)
-       ,.mtval_i(be_mem.csr.mtval_n[0+:vaddr_width_p])
-       ,.ret_v_i(be_mem.csr.ret_v_o)
-       ,.mepc_i(be_mem.csr.mepc_n[0+:vaddr_width_p])
-       ,.mcause_i(be_mem.csr.mcause_n)
-  
-       ,.priv_mode_i(be_mem.csr.priv_mode_n)
-       ,.mpp_i(be_mem.csr.mstatus_n.mpp)
-       );
-*/
-/*bind bp_be_top
-  bp_be_nonsynth_perf
-   #(.cfg_p(cfg_p))
-   perf
-    (.clk_i(clk_i)
-     ,.reset_i(reset_i)
-
-     ,.mhartid_i(be_calculator.proc_cfg.core_id)
-
-     ,.fe_nop_i(be_calculator.exc_stage_r[2].fe_nop_v)
-     ,.be_nop_i(be_calculator.exc_stage_r[2].be_nop_v)
-     ,.me_nop_i(be_calculator.exc_stage_r[2].me_nop_v)
-     ,.poison_i(be_calculator.exc_stage_r[2].poison_v)
-     ,.roll_i(be_calculator.exc_stage_r[2].roll_v)
-     ,.instr_cmt_i(be_calculator.calc_status.mem3_cmt_v)
-
-     ,.program_finish_i(testbench.program_finish)
-     );
-*/
-/*if (dram_trace_p)
-  bp_mem_nonsynth_tracer
-   #(.cfg_p(cfg_p))
-   bp_mem_tracer
-    (.clk_i(clk_i & (testbench.dram_trace_p == 1))
-     ,.reset_i(reset_i)
-
-     ,.mem_cmd_i(dram_cmd_li)
-     ,.mem_cmd_v_i(dram_cmd_v_li)
-     ,.mem_cmd_yumi_i(dram_cmd_yumi_lo)
-
-     ,.mem_resp_i(dram_resp_lo)
-     ,.mem_resp_v_i(dram_resp_v_lo)
-     ,.mem_resp_ready_i(dram_resp_ready_li)
-     );
-
-if (cce_trace_p)
-  bind bp_cce_top
-    bp_cce_nonsynth_tracer
-      #(.cfg_p(cfg_p))
-      bp_cce_tracer
-       (.clk_i(clk_i & (testbench.cce_trace_p == 1))
-        ,.reset_i(reset_i)
-  
-        ,.cce_id_i(cce_id_i)
-  
-        // To CCE
-        ,.lce_req_i(lce_req_to_cce)
-        ,.lce_req_v_i(lce_req_v_to_cce)
-        ,.lce_req_yumi_i(lce_req_yumi_from_cce)
-        ,.lce_resp_i(lce_resp_to_cce)
-        ,.lce_resp_v_i(lce_resp_v_to_cce)
-        ,.lce_resp_yumi_i(lce_resp_yumi_from_cce)
-  
-        // From CCE
-        ,.lce_cmd_i(lce_cmd_o)
-        ,.lce_cmd_v_i(lce_cmd_v_o)
-        ,.lce_cmd_ready_i(lce_cmd_ready_i)
-  
-        // To CCE
-        ,.mem_resp_i(mem_resp_to_cce)
-        ,.mem_resp_v_i(mem_resp_v_to_cce)
-        ,.mem_resp_yumi_i(mem_resp_yumi_from_cce)
-  
-        // From CCE
-        ,.mem_cmd_i(mem_cmd_from_cce)
-        ,.mem_cmd_v_i(mem_cmd_v_from_cce)
-        ,.mem_cmd_ready_i(mem_cmd_ready_to_cce)
-        );
-*/
-// DRAM + link 
-bp_me_cce_to_wormhole_link_client
- #(.cfg_p(cfg_p))
-  client_link
-  (.clk_i(clk_i)
-  ,.reset_i(reset_i)
-
-  ,.mem_cmd_o(mem_cmd_lo)
-  ,.mem_cmd_v_o(mem_cmd_v_lo)
-  ,.mem_cmd_yumi_i(mem_cmd_yumi_li)
-
-  ,.mem_resp_i(mem_resp_li)
-  ,.mem_resp_v_i(mem_resp_v_li)
-  ,.mem_resp_ready_o(mem_resp_ready_lo)
-
-  ,.my_cord_i(dram_cord_lo)
-  ,.my_cid_i(mem_noc_cid_width_p'(0))
-     
-  ,.cmd_link_i(mem_cmd_link_li)
-  ,.cmd_link_o(mem_cmd_link_lo)
-
-  ,.resp_link_i(mem_resp_link_li)
-  ,.resp_link_o(mem_resp_link_lo)
-  );
-
-bp2wb_convertor
-  #(.cfg_p(cfg_p))
-bp2wb
-  (.clk_i(clk_i)
-  ,.reset_i(reset_i)
-  ,.mem_cmd_i(dram_cmd_li)
-  ,.mem_cmd_v_i(dram_cmd_v_li)
-  ,.mem_cmd_yumi_o(dram_cmd_yumi_lo)
-  ,.mem_resp_o(dram_resp_lo)
-  ,.mem_resp_v_o(dram_resp_v_lo)
-  ,.mem_resp_ready_i(dram_resp_ready_li)
-  ,.dat_i(wbm_dat_i)
-  ,.dat_o(wbm_dat_o)
-  ,.ack_i(wbm_ack_i)
-  ,.adr_o(wbm_adr_o)
-  ,.stb_o(wbm_stb_o)
-  ,.cyc_o(wbm_cyc_o)
-  ,.sel_o(wbm_sel_o )
-  ,.we_o(wbm_we_o)
-  ,.cti_o(wbm_cti_o)
-  ,.bte_o(wbm_bte_o )
-  );
-
-logic [num_core_p-1:0] program_finish;
-
-bp_nonsynth_host
- #(.cfg_p(cfg_p))
- host_mmio
-  (.clk_i(clk_i)
-   ,.reset_i(reset_i)
-
-   ,.mem_cmd_i(host_cmd_li)
-   ,.mem_cmd_v_i(host_cmd_v_li)
-   ,.mem_cmd_yumi_o(host_cmd_yumi_lo)
-
-   ,.mem_resp_o(host_resp_lo)
-   ,.mem_resp_v_o(host_resp_v_lo)
-   ,.mem_resp_ready_i(host_resp_ready_li)
-
-   ,.program_finish_o(program_finish)
-   ,.all_finished_debug_o(all_finished_debug_o)
-   ,.core_passed_debug(core_passed_debug)
-   ,.core_failed_debug(core_failed_debug)
-   );
-
-/*bp_nonsynth_if_verif
- #(.cfg_p(cfg_p))
- if_verif
-  ();
-*/
-// MMIO arbitration 
-//   Should this be on its own I/O router?
-logic req_outstanding_r;
-bsg_dff_reset_en
- #(.width_p(1))
- req_outstanding_reg
-  (.clk_i(clk_i)
-   ,.reset_i(reset_i)
-   ,.en_i(mem_cmd_yumi_li | mem_resp_v_li)
-
-   ,.data_i(mem_cmd_yumi_li)
-   ,.data_o(req_outstanding_r)
-   );
-
-wire host_cmd_not_dram      = mem_cmd_v_lo & (mem_cmd_lo.addr < 39'h00_4000_0000 );//dram_base_addr_gp
-
-assign host_cmd_li          = mem_cmd_lo;
-assign host_cmd_v_li        = mem_cmd_v_lo & host_cmd_not_dram & ~req_outstanding_r;
-assign dram_cmd_li          = mem_cmd_lo;
-assign dram_cmd_v_li        = mem_cmd_v_lo & ~host_cmd_not_dram & ~req_outstanding_r;
-assign mem_cmd_yumi_li      = host_cmd_not_dram 
-                              ? host_cmd_yumi_lo 
-                              : dram_cmd_yumi_lo;
-
-assign mem_resp_li = host_resp_v_lo ? host_resp_lo : dram_resp_lo;
-assign mem_resp_v_li = host_resp_v_lo | dram_resp_v_lo;
-assign host_resp_ready_li = mem_resp_ready_lo;
-assign dram_resp_ready_li = mem_resp_ready_lo;
-
-// CFG loader + rom + link
-bp_me_cce_to_wormhole_link_master
- #(.cfg_p(cfg_p))
-  master_link
-  (.clk_i(clk_i)
-  ,.reset_i(reset_i)
-
-  ,.mem_cmd_i(cfg_cmd_lo)
-  ,.mem_cmd_v_i(cfg_cmd_ready_li & cfg_cmd_v_lo)
-  ,.mem_cmd_ready_o(cfg_cmd_ready_li)
-
-  ,.mem_resp_o(cfg_resp_li)
-  ,.mem_resp_v_o(cfg_resp_v_li)
-  ,.mem_resp_yumi_i(cfg_resp_ready_lo & cfg_resp_v_li)
-
-  ,.my_cord_i(dram_cord_lo)
-  ,.my_cid_i(mem_noc_cid_width_p'(0))
-  ,.dram_cord_i(dram_cord_lo)
-  ,.mmio_cord_i(mmio_cord_lo)
-  ,.host_cord_i(host_cord_lo)
-  
-  ,.cmd_link_i(cfg_cmd_link_li)
-  ,.cmd_link_o(cfg_cmd_link_lo)
-
-  ,.resp_link_i(cfg_resp_link_li)
-  ,.resp_link_o(cfg_resp_link_lo)
-  );
-
-localparam cce_instr_ram_addr_width_lp = `BSG_SAFE_CLOG2(num_cce_instr_ram_els_p);
-bp_cce_mmio_cfg_loader
-  #(.cfg_p(cfg_p)
-    ,.inst_width_p(`bp_cce_inst_width)
-    ,.inst_ram_addr_width_p(cce_instr_ram_addr_width_lp)
-    ,.inst_ram_els_p(num_cce_instr_ram_els_p)
-    ,.skip_ram_init_p(skip_init_p)
-  )
-  cfg_loader
-  (.clk_i(clk_i)
-   ,.reset_i(reset_i)
-   
-   ,.mem_cmd_o(cfg_cmd_lo)
-   ,.mem_cmd_v_o(cfg_cmd_v_lo)
-   ,.mem_cmd_yumi_i(cfg_cmd_ready_li & cfg_cmd_v_lo)
-   
-   ,.mem_resp_i(cfg_resp_li)
-   ,.mem_resp_v_i(cfg_resp_v_li)
-   ,.mem_resp_ready_o(cfg_resp_ready_lo)
-  );
-
-endmodule
-
diff --git a/litex/soc/cores/cpu/blackparrot/bp_fpga/bp2wb_convertor.v b/litex/soc/cores/cpu/blackparrot/bp_fpga/bp2wb_convertor.v
index 3780fb8ce..90ed0854e 100644
--- a/litex/soc/cores/cpu/blackparrot/bp_fpga/bp2wb_convertor.v
+++ b/litex/soc/cores/cpu/blackparrot/bp_fpga/bp2wb_convertor.v
@@ -8,9 +8,9 @@ module bp2wb_convertor
   import bp_common_aviary_pkg::*;
   import bp_cce_pkg::*;
   import bp_me_pkg::*;
-  #(parameter bp_cfg_e cfg_p = e_bp_single_core_cfg
-   `declare_bp_proc_params(cfg_p)
-   `declare_bp_me_if_widths(paddr_width_p, cce_block_width_p, num_lce_p, lce_assoc_p)
+  #(parameter bp_params_e bp_params_p = e_bp_single_core_cfg
+   `declare_bp_proc_params(bp_params_p)
+   `declare_bp_me_if_widths(paddr_width_p, cce_block_width_p, lce_id_width_p, lce_assoc_p)
 
 //   , parameter [paddr_width_p-1:0] dram_offset_p = '0
    , localparam num_block_words_lp   = cce_block_width_p / 64
@@ -25,84 +25,69 @@ module bp2wb_convertor
    , localparam wbone_addr_lbound = 3 //`BSG_SAFE_CLOG2(wbone_data_width / mem_granularity) //dword granularity
    , localparam total_datafetch_cycle_lp   = cce_block_width_p / wbone_data_width
    , localparam total_datafetch_cycle_width = `BSG_SAFE_CLOG2(total_datafetch_cycle_lp)
-   , localparam cached_addr_base =  32'h4000_4000//   32'h5000_0000
+   , localparam cached_addr_base =  32'h7000_0000//6000_0000 //32'h4000_4000//   
    )
-  (input                                 clk_i
-   ,(* mark_debug = "true" *) input                               reset_i
+  (                            input                                 clk_i
+   ,(* mark_debug = "true" *)  input                               reset_i
 
-   // BP side
-   ,(* mark_debug = "true" *) input [cce_mem_msg_width_lp-1:0]    mem_cmd_i
-   ,(* mark_debug = "true" *) input                               mem_cmd_v_i
-   ,(* mark_debug = "true" *) output                              mem_cmd_yumi_o
+   // BP side 
+   ,(* mark_debug = "true" *)  input [cce_mem_msg_width_lp-1:0]    mem_cmd_i
+   ,(* mark_debug = "true" *)  input                               mem_cmd_v_i
+   ,(* mark_debug = "true" *)  output                              mem_cmd_ready_o
 
-   , (* mark_debug = "true" *) output [cce_mem_msg_width_lp-1:0]   mem_resp_o
+   ,                           output [cce_mem_msg_width_lp-1:0]   mem_resp_o
    , (* mark_debug = "true" *) output                              mem_resp_v_o
-   , (* mark_debug = "true" *) input                               mem_resp_ready_i
+   , (* mark_debug = "true" *) input                               mem_resp_yumi_i
 
    // Wishbone side
    , (* mark_debug = "true" *) input [63:0]                        dat_i
    , (* mark_debug = "true" *) output logic [63:0]                 dat_o
    , (* mark_debug = "true" *) input                               ack_i
-  // , input                               err_i
-  // , input                               rty_i
+   , input                               err_i
+//   , input                               rty_i
    , (* mark_debug = "true" *) output logic [wbone_addr_ubound-wbone_addr_lbound-1:0] adr_o//TODO: Double check!!!    
    , (* mark_debug = "true" *) output logic stb_o
    , output                              cyc_o
-   , output                              sel_o //TODO: double check!!!
+   , output [7:0]                        sel_o //TODO: double check!!!
    , (* mark_debug = "true" *) output                              we_o
    , output [2:0]                        cti_o //TODO: hardwire in Litex
    , output [1:0]                        bte_o //TODO: hardwire in Litex
  
    );
 
-  `declare_bp_me_if(paddr_width_p, cce_block_width_p, num_lce_p, lce_assoc_p);
+  `declare_bp_me_if(paddr_width_p, cce_block_width_p, lce_id_width_p, lce_assoc_p);
   
   //locals
  (* mark_debug = "true" *) logic  [total_datafetch_cycle_width:0] ack_ctr  = 0;
- (* mark_debug = "true" *) bp_cce_mem_msg_s  mem_cmd_cast_i, mem_resp_cast_o, mem_cmd_r;
+ (* mark_debug = "true" *) bp_cce_mem_msg_s  mem_cmd_cast_i, mem_resp_cast_o,  mem_cmd_debug;//, mem_cmd_debug2
  (* mark_debug = "true" *) logic ready_li, v_li, stb_justgotack;
   (* mark_debug = "true" *) logic [cce_block_width_p-1:0] data_lo; 
   (* mark_debug = "true" *) logic  [cce_block_width_p-1:0] data_li;
   (* mark_debug = "true" *) wire [paddr_width_p-1:0]  mem_cmd_addr_l;
-   (* mark_debug = "true" *) logic [paddr_width_p-1:0] addr_lo;
   (* mark_debug = "true" *) logic set_stb;
-  (* mark_debug = "true" *) wire [63:0] data_little_end;
 
 
-  //reset
-  //TODO: reset ack_ctr here
   //Handshaking between Wishbone and BlackParrot through convertor  
   //3.1.3:At every rising edge of [CLK_I] the terminating signal(ACK) is sampled.  If it
   //is asserted, then  [STB_O]  is  negated. 
- 
-  assign ready_li = ( ack_ctr == 0 );
-  assign mem_cmd_yumi_o = mem_cmd_v_i && ready_li;//!stb_o then ready to take!
+  
+  assign ready_li = ( ack_ctr == 0 ) & !set_stb & !mem_resp_v_o;
+  assign mem_cmd_ready_o = ready_li;//!stb_o then ready to take!
  // assign v_li =  (ack_ctr == total_datafetch_cycle_lp-1);
-  assign mem_resp_v_o = mem_resp_ready_i & v_li;
-  assign stb_o = (set_stb) && !stb_justgotack; //addresi mem_cmd_rdan aldigimiz icin 1 cycle geriden geliyo
+  assign mem_resp_v_o =  v_li;
+  assign stb_o = (set_stb) && !stb_justgotack; 
   assign cyc_o = stb_o; 
-  assign sel_o = 0; 
+  assign sel_o = 8'b11111111; 
   assign cti_o = 0;
   assign bte_o = 0;
 
   initial begin
     ack_ctr = 0;
-    //stb_reset_lo =0;
   end
   
-/*  always_ff @(posedge clk_i) 
-    if ( mem_cmd_yumi_o )// || (ack_ctr > 0))
-    begin
-      data_li <= 0;
-      set_stb <= 1;
-    end
-*/
-
 
 //Flip stb after each ack--->RULE 3.20:
-
 // Every time we get an ACK from WB, increment counter until the counter reaches to total_datafetch_cycle_lp
-assign data_little_end = dat_i;
   always_ff @(posedge clk_i)
     begin
       
@@ -112,10 +97,17 @@ assign data_little_end = dat_i;
         set_stb <= 0;
         v_li <=0;
       end
-      
-      else if (mem_cmd_yumi_o)
+      else if (v_li)
       begin
-        data_li <= 0;
+        if (mem_resp_yumi_i)
+        begin
+          v_li <= 0;
+          ack_ctr <= 0;
+        end
+      end
+      else if (mem_cmd_v_i)
+      begin
+        //data_li <= 0;
         set_stb <= 1;
         v_li <= 0;
         stb_justgotack <= 0;
@@ -126,10 +118,9 @@ assign data_little_end = dat_i;
         if (ack_i)//stb should be negated after ack
         begin
           stb_justgotack <= 1;
-          data_li[(ack_ctr*wbone_data_width) +: wbone_data_width] <= data_little_end;
-          if ((ack_ctr == total_datafetch_cycle_lp-1) || (mem_cmd_addr_l < cached_addr_base && mem_cmd_r.msg_type == e_cce_mem_uc_wr )) //if uncached store, just one cycle is fine
-          begin
-            ack_ctr <= 0;
+          data_li[(ack_ctr*wbone_data_width) +: wbone_data_width] <= dat_i;
+          if ((ack_ctr == total_datafetch_cycle_lp-1) || (mem_cmd_addr_l < cached_addr_base && mem_cmd_r.header.msg_type == e_cce_mem_uc_wr )) //if uncached store, just one cycle is fine
+          begin 
             v_li <=1;
             set_stb <= 0;
           end
@@ -145,25 +136,23 @@ assign data_little_end = dat_i;
     end
 
   //Packet Pass from BP to BP2WB
- assign mem_cmd_cast_i = mem_cmd_i;
-
-  bsg_dff_reset_en
+  assign mem_cmd_cast_i = mem_cmd_i;
+   bp_cce_mem_msg_s mem_cmd_r;
+   bsg_dff_reset_en
   #(.width_p(cce_mem_msg_width_lp))
     mshr_reg
      (.clk_i(clk_i)
       ,.reset_i(reset_i)
-      ,.en_i(mem_cmd_yumi_o)//when
+      ,.en_i(mem_cmd_v_i)//when
       ,.data_i(mem_cmd_i)
       ,.data_o(mem_cmd_r)
       );
- 
 
  //Addr && Data && Command  Pass from BP2WB to WB 
   logic [wbone_addr_lbound-1:0] throw_away; 
-  assign mem_cmd_addr_l =  mem_cmd_r.addr;
+  assign mem_cmd_addr_l =  mem_cmd_r.header.addr;
   assign data_lo = mem_cmd_r.data;
   logic [39:0] mem_cmd_addr_l_zero64;
-  logic [7:0] partial;
   always_comb begin
     if( mem_cmd_addr_l < cached_addr_base )
     begin 
@@ -174,41 +163,105 @@ assign data_little_end = dat_i;
     else
     begin
       mem_cmd_addr_l_zero64 = mem_cmd_addr_l >> 6 << 6;
-     // addr_lo = 
       {adr_o,throw_away} =  mem_cmd_addr_l_zero64 + (ack_ctr*8);//TODO:careful
-     // adr_o = addr_lo[wbone_addr_ubound-1:wbone_addr_lbound];
       dat_o = data_lo[(ack_ctr*wbone_data_width) +: wbone_data_width];
-    end
+     end
   end
 
-   assign we_o = (mem_cmd_r.msg_type inside {e_cce_mem_uc_wr, e_cce_mem_wb});
-
-//DEBUG
-
-wire [3:0] typean;
-assign typean = mem_cmd_r.msg_type;
-wire [2:0] debug1;
-assign debug1 = (mem_cmd_r.addr[5:0]>>3);
+   assign we_o = (mem_cmd_r.header.msg_type inside {e_cce_mem_uc_wr, e_cce_mem_wb});
 
 //Data Pass from BP2WB to BP
 
-wire [cce_block_width_p-1:0]  rd_word_offset = mem_cmd_r.addr[3+:3];
+wire [cce_block_width_p-1:0]  rd_word_offset = mem_cmd_r.header.addr[3+:3];
 //wire [cce_block_width_p-1:0]  rd_byte_offset = mem_cmd_r.addr[0+:3];
 wire [cce_block_width_p-1:0]    rd_bit_shift = rd_word_offset*64; // We rely on receiver to adjust bits
 
-wire [cce_block_width_p-1:0] data_li_resp = (mem_cmd_r.msg_type == e_cce_mem_uc_rd)
+(* mark_debug = "true" *) wire [cce_block_width_p-1:0] data_li_resp = (mem_cmd_r.header.msg_type == e_cce_mem_uc_rd)
                                             ? data_li >> rd_bit_shift
                                             : data_li;
 
+
+
 assign mem_resp_cast_o = '{data     : data_li_resp
-                                ,payload : mem_cmd_r.payload
-                                ,size    : mem_cmd_r.size
-                                ,addr    : mem_cmd_r.addr
-                                ,msg_type: mem_cmd_r.msg_type
+                                ,header :'{payload : mem_cmd_r.header.payload
+                                ,size    : mem_cmd_r.header.size
+                                ,addr    : mem_cmd_r.header.addr
+                                ,msg_type: mem_cmd_r.header.msg_type
+                                }
                                 };
  
 assign mem_resp_o = mem_resp_cast_o;
 
+/*********************************************/
+/*DEBUG SECTION*/
   
+/*  always_comb
+  begin
+    if (mem_cmd_yumi_o == 1)// && mem_cmd_addr_l >=32'h8000_0000)
+    begin
+    mem_cmd_debug = mem_cmd_i;
+      if(mem_cmd_debug.addr >= 32'h80000000)
+      begin
+      $display("myarray == %x", mem_cmd_debug.addr);
+      $display("myarray == %x", mem_cmd_debug.msg_type);
+      if(mem_cmd_debug.msg_type>=3)
+      $display("myarray == %x", mem_cmd_debug.data);
+
+      end
+    end
+  end
+
+always_comb
+begin
+  if(mem_resp_v_o)
+  begin
+    mem_cmd_debug2 = mem_resp_o;
+    if(mem_cmd_debug2.addr >= 32'h80000000)
+    begin
+     $display("myresp == %x", mem_cmd_debug2.addr);
+    $display("myresp == %x", mem_cmd_debug2.msg_type);
+     if(mem_cmd_debug2.msg_type<=1)
+      $display("myresp == %x", mem_cmd_debug2.data);
+    end
+  end
+end
+*/
+
+/*wire [3:0] fake_msg_type;
+wire [10:0] fake_payload;
+wire [2:0] fake_size;
+wire [39:0] fake_addr;
+assign fake_payload = mem_cmd_r.header.payload;
+assign fake_size = mem_cmd_r.header.size;
+assign fake_addr = mem_cmd_r.header.addr;
+assign fake_msg_type = mem_cmd_r.header.msg_type;
+*/
+(* mark_debug = "true" *) logic debug_wire;
+  initial begin
+    debug_wire = 0;
+  end
+
+  assign mem_cmd_debug = mem_cmd_i;
+
+always_ff @(posedge clk_i)
+debug_wire <= (ack_i && mem_cmd_debug.header.addr >= 32'h80000000);
+
+/*  always_ff @(posedge clk_i)
+  begin
+      if(mem_cmd_v_i && mem_cmd_debug.header.addr >= 32'h80000000)
+      begin
+        debug_wire <= 1;
+        //        $display("addr == %x", mem_cmd_debug.header.addr);
+      end*/
+/*      if (mem_resp_v_o && debug_ctr < 64 && mem_cmd_debug.header.addr >= 32'h80000000)
+      begin
+        debug_gotdata[((debug_ctr-1)*512) +: 512] <= data_li_resp;
+        $display("data == %x", data_li_resp);
+      end*/
+//  end
+
+wire [3:0] typean;
+assign typean = mem_cmd_r.header.msg_type;
+
 endmodule
 
diff --git a/litex/soc/cores/cpu/blackparrot/core.py b/litex/soc/cores/cpu/blackparrot/core.py
index ab4db8ad5..e1661bc07 100644
--- a/litex/soc/cores/cpu/blackparrot/core.py
+++ b/litex/soc/cores/cpu/blackparrot/core.py
@@ -77,7 +77,7 @@ class BlackParrotRV64(CPU):
         self.platform     = platform
         self.variant      = variant
         self.reset        = Signal()
-        self.interrupt    = Signal(4)
+#        self.interrupt    = Signal(4)
         self.idbus        = idbus = wishbone.Interface(data_width=64, adr_width=37)
         self.periph_buses = [idbus]
         self.memory_buses = []
@@ -118,8 +118,13 @@ class BlackParrotRV64(CPU):
 
     @staticmethod
     def add_sources(platform, variant="standard"):
-        filename = get_data_mod("cpu", "blackparrot").data_file(
-            "flist_litex.verilator")
+        simulation = 0
+        if (simulation == 1):
+            filename = get_data_mod("cpu", "blackparrot").data_file(
+            "flist.verilator")
+        else:
+            filename = get_data_mod("cpu", "blackparrot").data_file(
+            "flist.fpga")
         with open(filename) as openfileobject:
             for line in openfileobject:
                 temp = line
diff --git a/litex/soc/cores/cpu/blackparrot/crt0.S b/litex/soc/cores/cpu/blackparrot/crt0.S
index 9badaa48a..2b82399d4 100644
--- a/litex/soc/cores/cpu/blackparrot/crt0.S
+++ b/litex/soc/cores/cpu/blackparrot/crt0.S
@@ -68,7 +68,7 @@ bss_loop:
 bss_done:
 
 //  call plic_init // initialize external interrupt controller
-#  li a0, 0x800   // external interrupt sources only (using LiteX timer);
+  li a0, 0x800   // external interrupt sources only (using LiteX timer);
                  // NOTE: must still enable mstatus.MIE!
   csrw mie,a0
 
diff --git a/litex/soc/software/bios/isr.c b/litex/soc/software/bios/isr.c
index 0044f3d16..d6b417219 100644
--- a/litex/soc/software/bios/isr.c
+++ b/litex/soc/software/bios/isr.c
@@ -78,6 +78,8 @@ void isr(void)
 
 #else
 
-void isr(void){};
+void isr(void){
+printf("ISR blackparrot\n");
+};
 
 #endif
diff --git a/litex/soc/software/bios/sdram.c b/litex/soc/software/bios/sdram.c
index 7798d3013..513a12665 100644
--- a/litex/soc/software/bios/sdram.c
+++ b/litex/soc/software/bios/sdram.c
@@ -1005,7 +1005,7 @@ int memtest(void)
 		return 0;
 	else {
 		printf("Memtest OK\n");
-		//memspeed();
+		memspeed();
 		return 1;
 	}
 }
diff --git a/litex/tools/litex_sim.py b/litex/tools/litex_sim.py
index ebba204bd..83c50793d 100755
--- a/litex/tools/litex_sim.py
+++ b/litex/tools/litex_sim.py
@@ -177,7 +177,7 @@ class SimSoC(SoCSDRAM):
             ident               = "LiteX Simulation", ident_version=True,
             l2_reverse          = False,
             **kwargs)
-        self.add_constant("UART_POLLING",None)
+#        self.add_constant("UART_POLLING",None)
         # CRG --------------------------------------------------------------------------------------
         self.submodules.crg = CRG(platform.request("sys_clk"))
 
@@ -353,7 +353,7 @@ def main():
         with_analyzer  = args.with_analyzer,
         sdram_init     = [] if args.sdram_init is None else get_mem_data(args.sdram_init, cpu_endianness),
         **soc_kwargs)
-    if args.ram_init is not None:
+    if args.sdram_init is not None: #sdram_init
         soc.add_constant("ROM_BOOT_ADDRESS", 0x80000000)
     if args.with_ethernet:
         for i in range(4):

From 3eb9efd64f33c02fb1492965f881fa5f725d0497 Mon Sep 17 00:00:00 2001
From: sadullah <sadullahcanakci@gmail.com>
Date: Thu, 30 Apr 2020 23:02:32 -0400
Subject: [PATCH 66/95] BP fpga recent version

---
 ...xampleBlackParrotSystem_Linux_Simulation.v | 356 +++++++++++++++++
 .../bp_fpga/ExampleBlackParrotSystem_UART.v   | 357 ++++++++++++++++++
 .../bp_fpga/fpga/ExampleBlackParrotSystem.v   | 357 ++++++++++++++++++
 .../simulation/ExampleBlackParrotSystem.v     | 357 ++++++++++++++++++
 litex/soc/cores/cpu/blackparrot/flist.fpga    | 250 ++++++++++++
 .../soc/cores/cpu/blackparrot/flist.verilator | 250 ++++++++++++
 6 files changed, 1927 insertions(+)
 create mode 100644 litex/soc/cores/cpu/blackparrot/bp_fpga/ExampleBlackParrotSystem_Linux_Simulation.v
 create mode 100644 litex/soc/cores/cpu/blackparrot/bp_fpga/ExampleBlackParrotSystem_UART.v
 create mode 100644 litex/soc/cores/cpu/blackparrot/bp_fpga/fpga/ExampleBlackParrotSystem.v
 create mode 100644 litex/soc/cores/cpu/blackparrot/bp_fpga/simulation/ExampleBlackParrotSystem.v
 create mode 100644 litex/soc/cores/cpu/blackparrot/flist.fpga
 create mode 100644 litex/soc/cores/cpu/blackparrot/flist.verilator

diff --git a/litex/soc/cores/cpu/blackparrot/bp_fpga/ExampleBlackParrotSystem_Linux_Simulation.v b/litex/soc/cores/cpu/blackparrot/bp_fpga/ExampleBlackParrotSystem_Linux_Simulation.v
new file mode 100644
index 000000000..3c053f218
--- /dev/null
+++ b/litex/soc/cores/cpu/blackparrot/bp_fpga/ExampleBlackParrotSystem_Linux_Simulation.v
@@ -0,0 +1,356 @@
+/**
+  *
+  * ExampleBlackParrotSystem.v
+  *
+  */
+  
+`include "bsg_noc_links.vh"
+
+module ExampleBlackParrotSystem
+ import bp_common_pkg::*;
+ import bp_common_aviary_pkg::*;
+ import bp_be_pkg::*;
+ import bp_common_rv64_pkg::*;
+ import bp_cce_pkg::*;
+ import bp_me_pkg::*;
+ import bp_common_cfg_link_pkg::*;
+ import bsg_noc_pkg::*;
+ #(parameter bp_params_e bp_params_p = e_bp_softcore_cfg
+   `declare_bp_proc_params(bp_params_p)
+   `declare_bp_me_if_widths(paddr_width_p, cce_block_width_p, lce_id_width_p, lce_assoc_p)
+
+   // Tracing parameters
+   , parameter calc_trace_p                = 0
+   , parameter cce_trace_p                 = 0
+   , parameter cmt_trace_p                 = 0
+   , parameter dram_trace_p                = 0
+   , parameter npc_trace_p                 = 0
+   , parameter dcache_trace_p              = 0
+   , parameter vm_trace_p                  = 0
+   , parameter preload_mem_p               = 1
+   , parameter load_nbf_p                  = 0
+   , parameter skip_init_p                 = 0
+   , parameter cosim_p                     = 0
+   , parameter cosim_cfg_file_p            = "prog.cfg"
+
+   , parameter mem_zero_p         = 1
+   , parameter mem_file_p         = "prog.mem"
+   , parameter mem_cap_in_bytes_p = 2**25
+   , parameter [paddr_width_p-1:0] mem_offset_p = paddr_width_p'(32'h8000_0000)
+
+   // Number of elements in the fake BlackParrot memory
+   , parameter use_max_latency_p      = 1
+   , parameter use_random_latency_p   = 0
+   , parameter use_dramsim2_latency_p = 0
+
+   , parameter max_latency_p = 15
+
+   , parameter dram_clock_period_in_ps_p = 1000
+   , parameter dram_cfg_p                = "dram_ch.ini"
+   , parameter dram_sys_cfg_p            = "dram_sys.ini"
+   , parameter dram_capacity_p           = 16384
+   )
+  (input clk_i
+   , input reset_i
+      //Wishbone interface
+   , input  [63:0]  wbm_dat_i
+   , output [63:0]  wbm_dat_o
+   , input          wbm_ack_i
+   , input          wbm_err_i
+//   , input          wbm_rty_i
+   , output [36:0]  wbm_adr_o //TODO parametrize this
+   , output         wbm_stb_o
+   , output         wbm_cyc_o
+   , output [7:0]   wbm_sel_o //TODO: how many  bits ? check
+   , output         wbm_we_o
+   , output [2:0]   wbm_cti_o //TODO:
+   , output [1:0]   wbm_bte_o
+  // , input  [3:0]   interrupts
+   );
+
+`declare_bp_me_if(paddr_width_p, cce_block_width_p, lce_id_width_p, lce_assoc_p)
+
+bp_cce_mem_msg_s proc_mem_cmd_lo;
+logic proc_mem_cmd_v_lo, proc_mem_cmd_ready_li;
+bp_cce_mem_msg_s proc_mem_resp_li;
+logic proc_mem_resp_v_li, proc_mem_resp_yumi_lo;
+
+bp_cce_mem_msg_s proc_io_cmd_lo;
+logic proc_io_cmd_v_lo, proc_io_cmd_ready_li;
+bp_cce_mem_msg_s proc_io_resp_li;
+logic proc_io_resp_v_li, proc_io_resp_yumi_lo;
+
+bp_cce_mem_msg_s io_cmd_lo;
+logic io_cmd_v_lo, io_cmd_ready_li;
+bp_cce_mem_msg_s io_resp_li;
+logic io_resp_v_li, io_resp_yumi_lo;
+bp_softcore
+ #(.bp_params_p(bp_params_p))
+ softcore
+  (.clk_i(clk_i)
+   ,.reset_i(reset_i)
+
+   ,.io_cmd_o(proc_io_cmd_lo)
+   ,.io_cmd_v_o(proc_io_cmd_v_lo)
+   ,.io_cmd_ready_i(proc_io_cmd_ready_li)
+
+   ,.io_resp_i(proc_io_resp_li)
+   ,.io_resp_v_i(proc_io_resp_v_li)
+   ,.io_resp_yumi_o(proc_io_resp_yumi_lo)
+
+   ,.mem_cmd_o(proc_mem_cmd_lo)
+   ,.mem_cmd_v_o(proc_mem_cmd_v_lo)
+   ,.mem_cmd_ready_i(proc_mem_cmd_ready_li)
+
+   ,.mem_resp_i(proc_mem_resp_li)
+   ,.mem_resp_v_i(proc_mem_resp_v_li)
+   ,.mem_resp_yumi_o(proc_mem_resp_yumi_lo)
+   );
+
+ bp2wb_convertor
+   #(.bp_params_p(bp_params_p))
+   bp2wb
+    (.clk_i(clk_i)
+     ,.reset_i(reset_i)
+    ,.mem_cmd_i(proc_mem_cmd_lo)
+     ,.mem_cmd_v_i(proc_mem_cmd_v_lo & proc_mem_cmd_ready_li)
+     ,.mem_cmd_ready_o(proc_mem_cmd_ready_li)
+
+     ,.mem_resp_o(proc_mem_resp_li)
+     ,.mem_resp_v_o(proc_mem_resp_v_li)
+     ,.mem_resp_yumi_i(proc_mem_resp_yumi_lo)
+
+     ,.dat_i(wbm_dat_i)
+     ,.dat_o(wbm_dat_o)
+     ,.ack_i(wbm_ack_i)
+     ,.adr_o(wbm_adr_o)
+     ,.stb_o(wbm_stb_o)
+     ,.cyc_o(wbm_cyc_o)
+     ,.sel_o(wbm_sel_o )
+     ,.we_o(wbm_we_o)
+     ,.cti_o(wbm_cti_o)
+     ,.bte_o(wbm_bte_o )
+    // ,.rty_i(wbm_rty_i)
+     ,.err_i(wbm_err_i)
+     );
+
+/*
+bp_mem
+ mem
+  (.clk_i(clk_i)
+   ,.reset_i(reset_i)
+ 
+   ,.mem_cmd_i(proc_mem_cmd_lo)
+   ,.mem_cmd_v_i(proc_mem_cmd_v_lo & proc_mem_cmd_ready_li)
+   ,.mem_cmd_ready_o(proc_mem_cmd_ready_li)
+ 
+   ,.mem_resp_o(proc_mem_resp_li)
+   ,.mem_resp_v_o(proc_mem_resp_v_li)
+   ,.mem_resp_yumi_i(proc_mem_resp_yumi_lo)
+   );
+*/
+logic program_finish_lo;
+bp_nonsynth_host
+ #(.bp_params_p(bp_params_p))
+ host
+  (.clk_i(clk_i)
+   ,.reset_i(reset_i)
+
+   ,.io_cmd_i(proc_io_cmd_lo)
+   ,.io_cmd_v_i(proc_io_cmd_v_lo & proc_io_cmd_ready_li)
+   ,.io_cmd_ready_o(proc_io_cmd_ready_li)
+
+   ,.io_resp_o(proc_io_resp_li)
+   ,.io_resp_v_o(proc_io_resp_v_li)
+   ,.io_resp_yumi_i(proc_io_resp_yumi_lo)
+
+   ,.program_finish_o(program_finish_lo)
+   );
+
+/*bind bp_be_top
+  bp_nonsynth_commit_tracer
+   #(.bp_params_p(bp_params_p))
+   commit_tracer
+    (.clk_i(clk_i & (ExampleBlackParrotSystem.cmt_trace_p == 1))
+     ,.reset_i(reset_i)
+     ,.freeze_i('0)
+
+     ,.mhartid_i('0)
+
+     ,.commit_v_i(be_calculator.commit_pkt.instret)
+     ,.commit_pc_i(be_calculator.commit_pkt.pc)
+     ,.commit_instr_i(be_calculator.commit_pkt.instr)
+
+     ,.rd_w_v_i(be_calculator.wb_pkt.rd_w_v)
+     ,.rd_addr_i(be_calculator.wb_pkt.rd_addr)
+     ,.rd_data_i(be_calculator.wb_pkt.rd_data)
+     );
+*/
+/*  bind bp_be_top
+    bp_nonsynth_cosim
+     #(.bp_params_p(bp_params_p))
+      cosim
+      (.clk_i(clk_i)
+       ,.reset_i(reset_i)
+       ,.en_i(ExampleBlackParrotSystem.cosim_p == 1)
+
+       ,.mhartid_i(be_checker.scheduler.int_regfile.cfg_bus.core_id)
+       // Want to pass config file as a parameter, but cannot in Verilator 4.025
+       // Parameter-resolved constants must not use dotted references
+       ,.config_file_i(ExampleBlackParrotSystem.cosim_cfg_file_p)
+
+       ,.commit_v_i(be_calculator.commit_pkt.instret)
+       ,.commit_pc_i(be_calculator.commit_pkt.pc)
+       ,.commit_instr_i(be_calculator.commit_pkt.instr)
+
+       ,.rd_w_v_i(be_calculator.wb_pkt.rd_w_v)
+       ,.rd_addr_i(be_calculator.wb_pkt.rd_addr)
+       ,.rd_data_i(be_calculator.wb_pkt.rd_data)
+
+       ,.interrupt_v_i(be_mem.csr.trap_pkt_cast_o._interrupt)
+       ,.cause_i(be_mem.csr.trap_pkt_cast_o.cause)
+       );
+*/
+/*bind bp_be_top
+  bp_be_nonsynth_perf
+   #(.bp_params_p(bp_params_p))
+   perf
+    (.clk_i(clk_i)
+     ,.reset_i(reset_i)
+
+     ,.mhartid_i(be_checker.scheduler.int_regfile.cfg_bus.core_id)
+
+     ,.fe_nop_i(be_calculator.exc_stage_r[2].fe_nop_v)
+     ,.be_nop_i(be_calculator.exc_stage_r[2].be_nop_v)
+     ,.me_nop_i(be_calculator.exc_stage_r[2].me_nop_v)
+     ,.poison_i(be_calculator.exc_stage_r[2].poison_v)
+     ,.roll_i(be_calculator.exc_stage_r[2].roll_v)
+
+     ,.instr_cmt_i(be_calculator.commit_pkt.instret)
+
+     ,.program_finish_i(ExampleBlackParrotSystem.program_finish_lo)
+     );
+*/
+ /* bind bp_be_director
+    bp_be_nonsynth_npc_tracer
+     #(.bp_params_p(bp_params_p))
+     npc_tracer
+      (.clk_i(clk_i & (ExampleBlackParrotSystem.npc_trace_p == 1))
+       ,.reset_i(reset_i)
+       ,.freeze_i('0)
+
+       ,.mhartid_i(be_checker.scheduler.int_regfile.cfg_bus.core_id)
+
+       ,.npc_w_v(npc_w_v)
+       ,.npc_n(npc_n)
+       ,.npc_r(npc_r)
+       ,.expected_npc_o(expected_npc_o)
+
+       ,.fe_cmd_i(fe_cmd)
+       ,.fe_cmd_v(fe_cmd_v)
+
+       ,.commit_pkt_i(commit_pkt)
+       );
+*/
+  /*bind bp_be_dcache
+    bp_be_nonsynth_dcache_tracer
+     #(.bp_params_p(bp_params_p))
+     dcache_tracer
+      (.clk_i(clk_i & (ExampleBlackParrotSystem.dcache_trace_p == 1))
+       ,.reset_i(reset_i)
+       ,.freeze_i('0)
+
+       ,.mhartid_i(cfg_bus_cast_i.core_id)
+
+       ,.v_tv_r(v_tv_r)
+       //,.cache_miss_i(cache_miss_i)
+
+       ,.paddr_tv_r(paddr_tv_r)
+       ,.uncached_tv_r(uncached_tv_r)
+       ,.load_op_tv_r(load_op_tv_r)
+       ,.store_op_tv_r(store_op_tv_r)
+       ,.lr_op_tv_r(lr_op_tv_r)
+       ,.sc_op_tv_r(sc_op_tv_r)
+       ,.store_data(data_tv_r)
+       ,.load_data(data_o)
+       );*/
+/*
+  bind bp_be_top
+    bp_be_nonsynth_calc_tracer
+     #(.bp_params_p(bp_params_p))
+     calc_tracer
+      (.clk_i(clk_i & (ExampleBlackParrotSystem.calc_trace_p == 1))
+       ,.reset_i(reset_i)
+       ,.freeze_i('0)
+
+       ,.mhartid_i(be_checker.scheduler.int_regfile.cfg_bus.core_id)
+
+       ,.issue_pkt_i(be_checker.scheduler.issue_pkt)
+       ,.issue_pkt_v_i(be_checker.scheduler.fe_queue_yumi_o)
+
+       ,.fe_nop_v_i(be_calculator.exc_stage_n[0].fe_nop_v)
+       ,.be_nop_v_i(be_calculator.exc_stage_n[0].be_nop_v)
+       ,.me_nop_v_i(be_calculator.exc_stage_n[0].me_nop_v)
+       ,.dispatch_pkt_i(be_calculator.dispatch_pkt)
+
+       ,.ex1_br_tgt_i(be_calculator.calc_status.ex1_npc)
+       ,.ex1_btaken_i(be_calculator.pipe_int.btaken)
+       ,.iwb_result_i(be_calculator.comp_stage_n[3])
+       ,.fwb_result_i(be_calculator.comp_stage_n[4])
+
+       ,.cmt_trace_exc_i(be_calculator.exc_stage_n[1+:5])
+
+       ,.trap_v_i(be_mem.csr.trap_pkt_cast_o._interrupt | be_mem.csr.trap_pkt_cast_o.exception)
+       ,.mtvec_i(be_mem.csr.mtvec_n)
+       ,.mtval_i(be_mem.csr.mtval_n[0+:vaddr_width_p])
+       ,.ret_v_i(be_mem.csr.trap_pkt_cast_o.eret)
+       ,.mepc_i(be_mem.csr.mepc_n[0+:vaddr_width_p])
+       ,.mcause_i(be_mem.csr.mcause_n)
+
+       ,.priv_mode_i(be_mem.csr.priv_mode_n)
+       ,.mpp_i(be_mem.csr.mstatus_n.mpp)
+       );
+
+  bind bp_core_minimal
+    bp_be_nonsynth_vm_tracer
+    #(.bp_params_p(bp_params_p))
+    vm_tracer
+      (.clk_i(clk_i & (ExampleBlackParrotSystem.vm_trace_p == 1))
+       ,.reset_i(reset_i)
+       ,.freeze_i('0)
+
+       ,.mhartid_i(be.be_checker.scheduler.int_regfile.cfg_bus.core_id)
+
+       ,.itlb_clear_i(fe.mem.itlb.flush_i)
+       ,.itlb_fill_v_i(fe.mem.itlb.v_i & fe.mem.itlb.w_i)
+       ,.itlb_vtag_i(fe.mem.itlb.vtag_i)
+       ,.itlb_entry_i(fe.mem.itlb.entry_i)
+
+       ,.dtlb_clear_i(be.be_mem.dtlb.flush_i)
+       ,.dtlb_fill_v_i(be.be_mem.dtlb.v_i & be.be_mem.dtlb.w_i)
+       ,.dtlb_vtag_i(be.be_mem.dtlb.vtag_i)
+       ,.dtlb_entry_i(be.be_mem.dtlb.entry_i)
+       );
+*/
+  /*bp_mem_nonsynth_tracer
+   #(.bp_params_p(bp_params_p))
+   bp_mem_tracer
+    (.clk_i(clk_i & (ExampleBlackParrotSystem.dram_trace_p == 1))
+     ,.reset_i(reset_i)
+
+     ,.mem_cmd_i(proc_mem_cmd_lo)
+     ,.mem_cmd_v_i(proc_mem_cmd_v_lo & proc_mem_cmd_ready_li)
+     ,.mem_cmd_ready_i(proc_mem_cmd_ready_li)
+
+     ,.mem_resp_i(proc_mem_resp_li)
+     ,.mem_resp_v_i(proc_mem_resp_v_li)
+     ,.mem_resp_yumi_i(proc_mem_resp_yumi_lo)
+     );
+*/
+/*bp_nonsynth_if_verif
+ #(.bp_params_p(bp_params_p))
+ if_verif
+  ();
+*/
+endmodule
+
diff --git a/litex/soc/cores/cpu/blackparrot/bp_fpga/ExampleBlackParrotSystem_UART.v b/litex/soc/cores/cpu/blackparrot/bp_fpga/ExampleBlackParrotSystem_UART.v
new file mode 100644
index 000000000..c226c3316
--- /dev/null
+++ b/litex/soc/cores/cpu/blackparrot/bp_fpga/ExampleBlackParrotSystem_UART.v
@@ -0,0 +1,357 @@
+/**
+  *
+  * ExampleBlackParrotSystem.v
+  *
+  */
+  
+`include "bsg_noc_links.vh"
+
+module ExampleBlackParrotSystem
+ import bp_common_pkg::*;
+ import bp_common_aviary_pkg::*;
+ import bp_be_pkg::*;
+ import bp_common_rv64_pkg::*;
+ import bp_cce_pkg::*;
+ import bp_me_pkg::*;
+ import bp_common_cfg_link_pkg::*;
+ import bsg_noc_pkg::*;
+ #(parameter bp_params_e bp_params_p = e_bp_softcore_cfg
+   `declare_bp_proc_params(bp_params_p)
+   `declare_bp_me_if_widths(paddr_width_p, cce_block_width_p, lce_id_width_p, lce_assoc_p)
+
+   // Tracing parameters
+   , parameter calc_trace_p                = 0
+   , parameter cce_trace_p                 = 0
+   , parameter cmt_trace_p                 = 1
+   , parameter dram_trace_p                = 1
+   , parameter npc_trace_p                 = 0
+   , parameter dcache_trace_p              = 0
+   , parameter vm_trace_p                  = 0
+   , parameter preload_mem_p               = 1
+   , parameter load_nbf_p                  = 0
+   , parameter skip_init_p                 = 0
+   , parameter cosim_p                     = 0
+   , parameter cosim_cfg_file_p            = "prog.cfg"
+
+   , parameter mem_zero_p         = 1
+   , parameter mem_file_p         = "prog.mem"
+   , parameter mem_cap_in_bytes_p = 2**25
+   , parameter [paddr_width_p-1:0] mem_offset_p = paddr_width_p'(32'h8000_0000)
+
+   // Number of elements in the fake BlackParrot memory
+   , parameter use_max_latency_p      = 1
+   , parameter use_random_latency_p   = 0
+   , parameter use_dramsim2_latency_p = 0
+
+   , parameter max_latency_p = 15
+
+   , parameter dram_clock_period_in_ps_p = 1000
+   , parameter dram_cfg_p                = "dram_ch.ini"
+   , parameter dram_sys_cfg_p            = "dram_sys.ini"
+   , parameter dram_capacity_p           = 16384
+   )
+  (input clk_i
+   , input reset_i
+      //Wishbone interface
+   , input  [63:0]  wbm_dat_i
+   , output [63:0]  wbm_dat_o
+   , input          wbm_ack_i
+   , input          wbm_err_i
+//   , input          wbm_rty_i
+   , output [36:0]  wbm_adr_o //TODO parametrize this
+   , output         wbm_stb_o
+   , output         wbm_cyc_o
+   , output [7:0]   wbm_sel_o //TODO: how many  bits ? check
+   , output         wbm_we_o
+   , output [2:0]   wbm_cti_o //TODO:
+   , output [1:0]   wbm_bte_o
+  // , input  [3:0]   interrupts
+   );
+
+`declare_bp_me_if(paddr_width_p, cce_block_width_p, lce_id_width_p, lce_assoc_p)
+
+bp_cce_mem_msg_s proc_mem_cmd_lo;
+logic proc_mem_cmd_v_lo, proc_mem_cmd_ready_li;
+bp_cce_mem_msg_s proc_mem_resp_li;
+logic proc_mem_resp_v_li, proc_mem_resp_yumi_lo;
+
+bp_cce_mem_msg_s proc_io_cmd_lo;
+logic proc_io_cmd_v_lo, proc_io_cmd_ready_li;
+bp_cce_mem_msg_s proc_io_resp_li;
+logic proc_io_resp_v_li, proc_io_resp_yumi_lo;
+
+bp_cce_mem_msg_s io_cmd_lo;
+logic io_cmd_v_lo, io_cmd_ready_li;
+bp_cce_mem_msg_s io_resp_li;
+logic io_resp_v_li, io_resp_yumi_lo;
+bp_softcore
+ #(.bp_params_p(bp_params_p))
+ softcore
+  (.clk_i(clk_i)
+   ,.reset_i(reset_i)
+
+   ,.io_cmd_o(proc_io_cmd_lo)
+   ,.io_cmd_v_o(proc_io_cmd_v_lo)
+   ,.io_cmd_ready_i(proc_io_cmd_ready_li)
+
+   ,.io_resp_i(proc_io_resp_li)
+   ,.io_resp_v_i(proc_io_resp_v_li)
+   ,.io_resp_yumi_o(proc_io_resp_yumi_lo)
+
+   ,.mem_cmd_o(proc_mem_cmd_lo)
+   ,.mem_cmd_v_o(proc_mem_cmd_v_lo)
+   ,.mem_cmd_ready_i(proc_mem_cmd_ready_li)
+
+   ,.mem_resp_i(proc_mem_resp_li)
+   ,.mem_resp_v_i(proc_mem_resp_v_li)
+   ,.mem_resp_yumi_o(proc_mem_resp_yumi_lo)
+   );
+
+ bp2wb_convertor
+   #(.bp_params_p(bp_params_p))
+   bp2wb
+    (.clk_i(clk_i)
+     ,.reset_i(reset_i)
+    ,.mem_cmd_i(proc_mem_cmd_lo)
+     ,.mem_cmd_v_i(proc_mem_cmd_v_lo & proc_mem_cmd_ready_li)
+     ,.mem_cmd_ready_o(proc_mem_cmd_ready_li)
+
+     ,.mem_resp_o(proc_mem_resp_li)
+     ,.mem_resp_v_o(proc_mem_resp_v_li)
+     ,.mem_resp_yumi_i(proc_mem_resp_yumi_lo)
+
+     ,.dat_i(wbm_dat_i)
+     ,.dat_o(wbm_dat_o)
+     ,.ack_i(wbm_ack_i)
+     ,.adr_o(wbm_adr_o)
+     ,.stb_o(wbm_stb_o)
+     ,.cyc_o(wbm_cyc_o)
+     ,.sel_o(wbm_sel_o )
+     ,.we_o(wbm_we_o)
+     ,.cti_o(wbm_cti_o)
+     ,.bte_o(wbm_bte_o )
+    // ,.rty_i(wbm_rty_i)
+     ,.err_i(wbm_err_i)
+     );
+
+/*
+bp_mem
+ mem
+  (.clk_i(clk_i)
+   ,.reset_i(reset_i)
+ 
+   ,.mem_cmd_i(proc_mem_cmd_lo)
+   ,.mem_cmd_v_i(proc_mem_cmd_v_lo & proc_mem_cmd_ready_li)
+   ,.mem_cmd_ready_o(proc_mem_cmd_ready_li)
+ 
+   ,.mem_resp_o(proc_mem_resp_li)
+   ,.mem_resp_v_o(proc_mem_resp_v_li)
+   ,.mem_resp_yumi_i(proc_mem_resp_yumi_lo)
+   );
+*/
+logic program_finish_lo;
+assign proc_io_cmd_ready_li = 1;
+/*bp_nonsynth_host
+ #(.bp_params_p(bp_params_p))
+ host
+  (.clk_i(clk_i)
+   ,.reset_i(reset_i)
+
+   ,.io_cmd_i(proc_io_cmd_lo)
+   ,.io_cmd_v_i(proc_io_cmd_v_lo & proc_io_cmd_ready_li)
+   ,.io_cmd_ready_o(proc_io_cmd_ready_li)
+
+   ,.io_resp_o(proc_io_resp_li)
+   ,.io_resp_v_o(proc_io_resp_v_li)
+   ,.io_resp_yumi_i(proc_io_resp_yumi_lo)
+
+   ,.program_finish_o(program_finish_lo)
+   );
+*/
+bind bp_be_top
+  bp_nonsynth_commit_tracer
+   #(.bp_params_p(bp_params_p))
+   commit_tracer
+    (.clk_i(clk_i & (ExampleBlackParrotSystem.cmt_trace_p == 1))
+     ,.reset_i(reset_i)
+     ,.freeze_i('0)
+
+     ,.mhartid_i('0)
+
+     ,.commit_v_i(be_calculator.commit_pkt.instret)
+     ,.commit_pc_i(be_calculator.commit_pkt.pc)
+     ,.commit_instr_i(be_calculator.commit_pkt.instr)
+
+     ,.rd_w_v_i(be_calculator.wb_pkt.rd_w_v)
+     ,.rd_addr_i(be_calculator.wb_pkt.rd_addr)
+     ,.rd_data_i(be_calculator.wb_pkt.rd_data)
+     );
+
+/*  bind bp_be_top
+    bp_nonsynth_cosim
+     #(.bp_params_p(bp_params_p))
+      cosim
+      (.clk_i(clk_i)
+       ,.reset_i(reset_i)
+       ,.en_i(ExampleBlackParrotSystem.cosim_p == 1)
+
+       ,.mhartid_i(be_checker.scheduler.int_regfile.cfg_bus.core_id)
+       // Want to pass config file as a parameter, but cannot in Verilator 4.025
+       // Parameter-resolved constants must not use dotted references
+       ,.config_file_i(ExampleBlackParrotSystem.cosim_cfg_file_p)
+
+       ,.commit_v_i(be_calculator.commit_pkt.instret)
+       ,.commit_pc_i(be_calculator.commit_pkt.pc)
+       ,.commit_instr_i(be_calculator.commit_pkt.instr)
+
+       ,.rd_w_v_i(be_calculator.wb_pkt.rd_w_v)
+       ,.rd_addr_i(be_calculator.wb_pkt.rd_addr)
+       ,.rd_data_i(be_calculator.wb_pkt.rd_data)
+
+       ,.interrupt_v_i(be_mem.csr.trap_pkt_cast_o._interrupt)
+       ,.cause_i(be_mem.csr.trap_pkt_cast_o.cause)
+       );
+*/
+/*bind bp_be_top
+  bp_be_nonsynth_perf
+   #(.bp_params_p(bp_params_p))
+   perf
+    (.clk_i(clk_i)
+     ,.reset_i(reset_i)
+
+     ,.mhartid_i(be_checker.scheduler.int_regfile.cfg_bus.core_id)
+
+     ,.fe_nop_i(be_calculator.exc_stage_r[2].fe_nop_v)
+     ,.be_nop_i(be_calculator.exc_stage_r[2].be_nop_v)
+     ,.me_nop_i(be_calculator.exc_stage_r[2].me_nop_v)
+     ,.poison_i(be_calculator.exc_stage_r[2].poison_v)
+     ,.roll_i(be_calculator.exc_stage_r[2].roll_v)
+
+     ,.instr_cmt_i(be_calculator.commit_pkt.instret)
+
+     ,.program_finish_i(ExampleBlackParrotSystem.program_finish_lo)
+     );
+*/
+ /* bind bp_be_director
+    bp_be_nonsynth_npc_tracer
+     #(.bp_params_p(bp_params_p))
+     npc_tracer
+      (.clk_i(clk_i & (ExampleBlackParrotSystem.npc_trace_p == 1))
+       ,.reset_i(reset_i)
+       ,.freeze_i('0)
+
+       ,.mhartid_i(be_checker.scheduler.int_regfile.cfg_bus.core_id)
+
+       ,.npc_w_v(npc_w_v)
+       ,.npc_n(npc_n)
+       ,.npc_r(npc_r)
+       ,.expected_npc_o(expected_npc_o)
+
+       ,.fe_cmd_i(fe_cmd)
+       ,.fe_cmd_v(fe_cmd_v)
+
+       ,.commit_pkt_i(commit_pkt)
+       );
+*/
+  /*bind bp_be_dcache
+    bp_be_nonsynth_dcache_tracer
+     #(.bp_params_p(bp_params_p))
+     dcache_tracer
+      (.clk_i(clk_i & (ExampleBlackParrotSystem.dcache_trace_p == 1))
+       ,.reset_i(reset_i)
+       ,.freeze_i('0)
+
+       ,.mhartid_i(cfg_bus_cast_i.core_id)
+
+       ,.v_tv_r(v_tv_r)
+       //,.cache_miss_i(cache_miss_i)
+
+       ,.paddr_tv_r(paddr_tv_r)
+       ,.uncached_tv_r(uncached_tv_r)
+       ,.load_op_tv_r(load_op_tv_r)
+       ,.store_op_tv_r(store_op_tv_r)
+       ,.lr_op_tv_r(lr_op_tv_r)
+       ,.sc_op_tv_r(sc_op_tv_r)
+       ,.store_data(data_tv_r)
+       ,.load_data(data_o)
+       );*/
+/*
+  bind bp_be_top
+    bp_be_nonsynth_calc_tracer
+     #(.bp_params_p(bp_params_p))
+     calc_tracer
+      (.clk_i(clk_i & (ExampleBlackParrotSystem.calc_trace_p == 1))
+       ,.reset_i(reset_i)
+       ,.freeze_i('0)
+
+       ,.mhartid_i(be_checker.scheduler.int_regfile.cfg_bus.core_id)
+
+       ,.issue_pkt_i(be_checker.scheduler.issue_pkt)
+       ,.issue_pkt_v_i(be_checker.scheduler.fe_queue_yumi_o)
+
+       ,.fe_nop_v_i(be_calculator.exc_stage_n[0].fe_nop_v)
+       ,.be_nop_v_i(be_calculator.exc_stage_n[0].be_nop_v)
+       ,.me_nop_v_i(be_calculator.exc_stage_n[0].me_nop_v)
+       ,.dispatch_pkt_i(be_calculator.dispatch_pkt)
+
+       ,.ex1_br_tgt_i(be_calculator.calc_status.ex1_npc)
+       ,.ex1_btaken_i(be_calculator.pipe_int.btaken)
+       ,.iwb_result_i(be_calculator.comp_stage_n[3])
+       ,.fwb_result_i(be_calculator.comp_stage_n[4])
+
+       ,.cmt_trace_exc_i(be_calculator.exc_stage_n[1+:5])
+
+       ,.trap_v_i(be_mem.csr.trap_pkt_cast_o._interrupt | be_mem.csr.trap_pkt_cast_o.exception)
+       ,.mtvec_i(be_mem.csr.mtvec_n)
+       ,.mtval_i(be_mem.csr.mtval_n[0+:vaddr_width_p])
+       ,.ret_v_i(be_mem.csr.trap_pkt_cast_o.eret)
+       ,.mepc_i(be_mem.csr.mepc_n[0+:vaddr_width_p])
+       ,.mcause_i(be_mem.csr.mcause_n)
+
+       ,.priv_mode_i(be_mem.csr.priv_mode_n)
+       ,.mpp_i(be_mem.csr.mstatus_n.mpp)
+       );
+
+  bind bp_core_minimal
+    bp_be_nonsynth_vm_tracer
+    #(.bp_params_p(bp_params_p))
+    vm_tracer
+      (.clk_i(clk_i & (ExampleBlackParrotSystem.vm_trace_p == 1))
+       ,.reset_i(reset_i)
+       ,.freeze_i('0)
+
+       ,.mhartid_i(be.be_checker.scheduler.int_regfile.cfg_bus.core_id)
+
+       ,.itlb_clear_i(fe.mem.itlb.flush_i)
+       ,.itlb_fill_v_i(fe.mem.itlb.v_i & fe.mem.itlb.w_i)
+       ,.itlb_vtag_i(fe.mem.itlb.vtag_i)
+       ,.itlb_entry_i(fe.mem.itlb.entry_i)
+
+       ,.dtlb_clear_i(be.be_mem.dtlb.flush_i)
+       ,.dtlb_fill_v_i(be.be_mem.dtlb.v_i & be.be_mem.dtlb.w_i)
+       ,.dtlb_vtag_i(be.be_mem.dtlb.vtag_i)
+       ,.dtlb_entry_i(be.be_mem.dtlb.entry_i)
+       );
+*/
+/*  bp_mem_nonsynth_tracer
+   #(.bp_params_p(bp_params_p))
+   bp_mem_tracer
+    (.clk_i(clk_i & (ExampleBlackParrotSystem.dram_trace_p == 1))
+     ,.reset_i(reset_i)
+
+     ,.mem_cmd_i(proc_mem_cmd_lo)
+     ,.mem_cmd_v_i(proc_mem_cmd_v_lo & proc_mem_cmd_ready_li)
+     ,.mem_cmd_ready_i(proc_mem_cmd_ready_li)
+
+     ,.mem_resp_i(proc_mem_resp_li)
+     ,.mem_resp_v_i(proc_mem_resp_v_li)
+     ,.mem_resp_yumi_i(proc_mem_resp_yumi_lo)
+     );
+*/
+/*bp_nonsynth_if_verif
+ #(.bp_params_p(bp_params_p))
+ if_verif
+  ();
+*/
+endmodule
+
diff --git a/litex/soc/cores/cpu/blackparrot/bp_fpga/fpga/ExampleBlackParrotSystem.v b/litex/soc/cores/cpu/blackparrot/bp_fpga/fpga/ExampleBlackParrotSystem.v
new file mode 100644
index 000000000..6e52cc209
--- /dev/null
+++ b/litex/soc/cores/cpu/blackparrot/bp_fpga/fpga/ExampleBlackParrotSystem.v
@@ -0,0 +1,357 @@
+/**
+  *
+  * ExampleBlackParrotSystem.v
+  *
+  */
+  
+`include "bsg_noc_links.vh"
+
+module ExampleBlackParrotSystem
+ import bp_common_pkg::*;
+ import bp_common_aviary_pkg::*;
+ import bp_be_pkg::*;
+ import bp_common_rv64_pkg::*;
+ import bp_cce_pkg::*;
+ import bp_me_pkg::*;
+ import bp_common_cfg_link_pkg::*;
+ import bsg_noc_pkg::*;
+ #(parameter bp_params_e bp_params_p = e_bp_softcore_cfg
+   `declare_bp_proc_params(bp_params_p)
+   `declare_bp_me_if_widths(paddr_width_p, cce_block_width_p, lce_id_width_p, lce_assoc_p)
+
+   // Tracing parameters
+   , parameter calc_trace_p                = 0
+   , parameter cce_trace_p                 = 0
+   , parameter cmt_trace_p                 = 1
+   , parameter dram_trace_p                = 1
+   , parameter npc_trace_p                 = 0
+   , parameter dcache_trace_p              = 0
+   , parameter vm_trace_p                  = 0
+   , parameter preload_mem_p               = 1
+   , parameter load_nbf_p                  = 0
+   , parameter skip_init_p                 = 0
+   , parameter cosim_p                     = 0
+   , parameter cosim_cfg_file_p            = "prog.cfg"
+
+   , parameter mem_zero_p         = 1
+   , parameter mem_file_p         = "prog.mem"
+   , parameter mem_cap_in_bytes_p = 2**25
+   , parameter [paddr_width_p-1:0] mem_offset_p = paddr_width_p'(32'h8000_0000)
+
+   // Number of elements in the fake BlackParrot memory
+   , parameter use_max_latency_p      = 1
+   , parameter use_random_latency_p   = 0
+   , parameter use_dramsim2_latency_p = 0
+
+   , parameter max_latency_p = 15
+
+   , parameter dram_clock_period_in_ps_p = 1000
+   , parameter dram_cfg_p                = "dram_ch.ini"
+   , parameter dram_sys_cfg_p            = "dram_sys.ini"
+   , parameter dram_capacity_p           = 16384
+   )
+  (input clk_i
+   , input reset_i
+      //Wishbone interface
+   , input  [63:0]  wbm_dat_i
+   , output [63:0]  wbm_dat_o
+   , input          wbm_ack_i
+   , input          wbm_err_i
+//   , input          wbm_rty_i
+   , output [36:0]  wbm_adr_o //TODO parametrize this
+   , output         wbm_stb_o
+   , output         wbm_cyc_o
+   , output [7:0]   wbm_sel_o //TODO: how many  bits ? check
+   , output         wbm_we_o
+   , output [2:0]   wbm_cti_o //TODO:
+   , output [1:0]   wbm_bte_o
+  // , input  [3:0]   interrupts
+   );
+
+`declare_bp_me_if(paddr_width_p, cce_block_width_p, lce_id_width_p, lce_assoc_p)
+
+bp_cce_mem_msg_s proc_mem_cmd_lo;
+logic proc_mem_cmd_v_lo, proc_mem_cmd_ready_li;
+bp_cce_mem_msg_s proc_mem_resp_li;
+logic proc_mem_resp_v_li, proc_mem_resp_yumi_lo;
+
+bp_cce_mem_msg_s proc_io_cmd_lo;
+logic proc_io_cmd_v_lo, proc_io_cmd_ready_li;
+bp_cce_mem_msg_s proc_io_resp_li;
+logic proc_io_resp_v_li, proc_io_resp_yumi_lo;
+
+bp_cce_mem_msg_s io_cmd_lo;
+logic io_cmd_v_lo, io_cmd_ready_li;
+bp_cce_mem_msg_s io_resp_li;
+logic io_resp_v_li, io_resp_yumi_lo;
+bp_softcore
+ #(.bp_params_p(bp_params_p))
+ softcore
+  (.clk_i(clk_i)
+   ,.reset_i(reset_i)
+
+   ,.io_cmd_o(proc_io_cmd_lo)
+   ,.io_cmd_v_o(proc_io_cmd_v_lo)
+   ,.io_cmd_ready_i(proc_io_cmd_ready_li)
+
+   ,.io_resp_i(proc_io_resp_li)
+   ,.io_resp_v_i(proc_io_resp_v_li)
+   ,.io_resp_yumi_o(proc_io_resp_yumi_lo)
+
+   ,.mem_cmd_o(proc_mem_cmd_lo)
+   ,.mem_cmd_v_o(proc_mem_cmd_v_lo)
+   ,.mem_cmd_ready_i(proc_mem_cmd_ready_li)
+
+   ,.mem_resp_i(proc_mem_resp_li)
+   ,.mem_resp_v_i(proc_mem_resp_v_li)
+   ,.mem_resp_yumi_o(proc_mem_resp_yumi_lo)
+   );
+
+ bp2wb_convertor
+   #(.bp_params_p(bp_params_p))
+   bp2wb
+    (.clk_i(clk_i)
+     ,.reset_i(reset_i)
+    ,.mem_cmd_i(proc_mem_cmd_lo)
+     ,.mem_cmd_v_i(proc_mem_cmd_v_lo & proc_mem_cmd_ready_li)
+     ,.mem_cmd_ready_o(proc_mem_cmd_ready_li)
+
+     ,.mem_resp_o(proc_mem_resp_li)
+     ,.mem_resp_v_o(proc_mem_resp_v_li)
+     ,.mem_resp_yumi_i(proc_mem_resp_yumi_lo)
+
+     ,.dat_i(wbm_dat_i)
+     ,.dat_o(wbm_dat_o)
+     ,.ack_i(wbm_ack_i)
+     ,.adr_o(wbm_adr_o)
+     ,.stb_o(wbm_stb_o)
+     ,.cyc_o(wbm_cyc_o)
+     ,.sel_o(wbm_sel_o )
+     ,.we_o(wbm_we_o)
+     ,.cti_o(wbm_cti_o)
+     ,.bte_o(wbm_bte_o )
+    // ,.rty_i(wbm_rty_i)
+     ,.err_i(wbm_err_i)
+     );
+
+/*
+bp_mem
+ mem
+  (.clk_i(clk_i)
+   ,.reset_i(reset_i)
+ 
+   ,.mem_cmd_i(proc_mem_cmd_lo)
+   ,.mem_cmd_v_i(proc_mem_cmd_v_lo & proc_mem_cmd_ready_li)
+   ,.mem_cmd_ready_o(proc_mem_cmd_ready_li)
+ 
+   ,.mem_resp_o(proc_mem_resp_li)
+   ,.mem_resp_v_o(proc_mem_resp_v_li)
+   ,.mem_resp_yumi_i(proc_mem_resp_yumi_lo)
+   );
+*/
+logic program_finish_lo;
+assign proc_io_cmd_ready_li = 1;
+/*bp_nonsynth_host
+ #(.bp_params_p(bp_params_p))
+ host
+  (.clk_i(clk_i)
+   ,.reset_i(reset_i)
+
+   ,.io_cmd_i(proc_io_cmd_lo)
+   ,.io_cmd_v_i(proc_io_cmd_v_lo & proc_io_cmd_ready_li)
+   ,.io_cmd_ready_o(proc_io_cmd_ready_li)
+
+   ,.io_resp_o(proc_io_resp_li)
+   ,.io_resp_v_o(proc_io_resp_v_li)
+   ,.io_resp_yumi_i(proc_io_resp_yumi_lo)
+
+   ,.program_finish_o(program_finish_lo)
+   );
+*/
+/*bind bp_be_top
+  bp_nonsynth_commit_tracer
+   #(.bp_params_p(bp_params_p))
+   commit_tracer
+    (.clk_i(clk_i & (ExampleBlackParrotSystem.cmt_trace_p == 1))
+     ,.reset_i(reset_i)
+     ,.freeze_i('0)
+
+     ,.mhartid_i('0)
+
+     ,.commit_v_i(be_calculator.commit_pkt.instret)
+     ,.commit_pc_i(be_calculator.commit_pkt.pc)
+     ,.commit_instr_i(be_calculator.commit_pkt.instr)
+
+     ,.rd_w_v_i(be_calculator.wb_pkt.rd_w_v)
+     ,.rd_addr_i(be_calculator.wb_pkt.rd_addr)
+     ,.rd_data_i(be_calculator.wb_pkt.rd_data)
+     );
+*/
+/*  bind bp_be_top
+    bp_nonsynth_cosim
+     #(.bp_params_p(bp_params_p))
+      cosim
+      (.clk_i(clk_i)
+       ,.reset_i(reset_i)
+       ,.en_i(ExampleBlackParrotSystem.cosim_p == 1)
+
+       ,.mhartid_i(be_checker.scheduler.int_regfile.cfg_bus.core_id)
+       // Want to pass config file as a parameter, but cannot in Verilator 4.025
+       // Parameter-resolved constants must not use dotted references
+       ,.config_file_i(ExampleBlackParrotSystem.cosim_cfg_file_p)
+
+       ,.commit_v_i(be_calculator.commit_pkt.instret)
+       ,.commit_pc_i(be_calculator.commit_pkt.pc)
+       ,.commit_instr_i(be_calculator.commit_pkt.instr)
+
+       ,.rd_w_v_i(be_calculator.wb_pkt.rd_w_v)
+       ,.rd_addr_i(be_calculator.wb_pkt.rd_addr)
+       ,.rd_data_i(be_calculator.wb_pkt.rd_data)
+
+       ,.interrupt_v_i(be_mem.csr.trap_pkt_cast_o._interrupt)
+       ,.cause_i(be_mem.csr.trap_pkt_cast_o.cause)
+       );
+*/
+/*bind bp_be_top
+  bp_be_nonsynth_perf
+   #(.bp_params_p(bp_params_p))
+   perf
+    (.clk_i(clk_i)
+     ,.reset_i(reset_i)
+
+     ,.mhartid_i(be_checker.scheduler.int_regfile.cfg_bus.core_id)
+
+     ,.fe_nop_i(be_calculator.exc_stage_r[2].fe_nop_v)
+     ,.be_nop_i(be_calculator.exc_stage_r[2].be_nop_v)
+     ,.me_nop_i(be_calculator.exc_stage_r[2].me_nop_v)
+     ,.poison_i(be_calculator.exc_stage_r[2].poison_v)
+     ,.roll_i(be_calculator.exc_stage_r[2].roll_v)
+
+     ,.instr_cmt_i(be_calculator.commit_pkt.instret)
+
+     ,.program_finish_i(ExampleBlackParrotSystem.program_finish_lo)
+     );
+*/
+ /* bind bp_be_director
+    bp_be_nonsynth_npc_tracer
+     #(.bp_params_p(bp_params_p))
+     npc_tracer
+      (.clk_i(clk_i & (ExampleBlackParrotSystem.npc_trace_p == 1))
+       ,.reset_i(reset_i)
+       ,.freeze_i('0)
+
+       ,.mhartid_i(be_checker.scheduler.int_regfile.cfg_bus.core_id)
+
+       ,.npc_w_v(npc_w_v)
+       ,.npc_n(npc_n)
+       ,.npc_r(npc_r)
+       ,.expected_npc_o(expected_npc_o)
+
+       ,.fe_cmd_i(fe_cmd)
+       ,.fe_cmd_v(fe_cmd_v)
+
+       ,.commit_pkt_i(commit_pkt)
+       );
+*/
+  /*bind bp_be_dcache
+    bp_be_nonsynth_dcache_tracer
+     #(.bp_params_p(bp_params_p))
+     dcache_tracer
+      (.clk_i(clk_i & (ExampleBlackParrotSystem.dcache_trace_p == 1))
+       ,.reset_i(reset_i)
+       ,.freeze_i('0)
+
+       ,.mhartid_i(cfg_bus_cast_i.core_id)
+
+       ,.v_tv_r(v_tv_r)
+       //,.cache_miss_i(cache_miss_i)
+
+       ,.paddr_tv_r(paddr_tv_r)
+       ,.uncached_tv_r(uncached_tv_r)
+       ,.load_op_tv_r(load_op_tv_r)
+       ,.store_op_tv_r(store_op_tv_r)
+       ,.lr_op_tv_r(lr_op_tv_r)
+       ,.sc_op_tv_r(sc_op_tv_r)
+       ,.store_data(data_tv_r)
+       ,.load_data(data_o)
+       );*/
+/*
+  bind bp_be_top
+    bp_be_nonsynth_calc_tracer
+     #(.bp_params_p(bp_params_p))
+     calc_tracer
+      (.clk_i(clk_i & (ExampleBlackParrotSystem.calc_trace_p == 1))
+       ,.reset_i(reset_i)
+       ,.freeze_i('0)
+
+       ,.mhartid_i(be_checker.scheduler.int_regfile.cfg_bus.core_id)
+
+       ,.issue_pkt_i(be_checker.scheduler.issue_pkt)
+       ,.issue_pkt_v_i(be_checker.scheduler.fe_queue_yumi_o)
+
+       ,.fe_nop_v_i(be_calculator.exc_stage_n[0].fe_nop_v)
+       ,.be_nop_v_i(be_calculator.exc_stage_n[0].be_nop_v)
+       ,.me_nop_v_i(be_calculator.exc_stage_n[0].me_nop_v)
+       ,.dispatch_pkt_i(be_calculator.dispatch_pkt)
+
+       ,.ex1_br_tgt_i(be_calculator.calc_status.ex1_npc)
+       ,.ex1_btaken_i(be_calculator.pipe_int.btaken)
+       ,.iwb_result_i(be_calculator.comp_stage_n[3])
+       ,.fwb_result_i(be_calculator.comp_stage_n[4])
+
+       ,.cmt_trace_exc_i(be_calculator.exc_stage_n[1+:5])
+
+       ,.trap_v_i(be_mem.csr.trap_pkt_cast_o._interrupt | be_mem.csr.trap_pkt_cast_o.exception)
+       ,.mtvec_i(be_mem.csr.mtvec_n)
+       ,.mtval_i(be_mem.csr.mtval_n[0+:vaddr_width_p])
+       ,.ret_v_i(be_mem.csr.trap_pkt_cast_o.eret)
+       ,.mepc_i(be_mem.csr.mepc_n[0+:vaddr_width_p])
+       ,.mcause_i(be_mem.csr.mcause_n)
+
+       ,.priv_mode_i(be_mem.csr.priv_mode_n)
+       ,.mpp_i(be_mem.csr.mstatus_n.mpp)
+       );
+
+  bind bp_core_minimal
+    bp_be_nonsynth_vm_tracer
+    #(.bp_params_p(bp_params_p))
+    vm_tracer
+      (.clk_i(clk_i & (ExampleBlackParrotSystem.vm_trace_p == 1))
+       ,.reset_i(reset_i)
+       ,.freeze_i('0)
+
+       ,.mhartid_i(be.be_checker.scheduler.int_regfile.cfg_bus.core_id)
+
+       ,.itlb_clear_i(fe.mem.itlb.flush_i)
+       ,.itlb_fill_v_i(fe.mem.itlb.v_i & fe.mem.itlb.w_i)
+       ,.itlb_vtag_i(fe.mem.itlb.vtag_i)
+       ,.itlb_entry_i(fe.mem.itlb.entry_i)
+
+       ,.dtlb_clear_i(be.be_mem.dtlb.flush_i)
+       ,.dtlb_fill_v_i(be.be_mem.dtlb.v_i & be.be_mem.dtlb.w_i)
+       ,.dtlb_vtag_i(be.be_mem.dtlb.vtag_i)
+       ,.dtlb_entry_i(be.be_mem.dtlb.entry_i)
+       );
+*/
+/*  bp_mem_nonsynth_tracer
+   #(.bp_params_p(bp_params_p))
+   bp_mem_tracer
+    (.clk_i(clk_i & (ExampleBlackParrotSystem.dram_trace_p == 1))
+     ,.reset_i(reset_i)
+
+     ,.mem_cmd_i(proc_mem_cmd_lo)
+     ,.mem_cmd_v_i(proc_mem_cmd_v_lo & proc_mem_cmd_ready_li)
+     ,.mem_cmd_ready_i(proc_mem_cmd_ready_li)
+
+     ,.mem_resp_i(proc_mem_resp_li)
+     ,.mem_resp_v_i(proc_mem_resp_v_li)
+     ,.mem_resp_yumi_i(proc_mem_resp_yumi_lo)
+     );
+*/
+/*bp_nonsynth_if_verif
+ #(.bp_params_p(bp_params_p))
+ if_verif
+  ();
+*/
+endmodule
+
diff --git a/litex/soc/cores/cpu/blackparrot/bp_fpga/simulation/ExampleBlackParrotSystem.v b/litex/soc/cores/cpu/blackparrot/bp_fpga/simulation/ExampleBlackParrotSystem.v
new file mode 100644
index 000000000..48fa4b482
--- /dev/null
+++ b/litex/soc/cores/cpu/blackparrot/bp_fpga/simulation/ExampleBlackParrotSystem.v
@@ -0,0 +1,357 @@
+/**
+  *
+  * ExampleBlackParrotSystem.v
+  *
+  */
+  
+`include "bsg_noc_links.vh"
+
+module ExampleBlackParrotSystem
+ import bp_common_pkg::*;
+ import bp_common_aviary_pkg::*;
+ import bp_be_pkg::*;
+ import bp_common_rv64_pkg::*;
+ import bp_cce_pkg::*;
+ import bp_me_pkg::*;
+ import bp_common_cfg_link_pkg::*;
+ import bsg_noc_pkg::*;
+ #(parameter bp_params_e bp_params_p = e_bp_softcore_cfg
+   `declare_bp_proc_params(bp_params_p)
+   `declare_bp_me_if_widths(paddr_width_p, cce_block_width_p, lce_id_width_p, lce_assoc_p)
+
+   // Tracing parameters
+   , parameter calc_trace_p                = 0
+   , parameter cce_trace_p                 = 0
+   , parameter cmt_trace_p                 = 1
+   , parameter dram_trace_p                = 1
+   , parameter npc_trace_p                 = 0
+   , parameter dcache_trace_p              = 0
+   , parameter vm_trace_p                  = 0
+   , parameter preload_mem_p               = 1
+   , parameter load_nbf_p                  = 0
+   , parameter skip_init_p                 = 0
+   , parameter cosim_p                     = 0
+   , parameter cosim_cfg_file_p            = "prog.cfg"
+
+   , parameter mem_zero_p         = 1
+   , parameter mem_file_p         = "prog.mem"
+   , parameter mem_cap_in_bytes_p = 2**25
+   , parameter [paddr_width_p-1:0] mem_offset_p = paddr_width_p'(32'h8000_0000)
+
+   // Number of elements in the fake BlackParrot memory
+   , parameter use_max_latency_p      = 1
+   , parameter use_random_latency_p   = 0
+   , parameter use_dramsim2_latency_p = 0
+
+   , parameter max_latency_p = 15
+
+   , parameter dram_clock_period_in_ps_p = 1000
+   , parameter dram_cfg_p                = "dram_ch.ini"
+   , parameter dram_sys_cfg_p            = "dram_sys.ini"
+   , parameter dram_capacity_p           = 16384
+   )
+  (input clk_i
+   , input reset_i
+      //Wishbone interface
+   , input  [63:0]  wbm_dat_i
+   , output [63:0]  wbm_dat_o
+   , input          wbm_ack_i
+   , input          wbm_err_i
+//   , input          wbm_rty_i
+   , output [36:0]  wbm_adr_o //TODO parametrize this
+   , output         wbm_stb_o
+   , output         wbm_cyc_o
+   , output [7:0]   wbm_sel_o //TODO: how many  bits ? check
+   , output         wbm_we_o
+   , output [2:0]   wbm_cti_o //TODO:
+   , output [1:0]   wbm_bte_o
+  // , input  [3:0]   interrupts
+   );
+
+`declare_bp_me_if(paddr_width_p, cce_block_width_p, lce_id_width_p, lce_assoc_p)
+
+bp_cce_mem_msg_s proc_mem_cmd_lo;
+logic proc_mem_cmd_v_lo, proc_mem_cmd_ready_li;
+bp_cce_mem_msg_s proc_mem_resp_li;
+logic proc_mem_resp_v_li, proc_mem_resp_yumi_lo;
+
+bp_cce_mem_msg_s proc_io_cmd_lo;
+logic proc_io_cmd_v_lo, proc_io_cmd_ready_li;
+bp_cce_mem_msg_s proc_io_resp_li;
+logic proc_io_resp_v_li, proc_io_resp_yumi_lo;
+
+bp_cce_mem_msg_s io_cmd_lo;
+logic io_cmd_v_lo, io_cmd_ready_li;
+bp_cce_mem_msg_s io_resp_li;
+logic io_resp_v_li, io_resp_yumi_lo;
+bp_softcore
+ #(.bp_params_p(bp_params_p))
+ softcore
+  (.clk_i(clk_i)
+   ,.reset_i(reset_i)
+
+   ,.io_cmd_o(proc_io_cmd_lo)
+   ,.io_cmd_v_o(proc_io_cmd_v_lo)
+   ,.io_cmd_ready_i(proc_io_cmd_ready_li)
+
+   ,.io_resp_i(proc_io_resp_li)
+   ,.io_resp_v_i(proc_io_resp_v_li)
+   ,.io_resp_yumi_o(proc_io_resp_yumi_lo)
+
+   ,.mem_cmd_o(proc_mem_cmd_lo)
+   ,.mem_cmd_v_o(proc_mem_cmd_v_lo)
+   ,.mem_cmd_ready_i(proc_mem_cmd_ready_li)
+
+   ,.mem_resp_i(proc_mem_resp_li)
+   ,.mem_resp_v_i(proc_mem_resp_v_li)
+   ,.mem_resp_yumi_o(proc_mem_resp_yumi_lo)
+   );
+
+ bp2wb_convertor
+   #(.bp_params_p(bp_params_p))
+   bp2wb
+    (.clk_i(clk_i)
+     ,.reset_i(reset_i)
+    ,.mem_cmd_i(proc_mem_cmd_lo)
+     ,.mem_cmd_v_i(proc_mem_cmd_v_lo & proc_mem_cmd_ready_li)
+     ,.mem_cmd_ready_o(proc_mem_cmd_ready_li)
+
+     ,.mem_resp_o(proc_mem_resp_li)
+     ,.mem_resp_v_o(proc_mem_resp_v_li)
+     ,.mem_resp_yumi_i(proc_mem_resp_yumi_lo)
+
+     ,.dat_i(wbm_dat_i)
+     ,.dat_o(wbm_dat_o)
+     ,.ack_i(wbm_ack_i)
+     ,.adr_o(wbm_adr_o)
+     ,.stb_o(wbm_stb_o)
+     ,.cyc_o(wbm_cyc_o)
+     ,.sel_o(wbm_sel_o )
+     ,.we_o(wbm_we_o)
+     ,.cti_o(wbm_cti_o)
+     ,.bte_o(wbm_bte_o )
+    // ,.rty_i(wbm_rty_i)
+     ,.err_i(wbm_err_i)
+     );
+
+/*
+bp_mem
+ mem
+  (.clk_i(clk_i)
+   ,.reset_i(reset_i)
+ 
+   ,.mem_cmd_i(proc_mem_cmd_lo)
+   ,.mem_cmd_v_i(proc_mem_cmd_v_lo & proc_mem_cmd_ready_li)
+   ,.mem_cmd_ready_o(proc_mem_cmd_ready_li)
+ 
+   ,.mem_resp_o(proc_mem_resp_li)
+   ,.mem_resp_v_o(proc_mem_resp_v_li)
+   ,.mem_resp_yumi_i(proc_mem_resp_yumi_lo)
+   );
+*/
+logic program_finish_lo;
+assign proc_io_cmd_ready_li = 1;
+/*bp_nonsynth_host
+ #(.bp_params_p(bp_params_p))
+ host
+  (.clk_i(clk_i)
+   ,.reset_i(reset_i)
+
+   ,.io_cmd_i(proc_io_cmd_lo)
+   ,.io_cmd_v_i(proc_io_cmd_v_lo & proc_io_cmd_ready_li)
+   ,.io_cmd_ready_o(proc_io_cmd_ready_li)
+
+   ,.io_resp_o(proc_io_resp_li)
+   ,.io_resp_v_o(proc_io_resp_v_li)
+   ,.io_resp_yumi_i(proc_io_resp_yumi_lo)
+
+   ,.program_finish_o(program_finish_lo)
+   );
+*/
+bind bp_be_top
+  bp_nonsynth_commit_tracer
+   #(.bp_params_p(bp_params_p))
+   commit_tracer
+    (.clk_i(clk_i & (ExampleBlackParrotSystem.cmt_trace_p == 1))
+     ,.reset_i(reset_i)
+     ,.freeze_i('0)
+
+     ,.mhartid_i('0)
+
+     ,.commit_v_i(be_calculator.commit_pkt.instret)
+     ,.commit_pc_i(be_calculator.commit_pkt.pc)
+     ,.commit_instr_i(be_calculator.commit_pkt.instr)
+
+     ,.rd_w_v_i(be_calculator.wb_pkt.rd_w_v)
+     ,.rd_addr_i(be_calculator.wb_pkt.rd_addr)
+     ,.rd_data_i(be_calculator.wb_pkt.rd_data)
+     );
+
+/*  bind bp_be_top
+    bp_nonsynth_cosim
+     #(.bp_params_p(bp_params_p))
+      cosim
+      (.clk_i(clk_i)
+       ,.reset_i(reset_i)
+       ,.en_i(ExampleBlackParrotSystem.cosim_p == 1)
+
+       ,.mhartid_i(be_checker.scheduler.int_regfile.cfg_bus.core_id)
+       // Want to pass config file as a parameter, but cannot in Verilator 4.025
+       // Parameter-resolved constants must not use dotted references
+       ,.config_file_i(ExampleBlackParrotSystem.cosim_cfg_file_p)
+
+       ,.commit_v_i(be_calculator.commit_pkt.instret)
+       ,.commit_pc_i(be_calculator.commit_pkt.pc)
+       ,.commit_instr_i(be_calculator.commit_pkt.instr)
+
+       ,.rd_w_v_i(be_calculator.wb_pkt.rd_w_v)
+       ,.rd_addr_i(be_calculator.wb_pkt.rd_addr)
+       ,.rd_data_i(be_calculator.wb_pkt.rd_data)
+
+       ,.interrupt_v_i(be_mem.csr.trap_pkt_cast_o._interrupt)
+       ,.cause_i(be_mem.csr.trap_pkt_cast_o.cause)
+       );
+*/
+/*bind bp_be_top
+  bp_be_nonsynth_perf
+   #(.bp_params_p(bp_params_p))
+   perf
+    (.clk_i(clk_i)
+     ,.reset_i(reset_i)
+
+     ,.mhartid_i(be_checker.scheduler.int_regfile.cfg_bus.core_id)
+
+     ,.fe_nop_i(be_calculator.exc_stage_r[2].fe_nop_v)
+     ,.be_nop_i(be_calculator.exc_stage_r[2].be_nop_v)
+     ,.me_nop_i(be_calculator.exc_stage_r[2].me_nop_v)
+     ,.poison_i(be_calculator.exc_stage_r[2].poison_v)
+     ,.roll_i(be_calculator.exc_stage_r[2].roll_v)
+
+     ,.instr_cmt_i(be_calculator.commit_pkt.instret)
+
+     ,.program_finish_i(ExampleBlackParrotSystem.program_finish_lo)
+     );
+*/
+ /* bind bp_be_director
+    bp_be_nonsynth_npc_tracer
+     #(.bp_params_p(bp_params_p))
+     npc_tracer
+      (.clk_i(clk_i & (ExampleBlackParrotSystem.npc_trace_p == 1))
+       ,.reset_i(reset_i)
+       ,.freeze_i('0)
+
+       ,.mhartid_i(be_checker.scheduler.int_regfile.cfg_bus.core_id)
+
+       ,.npc_w_v(npc_w_v)
+       ,.npc_n(npc_n)
+       ,.npc_r(npc_r)
+       ,.expected_npc_o(expected_npc_o)
+
+       ,.fe_cmd_i(fe_cmd)
+       ,.fe_cmd_v(fe_cmd_v)
+
+       ,.commit_pkt_i(commit_pkt)
+       );
+*/
+  /*bind bp_be_dcache
+    bp_be_nonsynth_dcache_tracer
+     #(.bp_params_p(bp_params_p))
+     dcache_tracer
+      (.clk_i(clk_i & (ExampleBlackParrotSystem.dcache_trace_p == 1))
+       ,.reset_i(reset_i)
+       ,.freeze_i('0)
+
+       ,.mhartid_i(cfg_bus_cast_i.core_id)
+
+       ,.v_tv_r(v_tv_r)
+       //,.cache_miss_i(cache_miss_i)
+
+       ,.paddr_tv_r(paddr_tv_r)
+       ,.uncached_tv_r(uncached_tv_r)
+       ,.load_op_tv_r(load_op_tv_r)
+       ,.store_op_tv_r(store_op_tv_r)
+       ,.lr_op_tv_r(lr_op_tv_r)
+       ,.sc_op_tv_r(sc_op_tv_r)
+       ,.store_data(data_tv_r)
+       ,.load_data(data_o)
+       );*/
+/*
+  bind bp_be_top
+    bp_be_nonsynth_calc_tracer
+     #(.bp_params_p(bp_params_p))
+     calc_tracer
+      (.clk_i(clk_i & (ExampleBlackParrotSystem.calc_trace_p == 1))
+       ,.reset_i(reset_i)
+       ,.freeze_i('0)
+
+       ,.mhartid_i(be_checker.scheduler.int_regfile.cfg_bus.core_id)
+
+       ,.issue_pkt_i(be_checker.scheduler.issue_pkt)
+       ,.issue_pkt_v_i(be_checker.scheduler.fe_queue_yumi_o)
+
+       ,.fe_nop_v_i(be_calculator.exc_stage_n[0].fe_nop_v)
+       ,.be_nop_v_i(be_calculator.exc_stage_n[0].be_nop_v)
+       ,.me_nop_v_i(be_calculator.exc_stage_n[0].me_nop_v)
+       ,.dispatch_pkt_i(be_calculator.dispatch_pkt)
+
+       ,.ex1_br_tgt_i(be_calculator.calc_status.ex1_npc)
+       ,.ex1_btaken_i(be_calculator.pipe_int.btaken)
+       ,.iwb_result_i(be_calculator.comp_stage_n[3])
+       ,.fwb_result_i(be_calculator.comp_stage_n[4])
+
+       ,.cmt_trace_exc_i(be_calculator.exc_stage_n[1+:5])
+
+       ,.trap_v_i(be_mem.csr.trap_pkt_cast_o._interrupt | be_mem.csr.trap_pkt_cast_o.exception)
+       ,.mtvec_i(be_mem.csr.mtvec_n)
+       ,.mtval_i(be_mem.csr.mtval_n[0+:vaddr_width_p])
+       ,.ret_v_i(be_mem.csr.trap_pkt_cast_o.eret)
+       ,.mepc_i(be_mem.csr.mepc_n[0+:vaddr_width_p])
+       ,.mcause_i(be_mem.csr.mcause_n)
+
+       ,.priv_mode_i(be_mem.csr.priv_mode_n)
+       ,.mpp_i(be_mem.csr.mstatus_n.mpp)
+       );
+
+  bind bp_core_minimal
+    bp_be_nonsynth_vm_tracer
+    #(.bp_params_p(bp_params_p))
+    vm_tracer
+      (.clk_i(clk_i & (ExampleBlackParrotSystem.vm_trace_p == 1))
+       ,.reset_i(reset_i)
+       ,.freeze_i('0)
+
+       ,.mhartid_i(be.be_checker.scheduler.int_regfile.cfg_bus.core_id)
+
+       ,.itlb_clear_i(fe.mem.itlb.flush_i)
+       ,.itlb_fill_v_i(fe.mem.itlb.v_i & fe.mem.itlb.w_i)
+       ,.itlb_vtag_i(fe.mem.itlb.vtag_i)
+       ,.itlb_entry_i(fe.mem.itlb.entry_i)
+
+       ,.dtlb_clear_i(be.be_mem.dtlb.flush_i)
+       ,.dtlb_fill_v_i(be.be_mem.dtlb.v_i & be.be_mem.dtlb.w_i)
+       ,.dtlb_vtag_i(be.be_mem.dtlb.vtag_i)
+       ,.dtlb_entry_i(be.be_mem.dtlb.entry_i)
+       );
+*/
+  bp_mem_nonsynth_tracer
+   #(.bp_params_p(bp_params_p))
+   bp_mem_tracer
+    (.clk_i(clk_i & (ExampleBlackParrotSystem.dram_trace_p == 1))
+     ,.reset_i(reset_i)
+
+     ,.mem_cmd_i(proc_mem_cmd_lo)
+     ,.mem_cmd_v_i(proc_mem_cmd_v_lo & proc_mem_cmd_ready_li)
+     ,.mem_cmd_ready_i(proc_mem_cmd_ready_li)
+
+     ,.mem_resp_i(proc_mem_resp_li)
+     ,.mem_resp_v_i(proc_mem_resp_v_li)
+     ,.mem_resp_yumi_i(proc_mem_resp_yumi_lo)
+     );
+
+/*bp_nonsynth_if_verif
+ #(.bp_params_p(bp_params_p))
+ if_verif
+  ();
+*/
+endmodule
+
diff --git a/litex/soc/cores/cpu/blackparrot/flist.fpga b/litex/soc/cores/cpu/blackparrot/flist.fpga
new file mode 100644
index 000000000..6ca19de8b
--- /dev/null
+++ b/litex/soc/cores/cpu/blackparrot/flist.fpga
@@ -0,0 +1,250 @@
++incdir+$BASEJUMP_STL_DIR/bsg_dataflow
++incdir+$BASEJUMP_STL_DIR/bsg_mem
++incdir+$BASEJUMP_STL_DIR/bsg_misc
++incdir+$BASEJUMP_STL_DIR/bsg_test
++incdir+$BASEJUMP_STL_DIR/bsg_noc
++incdir+$BP_COMMON_DIR/src/include
++incdir+$BP_FE_DIR/src/include
++incdir+$BP_BE_DIR/src/include
++incdir+$BP_BE_DIR/src/include/bp_be_dcache
++incdir+$BP_ME_DIR/src/include/v
++incdir+$BP_TOP_DIR/src/include
+$BASEJUMP_STL_DIR/bsg_cache/bsg_cache_pkg.v
+$BASEJUMP_STL_DIR/bsg_noc/bsg_noc_pkg.v
+$BASEJUMP_STL_DIR/bsg_noc/bsg_wormhole_router_pkg.v
+$BP_COMMON_DIR/src/include/bp_common_rv64_pkg.vh
+$BP_COMMON_DIR/src/include/bp_common_pkg.vh
+$BP_COMMON_DIR/src/include/bp_common_aviary_pkg.vh
+$BP_COMMON_DIR/src/include/bp_common_cfg_link_pkg.vh
+$BP_FE_DIR/src/include/bp_fe_icache_pkg.vh
+$BP_FE_DIR/src/include/bp_fe_pkg.vh
+$BP_BE_DIR/src/include/bp_be_pkg.vh
+$BP_BE_DIR/src/include/bp_be_dcache/bp_be_dcache_pkg.vh
+$BP_ME_DIR/src/include/v/bp_cce_pkg.v
+$BP_ME_DIR/src/include/v/bp_me_pkg.vh
+$BASEJUMP_STL_DIR/bsg_async/bsg_async_fifo.v
+$BASEJUMP_STL_DIR/bsg_async/bsg_launch_sync_sync.v
+$BASEJUMP_STL_DIR/bsg_async/bsg_async_ptr_gray.v
+$BASEJUMP_STL_DIR/bsg_cache/bsg_cache.v
+$BASEJUMP_STL_DIR/bsg_cache/bsg_cache_dma.v
+$BASEJUMP_STL_DIR/bsg_cache/bsg_cache_miss.v
+$BASEJUMP_STL_DIR/bsg_cache/bsg_cache_decode.v
+$BASEJUMP_STL_DIR/bsg_cache/bsg_cache_sbuf.v
+$BASEJUMP_STL_DIR/bsg_cache/bsg_cache_sbuf_queue.v
+$BASEJUMP_STL_DIR/bsg_dataflow/bsg_channel_tunnel.v
+$BASEJUMP_STL_DIR/bsg_dataflow/bsg_channel_tunnel_in.v
+$BASEJUMP_STL_DIR/bsg_dataflow/bsg_channel_tunnel_out.v
+$BASEJUMP_STL_DIR/bsg_dataflow/bsg_1_to_n_tagged_fifo.v
+$BASEJUMP_STL_DIR/bsg_dataflow/bsg_1_to_n_tagged.v
+$BASEJUMP_STL_DIR/bsg_dataflow/bsg_fifo_1r1w_large.v
+$BASEJUMP_STL_DIR/bsg_dataflow/bsg_fifo_1r1w_pseudo_large.v
+$BASEJUMP_STL_DIR/bsg_dataflow/bsg_fifo_1r1w_small.v
+$BASEJUMP_STL_DIR/bsg_dataflow/bsg_fifo_1r1w_small_unhardened.v
+$BASEJUMP_STL_DIR/bsg_dataflow/bsg_fifo_1rw_large.v
+$BASEJUMP_STL_DIR/bsg_dataflow/bsg_fifo_tracker.v
+$BASEJUMP_STL_DIR/bsg_dataflow/bsg_flow_counter.v
+$BASEJUMP_STL_DIR/bsg_dataflow/bsg_one_fifo.v
+$BASEJUMP_STL_DIR/bsg_dataflow/bsg_parallel_in_serial_out.v
+$BASEJUMP_STL_DIR/bsg_dataflow/bsg_parallel_in_serial_out_dynamic.v
+$BASEJUMP_STL_DIR/bsg_dataflow/bsg_round_robin_1_to_n.v
+$BASEJUMP_STL_DIR/bsg_dataflow/bsg_round_robin_2_to_2.v
+$BASEJUMP_STL_DIR/bsg_dataflow/bsg_round_robin_n_to_1.v
+$BASEJUMP_STL_DIR/bsg_dataflow/bsg_serial_in_parallel_out.v
+$BASEJUMP_STL_DIR/bsg_dataflow/bsg_serial_in_parallel_out_dynamic.v
+$BASEJUMP_STL_DIR/bsg_dataflow/bsg_serial_in_parallel_out_full.v
+$BASEJUMP_STL_DIR/bsg_dataflow/bsg_shift_reg.v
+$BASEJUMP_STL_DIR/bsg_dataflow/bsg_two_fifo.v
+$BASEJUMP_STL_DIR/bsg_mem/bsg_cam_1r1w.v
+$BASEJUMP_STL_DIR/bsg_mem/bsg_mem_1r1w.v
+$BASEJUMP_STL_DIR/bsg_mem/bsg_mem_1r1w_sync.v
+$BASEJUMP_STL_DIR/bsg_mem/bsg_mem_1r1w_sync_synth.v
+$BASEJUMP_STL_DIR/bsg_mem/bsg_mem_1r1w_synth.v
+$BASEJUMP_STL_DIR/bsg_mem/bsg_mem_1rw_sync.v
+//$BASEJUMP_STL_DIR/bsg_mem/bsg_mem_1rw_sync_mask_write_bit.v
+$BP_FPGA_DIR/bsg_mem_1rw_sync_mask_write_bit.v
+$BASEJUMP_STL_DIR/bsg_mem/bsg_mem_1rw_sync_mask_write_bit_synth.v
+$BASEJUMP_STL_DIR/bsg_mem/bsg_mem_1rw_sync_mask_write_byte.v
+$BASEJUMP_STL_DIR/bsg_mem/bsg_mem_1rw_sync_mask_write_byte_synth.v
+$BASEJUMP_STL_DIR/bsg_mem/bsg_mem_1rw_sync_synth.v
+$BASEJUMP_STL_DIR/bsg_mem/bsg_mem_2r1w_sync.v
+$BASEJUMP_STL_DIR/bsg_mem/bsg_mem_2r1w_sync_synth.v
+$BASEJUMP_STL_DIR/bsg_misc/bsg_adder_ripple_carry.v
+$BASEJUMP_STL_DIR/bsg_misc/bsg_arb_fixed.v
+$BASEJUMP_STL_DIR/bsg_misc/bsg_array_concentrate_static.v
+$BASEJUMP_STL_DIR/bsg_misc/bsg_buf.v
+$BASEJUMP_STL_DIR/bsg_misc/bsg_circular_ptr.v
+$BASEJUMP_STL_DIR/bsg_misc/bsg_concentrate_static.v
+$BASEJUMP_STL_DIR/bsg_misc/bsg_counter_clear_up.v
+$BASEJUMP_STL_DIR/bsg_misc/bsg_counter_set_down.v
+$BASEJUMP_STL_DIR/bsg_misc/bsg_counter_set_en.v
+$BASEJUMP_STL_DIR/bsg_misc/bsg_counter_up_down.v
+$BASEJUMP_STL_DIR/bsg_misc/bsg_counter_up_down_variable.v
+$BASEJUMP_STL_DIR/bsg_misc/bsg_crossbar_o_by_i.v
+$BASEJUMP_STL_DIR/bsg_misc/bsg_cycle_counter.v
+$BASEJUMP_STL_DIR/bsg_misc/bsg_decode.v
+$BASEJUMP_STL_DIR/bsg_misc/bsg_decode_with_v.v
+$BASEJUMP_STL_DIR/bsg_misc/bsg_dff.v
+$BASEJUMP_STL_DIR/bsg_misc/bsg_dff_en_bypass.v
+$BASEJUMP_STL_DIR/bsg_misc/bsg_dff_reset_en_bypass.v
+$BASEJUMP_STL_DIR/bsg_misc/bsg_dff_chain.v
+$BASEJUMP_STL_DIR/bsg_misc/bsg_dff_en.v
+$BASEJUMP_STL_DIR/bsg_misc/bsg_dff_reset.v
+$BASEJUMP_STL_DIR/bsg_misc/bsg_dff_reset_en.v
+$BASEJUMP_STL_DIR/bsg_misc/bsg_edge_detect.v
+$BASEJUMP_STL_DIR/bsg_misc/bsg_encode_one_hot.v
+$BASEJUMP_STL_DIR/bsg_misc/bsg_expand_bitmask.v
+$BASEJUMP_STL_DIR/bsg_misc/bsg_hash_bank.v
+$BASEJUMP_STL_DIR/bsg_misc/bsg_hash_bank_reverse.v
+$BASEJUMP_STL_DIR/bsg_misc/bsg_lfsr.v
+$BASEJUMP_STL_DIR/bsg_misc/bsg_lru_pseudo_tree_decode.v
+$BASEJUMP_STL_DIR/bsg_misc/bsg_lru_pseudo_tree_encode.v
+$BASEJUMP_STL_DIR/bsg_misc/bsg_mux.v
+$BASEJUMP_STL_DIR/bsg_misc/bsg_mux_butterfly.v
+$BASEJUMP_STL_DIR/bsg_misc/bsg_mux_one_hot.v
+$BASEJUMP_STL_DIR/bsg_misc/bsg_mux_segmented.v
+$BASEJUMP_STL_DIR/bsg_misc/bsg_muxi2_gatestack.v
+$BASEJUMP_STL_DIR/bsg_misc/bsg_nor3.v
+$BASEJUMP_STL_DIR/bsg_misc/bsg_nand.v
+$BASEJUMP_STL_DIR/bsg_misc/bsg_priority_encode.v
+$BASEJUMP_STL_DIR/bsg_misc/bsg_priority_encode_one_hot_out.v
+$BASEJUMP_STL_DIR/bsg_misc/bsg_reduce.v
+$BASEJUMP_STL_DIR/bsg_misc/bsg_reduce_segmented.v
+$BASEJUMP_STL_DIR/bsg_misc/bsg_round_robin_arb.v
+$BASEJUMP_STL_DIR/bsg_misc/bsg_scan.v
+$BASEJUMP_STL_DIR/bsg_misc/bsg_strobe.v
+$BASEJUMP_STL_DIR/bsg_misc/bsg_swap.v
+$BASEJUMP_STL_DIR/bsg_misc/bsg_thermometer_count.v
+$BASEJUMP_STL_DIR/bsg_misc/bsg_transpose.v
+$BASEJUMP_STL_DIR/bsg_misc/bsg_unconcentrate_static.v
+$BASEJUMP_STL_DIR/bsg_misc/bsg_xnor.v
+$BASEJUMP_STL_DIR/bsg_noc/bsg_mesh_stitch.v
+$BASEJUMP_STL_DIR/bsg_noc/bsg_noc_repeater_node.v
+$BASEJUMP_STL_DIR/bsg_noc/bsg_wormhole_concentrator.v
+$BASEJUMP_STL_DIR/bsg_noc/bsg_wormhole_concentrator_in.v
+$BASEJUMP_STL_DIR/bsg_noc/bsg_wormhole_concentrator_out.v
+$BASEJUMP_STL_DIR/bsg_noc/bsg_wormhole_router.v
+$BASEJUMP_STL_DIR/bsg_noc/bsg_wormhole_router_adapter.v
+$BASEJUMP_STL_DIR/bsg_noc/bsg_wormhole_router_adapter_in.v
+$BASEJUMP_STL_DIR/bsg_noc/bsg_wormhole_router_adapter_out.v
+$BASEJUMP_STL_DIR/bsg_noc/bsg_wormhole_router_decoder_dor.v
+$BASEJUMP_STL_DIR/bsg_noc/bsg_wormhole_router_input_control.v  
+$BASEJUMP_STL_DIR/bsg_noc/bsg_wormhole_router_output_control.v 
+$BP_COMMON_DIR/src/v/bsg_fifo_1r1w_rolly.v
+$BP_COMMON_DIR/src/v/bp_pma.v
+$BP_COMMON_DIR/src/v/bp_tlb.v
+$BP_COMMON_DIR/src/v/bp_tlb_replacement.v
+$BP_BE_DIR/src/v/bp_be_top.v
+$BP_BE_DIR/src/v/bp_be_calculator/bp_be_bypass.v
+$BP_BE_DIR/src/v/bp_be_calculator/bp_be_calculator_top.v
+$BP_BE_DIR/src/v/bp_be_calculator/bp_be_instr_decoder.v
+$BP_BE_DIR/src/v/bp_be_calculator/bp_be_int_alu.v
+$BP_BE_DIR/src/v/bp_be_calculator/bp_be_pipe_fp.v
+$BP_BE_DIR/src/v/bp_be_calculator/bp_be_pipe_int.v
+$BP_BE_DIR/src/v/bp_be_calculator/bp_be_pipe_mem.v
+$BP_BE_DIR/src/v/bp_be_calculator/bp_be_pipe_mul.v
+$BP_BE_DIR/src/v/bp_be_calculator/bp_be_regfile.v
+$BP_BE_DIR/src/v/bp_be_checker/bp_be_checker_top.v
+$BP_BE_DIR/src/v/bp_be_checker/bp_be_detector.v
+$BP_BE_DIR/src/v/bp_be_checker/bp_be_director.v
+$BP_BE_DIR/src/v/bp_be_checker/bp_be_scheduler.v
+$BP_BE_DIR/src/v/bp_be_mem/bp_be_ptw.v
+$BP_BE_DIR/src/v/bp_be_mem/bp_be_csr.v
+$BP_BE_DIR/src/v/bp_be_mem/bp_be_dcache/bp_be_dcache.v
+$BP_BE_DIR/src/v/bp_be_mem/bp_be_dcache/bp_be_dcache_lce_cmd.v
+$BP_BE_DIR/src/v/bp_be_mem/bp_be_dcache/bp_be_dcache_lce.v
+$BP_BE_DIR/src/v/bp_be_mem/bp_be_dcache/bp_be_dcache_lce_req.v
+$BP_BE_DIR/src/v/bp_be_mem/bp_be_dcache/bp_be_dcache_wbuf.v
+$BP_BE_DIR/src/v/bp_be_mem/bp_be_dcache/bp_be_dcache_wbuf_queue.v
+$BP_BE_DIR/src/v/bp_be_mem/bp_be_mem_top.v
+$BP_FE_DIR/src/v/bp_fe_bht.v
+$BP_FE_DIR/src/v/bp_fe_btb.v
+$BP_FE_DIR/src/v/bp_fe_lce_cmd.v
+$BP_FE_DIR/src/v/bp_fe_icache.v
+$BP_FE_DIR/src/v/bp_fe_instr_scan.v
+$BP_FE_DIR/src/v/bp_fe_lce.v
+$BP_FE_DIR/src/v/bp_fe_lce_req.v
+$BP_FE_DIR/src/v/bp_fe_mem.v
+$BP_FE_DIR/src/v/bp_fe_pc_gen.v
+$BP_FE_DIR/src/v/bp_fe_top.v
+$BP_ME_DIR/src/v/cache/bp_me_cache_dma_to_cce.v
+$BP_ME_DIR/src/v/cache/bp_me_cache_slice.v
+$BP_ME_DIR/src/v/cache/bp_me_cce_to_cache.v
+$BP_ME_DIR/src/v/cache/bp_me_cce_to_cache_buffered.v
+$BP_ME_DIR/src/v/cce/bp_cce.v
+$BP_ME_DIR/src/v/cce/bp_cce_alu.v
+$BP_ME_DIR/src/v/cce/bp_cce_buffered.v
+$BP_ME_DIR/src/v/cce/bp_cce_dir.v
+$BP_ME_DIR/src/v/cce/bp_cce_dir_tag_checker.v
+$BP_ME_DIR/src/v/cce/bp_cce_dir_lru_extract.v
+$BP_ME_DIR/src/v/cce/bp_cce_gad.v
+$BP_ME_DIR/src/v/cce/bp_cce_inst_decode.v
+$BP_ME_DIR/src/v/cce/bp_cce_msg.v
+$BP_ME_DIR/src/v/cce/bp_cce_msg_cached.v
+$BP_ME_DIR/src/v/cce/bp_cce_msg_uncached.v
+$BP_ME_DIR/src/v/cce/bp_cce_pc.v
+$BP_ME_DIR/src/v/cce/bp_cce_pending.v
+$BP_ME_DIR/src/v/cce/bp_cce_reg.v
+$BP_ME_DIR/src/v/cce/bp_cce_spec.v
+$BP_ME_DIR/src/v/cce/bp_io_cce.v
+$BP_ME_DIR/src/v/cce/bp_uce.v
+$BP_ME_DIR/src/v/wormhole/bp_me_addr_to_cce_id.v
+$BP_ME_DIR/src/v/wormhole/bp_me_cce_id_to_cord.v
+$BP_ME_DIR/src/v/wormhole/bp_me_cce_to_mem_link_bidir.v
+$BP_ME_DIR/src/v/wormhole/bp_me_cce_to_mem_link_client.v
+$BP_ME_DIR/src/v/wormhole/bp_me_cce_to_mem_link_master.v
+$BP_ME_DIR/src/v/wormhole/bp_me_cord_to_id.v
+$BP_ME_DIR/src/v/wormhole/bp_me_lce_id_to_cord.v
+$BP_ME_DIR/src/v/wormhole/bp_me_wormhole_packet_encode_lce_cmd.v
+$BP_ME_DIR/src/v/wormhole/bp_me_wormhole_packet_encode_lce_req.v
+$BP_ME_DIR/src/v/wormhole/bp_me_wormhole_packet_encode_lce_resp.v
+$BP_ME_DIR/src/v/wormhole/bp_me_wormhole_packet_encode_mem_cmd.v
+$BP_ME_DIR/src/v/wormhole/bp_me_wormhole_packet_encode_mem_resp.v
+//$BP_TOP_DIR/src/v/bp_accelerator_complex.v
+$BP_TOP_DIR/src/v/bp_cfg.v
+$BP_TOP_DIR/src/v/bp_cfg_buffered.v
+$BP_TOP_DIR/src/v/bp_core.v
+//$BP_TOP_DIR/src/v/bp_core_complex.v
+$BP_TOP_DIR/src/v/bp_core_minimal.v
+//$BP_TOP_DIR/src/v/bp_clint.v
+$BP_TOP_DIR/src/v/bp_clint_node.v
+$BP_TOP_DIR/src/v/bp_clint_slice.v
+$BP_TOP_DIR/src/v/bp_clint_slice_buffered.v
+//$BP_TOP_DIR/src/v/bp_l2e_tile.v
+//$BP_TOP_DIR/src/v/bp_l2e_tile_node.v
+$BP_TOP_DIR/src/v/bp_io_complex.v
+$BP_TOP_DIR/src/v/bp_io_link_to_lce.v
+$BP_TOP_DIR/src/v/bp_io_tile.v
+$BP_TOP_DIR/src/v/bp_io_tile_node.v
+$BP_TOP_DIR/src/v/bp_mem_complex.v
+//$BP_TOP_DIR/src/v/bp_processor.v
+$BP_TOP_DIR/src/v/bp_softcore.v
+//$BP_TOP_DIR/src/v/bp_tile.v
+//$BP_TOP_DIR/src/v/bp_tile_node.v
+$BP_TOP_DIR/src/v/bsg_async_noc_link.v
+//$BASEJUMP_STL_DIR/bsg_test/bsg_nonsynth_reset_gen.v
+//$BASEJUMP_STL_DIR/bsg_test/bsg_nonsynth_clock_gen.v
+//$BASEJUMP_STL_DIR/bsg_fsb/bsg_fsb_node_trace_replay.v
+//$BP_BE_DIR/test/common/bp_be_nonsynth_calc_tracer.v
+//$BP_BE_DIR/test/common/bp_be_nonsynth_dcache_tracer.v
+//$BP_BE_DIR/test/common/bp_be_nonsynth_perf.v
+//$BP_BE_DIR/test/common/bp_be_nonsynth_npc_tracer.v
+//$BP_BE_DIR/test/common/bp_be_nonsynth_vm_tracer.v
+//$BP_ME_DIR/test/common/bp_mem.v
+//$BP_ME_DIR/test/common/bp_mem_transducer.v
+//$BP_ME_DIR/test/common/bp_mem_delay_model.v
+//$BP_ME_DIR/test/common/bp_mem_storage_sync.v
+//$BP_ME_DIR/test/common/bp_cce_mmio_cfg_loader.v
+//$BP_ME_DIR/test/common/dramsim2_wrapper.cpp
+//$BP_ME_DIR/test/common/bp_mem_utils.cpp
+//$BP_ME_DIR/test/common/bp_cce_nonsynth_tracer.v
+$BP_ME_DIR/test/common/bp_mem_nonsynth_tracer.v
+//$BP_TOP_DIR/test/common/bp_nonsynth_cosim.v
+//$BP_TOP_DIR/test/common/bp_nonsynth_host.v
+//$BP_TOP_DIR/test/common/bp_nonsynth_if_verif.v
+$BP_TOP_DIR/test/common/bp_nonsynth_commit_tracer.v
+//$BP_TOP_DIR/test/common/bp_nonsynth_nbf_loader.v
+//$BP_TOP_DIR/test/common/bp_monitor.cpp
+//$BP_TOP_DIR/test/common/dromajo_cosim.cpp
+//$BP_FPGA_DIR/wrapper.v
+$BP_FPGA_DIR/bp2wb_convertor.v
+$BP_FPGA_DIR/fpga/ExampleBlackParrotSystem.v
diff --git a/litex/soc/cores/cpu/blackparrot/flist.verilator b/litex/soc/cores/cpu/blackparrot/flist.verilator
new file mode 100644
index 000000000..551f5ea5d
--- /dev/null
+++ b/litex/soc/cores/cpu/blackparrot/flist.verilator
@@ -0,0 +1,250 @@
++incdir+$BASEJUMP_STL_DIR/bsg_dataflow
++incdir+$BASEJUMP_STL_DIR/bsg_mem
++incdir+$BASEJUMP_STL_DIR/bsg_misc
++incdir+$BASEJUMP_STL_DIR/bsg_test
++incdir+$BASEJUMP_STL_DIR/bsg_noc
++incdir+$BP_COMMON_DIR/src/include
++incdir+$BP_FE_DIR/src/include
++incdir+$BP_BE_DIR/src/include
++incdir+$BP_BE_DIR/src/include/bp_be_dcache
++incdir+$BP_ME_DIR/src/include/v
++incdir+$BP_TOP_DIR/src/include
+$BASEJUMP_STL_DIR/bsg_cache/bsg_cache_pkg.v
+$BASEJUMP_STL_DIR/bsg_noc/bsg_noc_pkg.v
+$BASEJUMP_STL_DIR/bsg_noc/bsg_wormhole_router_pkg.v
+$BP_COMMON_DIR/src/include/bp_common_rv64_pkg.vh
+$BP_COMMON_DIR/src/include/bp_common_pkg.vh
+$BP_COMMON_DIR/src/include/bp_common_aviary_pkg.vh
+$BP_COMMON_DIR/src/include/bp_common_cfg_link_pkg.vh
+$BP_FE_DIR/src/include/bp_fe_icache_pkg.vh
+$BP_FE_DIR/src/include/bp_fe_pkg.vh
+$BP_BE_DIR/src/include/bp_be_pkg.vh
+$BP_BE_DIR/src/include/bp_be_dcache/bp_be_dcache_pkg.vh
+$BP_ME_DIR/src/include/v/bp_cce_pkg.v
+$BP_ME_DIR/src/include/v/bp_me_pkg.vh
+$BASEJUMP_STL_DIR/bsg_async/bsg_async_fifo.v
+$BASEJUMP_STL_DIR/bsg_async/bsg_launch_sync_sync.v
+$BASEJUMP_STL_DIR/bsg_async/bsg_async_ptr_gray.v
+$BASEJUMP_STL_DIR/bsg_cache/bsg_cache.v
+$BASEJUMP_STL_DIR/bsg_cache/bsg_cache_dma.v
+$BASEJUMP_STL_DIR/bsg_cache/bsg_cache_miss.v
+$BASEJUMP_STL_DIR/bsg_cache/bsg_cache_decode.v
+$BASEJUMP_STL_DIR/bsg_cache/bsg_cache_sbuf.v
+$BASEJUMP_STL_DIR/bsg_cache/bsg_cache_sbuf_queue.v
+$BASEJUMP_STL_DIR/bsg_dataflow/bsg_channel_tunnel.v
+$BASEJUMP_STL_DIR/bsg_dataflow/bsg_channel_tunnel_in.v
+$BASEJUMP_STL_DIR/bsg_dataflow/bsg_channel_tunnel_out.v
+$BASEJUMP_STL_DIR/bsg_dataflow/bsg_1_to_n_tagged_fifo.v
+$BASEJUMP_STL_DIR/bsg_dataflow/bsg_1_to_n_tagged.v
+$BASEJUMP_STL_DIR/bsg_dataflow/bsg_fifo_1r1w_large.v
+$BASEJUMP_STL_DIR/bsg_dataflow/bsg_fifo_1r1w_pseudo_large.v
+$BASEJUMP_STL_DIR/bsg_dataflow/bsg_fifo_1r1w_small.v
+$BASEJUMP_STL_DIR/bsg_dataflow/bsg_fifo_1r1w_small_unhardened.v
+$BASEJUMP_STL_DIR/bsg_dataflow/bsg_fifo_1rw_large.v
+$BASEJUMP_STL_DIR/bsg_dataflow/bsg_fifo_tracker.v
+$BASEJUMP_STL_DIR/bsg_dataflow/bsg_flow_counter.v
+$BASEJUMP_STL_DIR/bsg_dataflow/bsg_one_fifo.v
+$BASEJUMP_STL_DIR/bsg_dataflow/bsg_parallel_in_serial_out.v
+$BASEJUMP_STL_DIR/bsg_dataflow/bsg_parallel_in_serial_out_dynamic.v
+$BASEJUMP_STL_DIR/bsg_dataflow/bsg_round_robin_1_to_n.v
+$BASEJUMP_STL_DIR/bsg_dataflow/bsg_round_robin_2_to_2.v
+$BASEJUMP_STL_DIR/bsg_dataflow/bsg_round_robin_n_to_1.v
+$BASEJUMP_STL_DIR/bsg_dataflow/bsg_serial_in_parallel_out.v
+$BASEJUMP_STL_DIR/bsg_dataflow/bsg_serial_in_parallel_out_dynamic.v
+$BASEJUMP_STL_DIR/bsg_dataflow/bsg_serial_in_parallel_out_full.v
+$BASEJUMP_STL_DIR/bsg_dataflow/bsg_shift_reg.v
+$BASEJUMP_STL_DIR/bsg_dataflow/bsg_two_fifo.v
+$BASEJUMP_STL_DIR/bsg_mem/bsg_cam_1r1w.v
+$BASEJUMP_STL_DIR/bsg_mem/bsg_mem_1r1w.v
+$BASEJUMP_STL_DIR/bsg_mem/bsg_mem_1r1w_sync.v
+$BASEJUMP_STL_DIR/bsg_mem/bsg_mem_1r1w_sync_synth.v
+$BASEJUMP_STL_DIR/bsg_mem/bsg_mem_1r1w_synth.v
+$BASEJUMP_STL_DIR/bsg_mem/bsg_mem_1rw_sync.v
+//$BASEJUMP_STL_DIR/bsg_mem/bsg_mem_1rw_sync_mask_write_bit.v
+$BP_FPGA_DIR/bsg_mem_1rw_sync_mask_write_bit.v
+$BASEJUMP_STL_DIR/bsg_mem/bsg_mem_1rw_sync_mask_write_bit_synth.v
+$BASEJUMP_STL_DIR/bsg_mem/bsg_mem_1rw_sync_mask_write_byte.v
+$BASEJUMP_STL_DIR/bsg_mem/bsg_mem_1rw_sync_mask_write_byte_synth.v
+$BASEJUMP_STL_DIR/bsg_mem/bsg_mem_1rw_sync_synth.v
+$BASEJUMP_STL_DIR/bsg_mem/bsg_mem_2r1w_sync.v
+$BASEJUMP_STL_DIR/bsg_mem/bsg_mem_2r1w_sync_synth.v
+$BASEJUMP_STL_DIR/bsg_misc/bsg_adder_ripple_carry.v
+$BASEJUMP_STL_DIR/bsg_misc/bsg_arb_fixed.v
+$BASEJUMP_STL_DIR/bsg_misc/bsg_array_concentrate_static.v
+$BASEJUMP_STL_DIR/bsg_misc/bsg_buf.v
+$BASEJUMP_STL_DIR/bsg_misc/bsg_circular_ptr.v
+$BASEJUMP_STL_DIR/bsg_misc/bsg_concentrate_static.v
+$BASEJUMP_STL_DIR/bsg_misc/bsg_counter_clear_up.v
+$BASEJUMP_STL_DIR/bsg_misc/bsg_counter_set_down.v
+$BASEJUMP_STL_DIR/bsg_misc/bsg_counter_set_en.v
+$BASEJUMP_STL_DIR/bsg_misc/bsg_counter_up_down.v
+$BASEJUMP_STL_DIR/bsg_misc/bsg_counter_up_down_variable.v
+$BASEJUMP_STL_DIR/bsg_misc/bsg_crossbar_o_by_i.v
+$BASEJUMP_STL_DIR/bsg_misc/bsg_cycle_counter.v
+$BASEJUMP_STL_DIR/bsg_misc/bsg_decode.v
+$BASEJUMP_STL_DIR/bsg_misc/bsg_decode_with_v.v
+$BASEJUMP_STL_DIR/bsg_misc/bsg_dff.v
+$BASEJUMP_STL_DIR/bsg_misc/bsg_dff_en_bypass.v
+$BASEJUMP_STL_DIR/bsg_misc/bsg_dff_reset_en_bypass.v
+$BASEJUMP_STL_DIR/bsg_misc/bsg_dff_chain.v
+$BASEJUMP_STL_DIR/bsg_misc/bsg_dff_en.v
+$BASEJUMP_STL_DIR/bsg_misc/bsg_dff_reset.v
+$BASEJUMP_STL_DIR/bsg_misc/bsg_dff_reset_en.v
+$BASEJUMP_STL_DIR/bsg_misc/bsg_edge_detect.v
+$BASEJUMP_STL_DIR/bsg_misc/bsg_encode_one_hot.v
+$BASEJUMP_STL_DIR/bsg_misc/bsg_expand_bitmask.v
+$BASEJUMP_STL_DIR/bsg_misc/bsg_hash_bank.v
+$BASEJUMP_STL_DIR/bsg_misc/bsg_hash_bank_reverse.v
+$BASEJUMP_STL_DIR/bsg_misc/bsg_lfsr.v
+$BASEJUMP_STL_DIR/bsg_misc/bsg_lru_pseudo_tree_decode.v
+$BASEJUMP_STL_DIR/bsg_misc/bsg_lru_pseudo_tree_encode.v
+$BASEJUMP_STL_DIR/bsg_misc/bsg_mux.v
+$BASEJUMP_STL_DIR/bsg_misc/bsg_mux_butterfly.v
+$BASEJUMP_STL_DIR/bsg_misc/bsg_mux_one_hot.v
+$BASEJUMP_STL_DIR/bsg_misc/bsg_mux_segmented.v
+$BASEJUMP_STL_DIR/bsg_misc/bsg_muxi2_gatestack.v
+$BASEJUMP_STL_DIR/bsg_misc/bsg_nor3.v
+$BASEJUMP_STL_DIR/bsg_misc/bsg_nand.v
+$BASEJUMP_STL_DIR/bsg_misc/bsg_priority_encode.v
+$BASEJUMP_STL_DIR/bsg_misc/bsg_priority_encode_one_hot_out.v
+$BASEJUMP_STL_DIR/bsg_misc/bsg_reduce.v
+$BASEJUMP_STL_DIR/bsg_misc/bsg_reduce_segmented.v
+$BASEJUMP_STL_DIR/bsg_misc/bsg_round_robin_arb.v
+$BASEJUMP_STL_DIR/bsg_misc/bsg_scan.v
+$BASEJUMP_STL_DIR/bsg_misc/bsg_strobe.v
+$BASEJUMP_STL_DIR/bsg_misc/bsg_swap.v
+$BASEJUMP_STL_DIR/bsg_misc/bsg_thermometer_count.v
+$BASEJUMP_STL_DIR/bsg_misc/bsg_transpose.v
+$BASEJUMP_STL_DIR/bsg_misc/bsg_unconcentrate_static.v
+$BASEJUMP_STL_DIR/bsg_misc/bsg_xnor.v
+$BASEJUMP_STL_DIR/bsg_noc/bsg_mesh_stitch.v
+$BASEJUMP_STL_DIR/bsg_noc/bsg_noc_repeater_node.v
+$BASEJUMP_STL_DIR/bsg_noc/bsg_wormhole_concentrator.v
+$BASEJUMP_STL_DIR/bsg_noc/bsg_wormhole_concentrator_in.v
+$BASEJUMP_STL_DIR/bsg_noc/bsg_wormhole_concentrator_out.v
+$BASEJUMP_STL_DIR/bsg_noc/bsg_wormhole_router.v
+$BASEJUMP_STL_DIR/bsg_noc/bsg_wormhole_router_adapter.v
+$BASEJUMP_STL_DIR/bsg_noc/bsg_wormhole_router_adapter_in.v
+$BASEJUMP_STL_DIR/bsg_noc/bsg_wormhole_router_adapter_out.v
+$BASEJUMP_STL_DIR/bsg_noc/bsg_wormhole_router_decoder_dor.v
+$BASEJUMP_STL_DIR/bsg_noc/bsg_wormhole_router_input_control.v  
+$BASEJUMP_STL_DIR/bsg_noc/bsg_wormhole_router_output_control.v 
+$BP_COMMON_DIR/src/v/bsg_fifo_1r1w_rolly.v
+$BP_COMMON_DIR/src/v/bp_pma.v
+$BP_COMMON_DIR/src/v/bp_tlb.v
+$BP_COMMON_DIR/src/v/bp_tlb_replacement.v
+$BP_BE_DIR/src/v/bp_be_top.v
+$BP_BE_DIR/src/v/bp_be_calculator/bp_be_bypass.v
+$BP_BE_DIR/src/v/bp_be_calculator/bp_be_calculator_top.v
+$BP_BE_DIR/src/v/bp_be_calculator/bp_be_instr_decoder.v
+$BP_BE_DIR/src/v/bp_be_calculator/bp_be_int_alu.v
+$BP_BE_DIR/src/v/bp_be_calculator/bp_be_pipe_fp.v
+$BP_BE_DIR/src/v/bp_be_calculator/bp_be_pipe_int.v
+$BP_BE_DIR/src/v/bp_be_calculator/bp_be_pipe_mem.v
+$BP_BE_DIR/src/v/bp_be_calculator/bp_be_pipe_mul.v
+$BP_BE_DIR/src/v/bp_be_calculator/bp_be_regfile.v
+$BP_BE_DIR/src/v/bp_be_checker/bp_be_checker_top.v
+$BP_BE_DIR/src/v/bp_be_checker/bp_be_detector.v
+$BP_BE_DIR/src/v/bp_be_checker/bp_be_director.v
+$BP_BE_DIR/src/v/bp_be_checker/bp_be_scheduler.v
+$BP_BE_DIR/src/v/bp_be_mem/bp_be_ptw.v
+$BP_BE_DIR/src/v/bp_be_mem/bp_be_csr.v
+$BP_BE_DIR/src/v/bp_be_mem/bp_be_dcache/bp_be_dcache.v
+$BP_BE_DIR/src/v/bp_be_mem/bp_be_dcache/bp_be_dcache_lce_cmd.v
+$BP_BE_DIR/src/v/bp_be_mem/bp_be_dcache/bp_be_dcache_lce.v
+$BP_BE_DIR/src/v/bp_be_mem/bp_be_dcache/bp_be_dcache_lce_req.v
+$BP_BE_DIR/src/v/bp_be_mem/bp_be_dcache/bp_be_dcache_wbuf.v
+$BP_BE_DIR/src/v/bp_be_mem/bp_be_dcache/bp_be_dcache_wbuf_queue.v
+$BP_BE_DIR/src/v/bp_be_mem/bp_be_mem_top.v
+$BP_FE_DIR/src/v/bp_fe_bht.v
+$BP_FE_DIR/src/v/bp_fe_btb.v
+$BP_FE_DIR/src/v/bp_fe_lce_cmd.v
+$BP_FE_DIR/src/v/bp_fe_icache.v
+$BP_FE_DIR/src/v/bp_fe_instr_scan.v
+$BP_FE_DIR/src/v/bp_fe_lce.v
+$BP_FE_DIR/src/v/bp_fe_lce_req.v
+$BP_FE_DIR/src/v/bp_fe_mem.v
+$BP_FE_DIR/src/v/bp_fe_pc_gen.v
+$BP_FE_DIR/src/v/bp_fe_top.v
+$BP_ME_DIR/src/v/cache/bp_me_cache_dma_to_cce.v
+$BP_ME_DIR/src/v/cache/bp_me_cache_slice.v
+$BP_ME_DIR/src/v/cache/bp_me_cce_to_cache.v
+$BP_ME_DIR/src/v/cache/bp_me_cce_to_cache_buffered.v
+$BP_ME_DIR/src/v/cce/bp_cce.v
+$BP_ME_DIR/src/v/cce/bp_cce_alu.v
+$BP_ME_DIR/src/v/cce/bp_cce_buffered.v
+$BP_ME_DIR/src/v/cce/bp_cce_dir.v
+$BP_ME_DIR/src/v/cce/bp_cce_dir_tag_checker.v
+$BP_ME_DIR/src/v/cce/bp_cce_dir_lru_extract.v
+$BP_ME_DIR/src/v/cce/bp_cce_gad.v
+$BP_ME_DIR/src/v/cce/bp_cce_inst_decode.v
+$BP_ME_DIR/src/v/cce/bp_cce_msg.v
+$BP_ME_DIR/src/v/cce/bp_cce_msg_cached.v
+$BP_ME_DIR/src/v/cce/bp_cce_msg_uncached.v
+$BP_ME_DIR/src/v/cce/bp_cce_pc.v
+$BP_ME_DIR/src/v/cce/bp_cce_pending.v
+$BP_ME_DIR/src/v/cce/bp_cce_reg.v
+$BP_ME_DIR/src/v/cce/bp_cce_spec.v
+$BP_ME_DIR/src/v/cce/bp_io_cce.v
+$BP_ME_DIR/src/v/cce/bp_uce.v
+$BP_ME_DIR/src/v/wormhole/bp_me_addr_to_cce_id.v
+$BP_ME_DIR/src/v/wormhole/bp_me_cce_id_to_cord.v
+$BP_ME_DIR/src/v/wormhole/bp_me_cce_to_mem_link_bidir.v
+$BP_ME_DIR/src/v/wormhole/bp_me_cce_to_mem_link_client.v
+$BP_ME_DIR/src/v/wormhole/bp_me_cce_to_mem_link_master.v
+$BP_ME_DIR/src/v/wormhole/bp_me_cord_to_id.v
+$BP_ME_DIR/src/v/wormhole/bp_me_lce_id_to_cord.v
+$BP_ME_DIR/src/v/wormhole/bp_me_wormhole_packet_encode_lce_cmd.v
+$BP_ME_DIR/src/v/wormhole/bp_me_wormhole_packet_encode_lce_req.v
+$BP_ME_DIR/src/v/wormhole/bp_me_wormhole_packet_encode_lce_resp.v
+$BP_ME_DIR/src/v/wormhole/bp_me_wormhole_packet_encode_mem_cmd.v
+$BP_ME_DIR/src/v/wormhole/bp_me_wormhole_packet_encode_mem_resp.v
+//$BP_TOP_DIR/src/v/bp_accelerator_complex.v
+$BP_TOP_DIR/src/v/bp_cfg.v
+$BP_TOP_DIR/src/v/bp_cfg_buffered.v
+$BP_TOP_DIR/src/v/bp_core.v
+//$BP_TOP_DIR/src/v/bp_core_complex.v
+$BP_TOP_DIR/src/v/bp_core_minimal.v
+//$BP_TOP_DIR/src/v/bp_clint.v
+$BP_TOP_DIR/src/v/bp_clint_node.v
+$BP_TOP_DIR/src/v/bp_clint_slice.v
+$BP_TOP_DIR/src/v/bp_clint_slice_buffered.v
+//$BP_TOP_DIR/src/v/bp_l2e_tile.v
+//$BP_TOP_DIR/src/v/bp_l2e_tile_node.v
+$BP_TOP_DIR/src/v/bp_io_complex.v
+$BP_TOP_DIR/src/v/bp_io_link_to_lce.v
+$BP_TOP_DIR/src/v/bp_io_tile.v
+$BP_TOP_DIR/src/v/bp_io_tile_node.v
+$BP_TOP_DIR/src/v/bp_mem_complex.v
+//$BP_TOP_DIR/src/v/bp_processor.v
+$BP_TOP_DIR/src/v/bp_softcore.v
+//$BP_TOP_DIR/src/v/bp_tile.v
+//$BP_TOP_DIR/src/v/bp_tile_node.v
+$BP_TOP_DIR/src/v/bsg_async_noc_link.v
+//$BASEJUMP_STL_DIR/bsg_test/bsg_nonsynth_reset_gen.v
+//$BASEJUMP_STL_DIR/bsg_test/bsg_nonsynth_clock_gen.v
+//$BASEJUMP_STL_DIR/bsg_fsb/bsg_fsb_node_trace_replay.v
+//$BP_BE_DIR/test/common/bp_be_nonsynth_calc_tracer.v
+//$BP_BE_DIR/test/common/bp_be_nonsynth_dcache_tracer.v
+//$BP_BE_DIR/test/common/bp_be_nonsynth_perf.v
+//$BP_BE_DIR/test/common/bp_be_nonsynth_npc_tracer.v
+//$BP_BE_DIR/test/common/bp_be_nonsynth_vm_tracer.v
+//$BP_ME_DIR/test/common/bp_mem.v
+//$BP_ME_DIR/test/common/bp_mem_transducer.v
+//$BP_ME_DIR/test/common/bp_mem_delay_model.v
+//$BP_ME_DIR/test/common/bp_mem_storage_sync.v
+//$BP_ME_DIR/test/common/bp_cce_mmio_cfg_loader.v
+//$BP_ME_DIR/test/common/dramsim2_wrapper.cpp
+//$BP_ME_DIR/test/common/bp_mem_utils.cpp
+//$BP_ME_DIR/test/common/bp_cce_nonsynth_tracer.v
+$BP_ME_DIR/test/common/bp_mem_nonsynth_tracer.v
+//$BP_TOP_DIR/test/common/bp_nonsynth_cosim.v
+//$BP_TOP_DIR/test/common/bp_nonsynth_host.v
+//$BP_TOP_DIR/test/common/bp_nonsynth_if_verif.v
+$BP_TOP_DIR/test/common/bp_nonsynth_commit_tracer.v
+//$BP_TOP_DIR/test/common/bp_nonsynth_nbf_loader.v
+//$BP_TOP_DIR/test/common/bp_monitor.cpp
+//$BP_TOP_DIR/test/common/dromajo_cosim.cpp
+//$BP_FPGA_DIR/wrapper.v
+$BP_FPGA_DIR/bp2wb_convertor.v
+$BP_FPGA_DIR/simulation/ExampleBlackParrotSystem.v

From 19bb1b9b8cd337c11ffd796ac8e65da19d7be9b7 Mon Sep 17 00:00:00 2001
From: sadullah <sadullahcanakci@gmail.com>
Date: Fri, 1 May 2020 23:44:20 -0400
Subject: [PATCH 67/95] update to comply with python-data layout

---
 litex/soc/cores/cpu/blackparrot/README.md     |  20 +++-
 litex/soc/cores/cpu/blackparrot/core.py       |   8 +-
 .../cores/cpu/blackparrot/setEnvironment.sh   | 108 +++---------------
 litex/soc/software/bios/Makefile              |   2 +-
 litex/tools/litex_sim.py                      |   2 +-
 5 files changed, 38 insertions(+), 102 deletions(-)

diff --git a/litex/soc/cores/cpu/blackparrot/README.md b/litex/soc/cores/cpu/blackparrot/README.md
index d320d4b45..95b10a1c3 100644
--- a/litex/soc/cores/cpu/blackparrot/README.md
+++ b/litex/soc/cores/cpu/blackparrot/README.md
@@ -1,12 +1,22 @@
 TODO: Edit
-git submodule update --init --recursive (for blackparrot pre-alpha repo)
-cd pre_alpha_release
-follow getting_started to install blackparrot
-cd ..
 source ./setEnvironment.sh #should be sourced each time you open a terminal or just add this line to bashrc
 Add $BP_TOP/external/bin to $PATH for verilator and riscv-gnu tools
-./update_BP.sh #to modify some of the files in Blackparrot repo (one-time process)
 Currently, we could simulate the LITEX-BIOS on BP processor. 
 
+
+#TODO Running BIOS
+
+
+
+#TODO Running Linux
+
+
+
+#TODO Running on FPGA
+
+
+#TODO
+RISCV tool chain explanation (we currently support IA extension)
+
 [![asciicast](https://asciinema.org/a/286568.svg)](https://asciinema.org/a/286568)
 
diff --git a/litex/soc/cores/cpu/blackparrot/core.py b/litex/soc/cores/cpu/blackparrot/core.py
index e1661bc07..5a9738d05 100644
--- a/litex/soc/cores/cpu/blackparrot/core.py
+++ b/litex/soc/cores/cpu/blackparrot/core.py
@@ -118,13 +118,13 @@ class BlackParrotRV64(CPU):
 
     @staticmethod
     def add_sources(platform, variant="standard"):
+        vdir = get_data_mod("cpu", "blackparrot").data_location
+        bp_litex_dir = os.path.join(vdir,"bp_litex")
         simulation = 0
         if (simulation == 1):
-            filename = get_data_mod("cpu", "blackparrot").data_file(
-            "flist.verilator")
+            filename= os.path.join(bp_litex_dir,"flist.verilator")
         else:
-            filename = get_data_mod("cpu", "blackparrot").data_file(
-            "flist.fpga")
+            filename= os.path.join(bp_litex_dir,"flist.fpga")
         with open(filename) as openfileobject:
             for line in openfileobject:
                 temp = line
diff --git a/litex/soc/cores/cpu/blackparrot/setEnvironment.sh b/litex/soc/cores/cpu/blackparrot/setEnvironment.sh
index 079bb17f7..1e45ca903 100755
--- a/litex/soc/cores/cpu/blackparrot/setEnvironment.sh
+++ b/litex/soc/cores/cpu/blackparrot/setEnvironment.sh
@@ -1,98 +1,24 @@
 #!/bin/bash
 ## Set common environment variables
 export LITEX=$(git rev-parse --show-toplevel)
-export BP=$PWD
-cp bp_software/cce_ucode.mem /tmp/.
-cd pre-alpha-release
-TOP=$(git rev-parse --show-toplevel)
-export BP_COMMON_DIR=$TOP/bp_common
-export BP_FE_DIR=$TOP/bp_fe
-export BP_BE_DIR=$TOP/bp_be
-export BP_ME_DIR=$TOP/bp_me
-export BP_TOP_DIR=$TOP/bp_top
-export BP_EXTERNAL_DIR=$TOP/external
+export BP=$LITEX/../pythondata-cpu-blackparrot/pythondata_cpu_blackparrot/system_verilog
+export BP_LITEX_DIR=$BP/bp_litex
+export LITEX_SOFTWARE_COMPILER_RT=$LITEX/../pythondata-software-compiler_rt
+
+#TODO: check if BP exists and warn user
+export BP_COMMON_DIR=$BP/bp_common
+export BP_FE_DIR=$BP/bp_fe
+export BP_BE_DIR=$BP/bp_be
+export BP_ME_DIR=$BP/bp_me
+export BP_TOP_DIR=$BP/bp_top
+export BP_EXTERNAL_DIR=$BP/external
 export BASEJUMP_STL_DIR=$BP_EXTERNAL_DIR/basejump_stl
-export BP_FPGA_DIR=$TOP/bp_fpga
-## Setup CAD tools
+export LITEX_FPGA_DIR=$BP_LITEX_DIR/fpga
+export LITEX_SIMU_DIR=$BP_LITEX_DIR/simulation
+export LITEX_SOFTWARE=$BP_LITEX_DIR/software
 
-# If the machine you are working on is bsg_cadenv compliant, then you do not
-# need to setup the cad tools, simply put bsg_cadenv in the same root dir.
-#BSG_CADENV_DIR=$(TOP)/external/bsg_cadenv
-#-include $(BSG_CADENV_DIR)/cadenv.mk
+##SOFTWARE CHANGES##
 
-## Sepcify license path if needed
-#LM_LICENSE_FILE ?=
+#for a reason, provided udivmoddi4.c is not functionally correct when used with either BP or Rocket under IA extension. Another version of udivmoddi4.c is a workaround to run BIOS on these architectures.
+cp $LITEX_SOFTWARE/udivmoddi4.c $LITEX_SOFTWARE_COMPILER_RT/pythondata_software_compiler_rt/data/lib/builtins/.
 
-## Override tool paths if needed
-#GCC       ?= gcc
-#VCS_HOME  ?=
-#VCS       ?= vcs
-#URG       ?= urg
-#VERILATOR ?= verilator
-#DC_SHELL  ?= dc_shell
-#DVE       ?= dve
-#PYTHON    ?= python
-
-## Needed for verilator g++ compilations
-export SYSTEMC_INCLUDE=$BP_EXTERNAL_DIR/include
-export SYSTEMC_LIBDIR=$BP_EXTERNAL_DIR/lib-linux64
-
-## Add external tools and libraries to environment
-export LD_LIBRARY_PATH=$SYSTEMC_LIBDIR
-#:$LD_LIBRARY_PATH
-#export PATH=$(BP_EXTERNAL_DIR)/bin:$(PATH)
-#export SYN_PATH=$(BP_TOP_DIR)/syn
-#export TB_PATH=$(BP_TOP_DIR)/test/tb
-#export MEM_PATH=$(BP_COMMON_DIR)/test/mem
-
-#export LOG_PATH=$(BP_TOP_DIR)/syn/logs
-#export RESULTS_PATH=$(BP_TOP_DIR)/syn/results
-#export REPORT_PATH=$(BP_TOP_DIR)/syn/reports
-
-TB="bp_top_trace_demo"
-CFG="e_bp_single_core_cfg"
-START_PC=0x80000000
-TOLERANCE=2
-
-# Select CCE ROM based on CFG and Coherence Protocol
-# TODO: is there a more scalable way to do this?
-if [ $CFG = "e_bp_half_core_cfg" ]
-then
-    NUM_LCE_P=1
-    N_WG=64
-elif [ $CFG = "e_bp_single_core_cfg" ]
-then
-    NUM_LCE_P=2
-    N_WG=64
-    #echo "Single Core config"
-#elif ($CFG -eq e_bp_dual_core_cfg)
-#    NUM_LCE_P=4
-#    N_WG=32
-#elif ($CFG -eq e_bp_quad_core_cfg)
-#    NUM_LCE_P=8
-#    N_WG=16
-#elif ($CFG -eq e_bp_oct_core_cfg)
-#     NUM_LCE_P=16
-#     N_WG=8
-#elif ($(CFG), e_bp_sexta_core_cfg)
-#    NUM_LCE_P=32
-#    N_WG=4
-#elif ($(CFG), e_bp_quad_core_2d_cfg)
-#    NUM_LCE_P=8
-#    N_WG=16
-#elif ($(CFG), e_bp_oct_core_2d_cfg)
-#    NUM_LCE_P=16
-#    N_WG=8
-fi
-
-COH_PROTO="mesi"
-CCE_MEM_PATH=$BP_ME_DIR/src/asm/roms/$COH_PROTO
-CCE_MEM=bp_cce_inst_rom_$COH_PROTO_lce$NUM_LCE_P_wg$N_WG_assoc8.mem
-#DRAMSIM_CH_CFG=DDR2_micron_16M_8b_x8_sg3E.ini
-#DRAMSIM_SYS_CFG=system.ini
-#$include $BP_COMMON_DIR/syn/Makefile.verilator
-#iinclude $(BP_COMMON_DIR)/syn/Makefile.common
-#include $(BP_COMMON_DIR)/syn/Makefile.dc
-#include $(BP_COMMON_DIR)/syn/Makefile.regress
-#include $(BP_COMMON_DIR)/syn/Makefile.vcs
-cd ../
diff --git a/litex/soc/software/bios/Makefile b/litex/soc/software/bios/Makefile
index 98dc44d52..cc58ddf3a 100755
--- a/litex/soc/software/bios/Makefile
+++ b/litex/soc/software/bios/Makefile
@@ -2,7 +2,7 @@ include ../include/generated/variables.mak
 include $(SOC_DIRECTORY)/software/common.mak
 
 ifeq ($(CPU),blackparrot)
-BP_LIBS =  -L$(BP_EXTERNAL_DIR)/lib/gcc/riscv64-unknown-elf/9.2.0/ 
+BP_LIBS =  -L$(LITEX_SOFTWARE)
 BP_FLAGS = -lgcc
 endif
 # Permit TFTP_SERVER_PORT override from shell environment / command line
diff --git a/litex/tools/litex_sim.py b/litex/tools/litex_sim.py
index 83c50793d..86c6d9692 100755
--- a/litex/tools/litex_sim.py
+++ b/litex/tools/litex_sim.py
@@ -353,7 +353,7 @@ def main():
         with_analyzer  = args.with_analyzer,
         sdram_init     = [] if args.sdram_init is None else get_mem_data(args.sdram_init, cpu_endianness),
         **soc_kwargs)
-    if args.sdram_init is not None: #sdram_init
+    if args.ram_init is not None: #sdram_init
         soc.add_constant("ROM_BOOT_ADDRESS", 0x80000000)
     if args.with_ethernet:
         for i in range(4):

From 0c770e0683f39cad480e1a51667159e0ae4ef80f Mon Sep 17 00:00:00 2001
From: Sadullah Canakci <sadullahcanakci@gmail.com>
Date: Sat, 2 May 2020 00:10:06 -0400
Subject: [PATCH 68/95] Update README.md

---
 litex/boards/targets/genesys2.py              |   3 +-
 ...{GETTING STARTED.md => GETTING_STARTED.md} |   5 +-
 litex/soc/cores/cpu/blackparrot/README.md     |  64 +++-
 ...xampleBlackParrotSystem_Linux_Simulation.v | 356 -----------------
 .../bp_fpga/ExampleBlackParrotSystem_UART.v   | 357 -----------------
 .../cpu/blackparrot/bp_fpga/bp2wb_convertor.v | 267 -------------
 .../bp_fpga/bsg_mem_1rw_sync_mask_write_bit.v |  55 ---
 .../bp_fpga/fpga/ExampleBlackParrotSystem.v   | 357 -----------------
 .../simulation/ExampleBlackParrotSystem.v     | 357 -----------------
 .../bp_hardware/bp_cce_mmio_cfg_loader.v      | 231 -----------
 .../blackparrot/bp_hardware/bp_common_pkg.vh  |  55 ---
 .../bp_hardware/bp_nonsynth_host.v            | 190 ----------
 .../cpu/blackparrot/bp_software/cce_ucode.mem |  96 -----
 .../cpu/blackparrot/bp_software/udivmoddi4.c  | 358 ------------------
 litex/soc/cores/cpu/blackparrot/core.py       |   7 +-
 litex/soc/cores/cpu/blackparrot/flist.fpga    | 250 ------------
 .../soc/cores/cpu/blackparrot/flist.verilator | 250 ------------
 .../cpu/blackparrot/flist_litex.verilator     | 229 -----------
 .../cores/cpu/blackparrot/setEnvironment.sh   |   4 +-
 litex/soc/cores/cpu/blackparrot/update_BP.sh  |  17 -
 litex/soc/software/bios/Makefile              |   2 +-
 litex/soc/software/bios/boot.c                |  11 -
 litex/soc/software/bios/isr.c                 |   4 +-
 litex/soc/software/include/base/ctype.h       |   6 +-
 litex/soc/software/libbase/libc.c             |   7 +-
 litex/soc/software/libnet/tftp.c              |  10 +-
 litex/tools/litex_sim.py                      |   5 +-
 27 files changed, 67 insertions(+), 3486 deletions(-)
 rename litex/soc/cores/cpu/blackparrot/{GETTING STARTED.md => GETTING_STARTED.md} (82%)
 delete mode 100644 litex/soc/cores/cpu/blackparrot/bp_fpga/ExampleBlackParrotSystem_Linux_Simulation.v
 delete mode 100644 litex/soc/cores/cpu/blackparrot/bp_fpga/ExampleBlackParrotSystem_UART.v
 delete mode 100644 litex/soc/cores/cpu/blackparrot/bp_fpga/bp2wb_convertor.v
 delete mode 100644 litex/soc/cores/cpu/blackparrot/bp_fpga/bsg_mem_1rw_sync_mask_write_bit.v
 delete mode 100644 litex/soc/cores/cpu/blackparrot/bp_fpga/fpga/ExampleBlackParrotSystem.v
 delete mode 100644 litex/soc/cores/cpu/blackparrot/bp_fpga/simulation/ExampleBlackParrotSystem.v
 delete mode 100644 litex/soc/cores/cpu/blackparrot/bp_hardware/bp_cce_mmio_cfg_loader.v
 delete mode 100644 litex/soc/cores/cpu/blackparrot/bp_hardware/bp_common_pkg.vh
 delete mode 100644 litex/soc/cores/cpu/blackparrot/bp_hardware/bp_nonsynth_host.v
 delete mode 100644 litex/soc/cores/cpu/blackparrot/bp_software/cce_ucode.mem
 delete mode 100644 litex/soc/cores/cpu/blackparrot/bp_software/udivmoddi4.c
 delete mode 100644 litex/soc/cores/cpu/blackparrot/flist.fpga
 delete mode 100644 litex/soc/cores/cpu/blackparrot/flist.verilator
 delete mode 100644 litex/soc/cores/cpu/blackparrot/flist_litex.verilator
 delete mode 100755 litex/soc/cores/cpu/blackparrot/update_BP.sh

diff --git a/litex/boards/targets/genesys2.py b/litex/boards/targets/genesys2.py
index 52023e535..d97b68a36 100755
--- a/litex/boards/targets/genesys2.py
+++ b/litex/boards/targets/genesys2.py
@@ -46,11 +46,10 @@ class BaseSoC(SoCCore):
 
         # SoCCore ----------------------------------------------------------------------------------
         SoCCore.__init__(self, platform, clk_freq=sys_clk_freq, **kwargs)
-#        sys_clk_freq = int(50e6)
 
         # CRG --------------------------------------------------------------------------------------
         self.submodules.crg = _CRG(platform, sys_clk_freq)
-#        self.add_constant("UART_POLLING",None)
+
         # DDR3 SDRAM -------------------------------------------------------------------------------
         if not self.integrated_main_ram_size:
             self.submodules.ddrphy = s7ddrphy.K7DDRPHY(platform.request("ddram"),
diff --git a/litex/soc/cores/cpu/blackparrot/GETTING STARTED.md b/litex/soc/cores/cpu/blackparrot/GETTING_STARTED.md
similarity index 82%
rename from litex/soc/cores/cpu/blackparrot/GETTING STARTED.md
rename to litex/soc/cores/cpu/blackparrot/GETTING_STARTED.md
index 47ea73734..55ec62e2d 100644
--- a/litex/soc/cores/cpu/blackparrot/GETTING STARTED.md	
+++ b/litex/soc/cores/cpu/blackparrot/GETTING_STARTED.md
@@ -1,4 +1,4 @@
-# Getting started
+# Getting started (TODO:update)
 
 ## Running BP in LiteX
 
@@ -20,4 +20,5 @@ The top module is $BP_FPGA_DIR/ExampleBlackParrotSystem.v
 
 The transducer for wishbone communication is $BP_FPGA_DIR/bp2wb_convertor.v
 
-  
+if args.sdram_init is not None: #instead of ram_init for sdram init boot 
+        soc.add_constant("ROM_BOOT_ADDRESS", 0x80000000)
diff --git a/litex/soc/cores/cpu/blackparrot/README.md b/litex/soc/cores/cpu/blackparrot/README.md
index 95b10a1c3..4fe921f79 100644
--- a/litex/soc/cores/cpu/blackparrot/README.md
+++ b/litex/soc/cores/cpu/blackparrot/README.md
@@ -1,22 +1,60 @@
-TODO: Edit
+# BlackParrot in LiteX
+
+
+## Getting Started
+
+TODO: modify getting started [Getting Started (Full)](GETTING_STARTED.md)
+
+### Prerequisites
+
+```
+BP sources (https://github.com/litex-hub/pythondata-cpu-blackparrot)
+RISC-V toolchain built for IA architecture (prebuilt binaries provided by LiteX works fine)
+Verilator (tested with Verilator 4.031)
+```
+
+### Installing
+
+```
+https://github.com/litex-hub/pythondata-cpu-blackparrot is required to run BP in LiteX. 
 source ./setEnvironment.sh #should be sourced each time you open a terminal or just add this line to bashrc
-Add $BP_TOP/external/bin to $PATH for verilator and riscv-gnu tools
-Currently, we could simulate the LITEX-BIOS on BP processor. 
+```
+
+## Running BIOS 
+
+### Simulation
+```
+cd $LITEX/litex/tools
+./litex_sim.py --cpu-type blackparrot --cpu-variant standard --output-dir build/BP_Trial
+```
+[![asciicast](https://asciinema.org/a/326077.svg)](https://asciinema.org/a/326077)
+
+### FPGA
+```
+Coming soon!
+```
+
+## Running Linux 
 
 
-#TODO Running BIOS
+### Simulation
+```
+Modify litex_sim.py by replacing soc.add_constant("ROM_BOOT_ADDRESS", 0x40000000) with soc.add_constant("ROM_BOOT_ADDRESS", 0x80000000)
+
+./litex_sim.py --cpu-type blackparrot --cpu-variant standard --integrated-rom-size 40960 --output-dir build/BP_newversion_linux_ram/ --threads 4 --ram-init build/tests/boot.bin.uart.simu.trial
+
+TODO: add prebuilt bbl files into python-data repository
+
+```
+
+### FPGA
+
+```
+Coming soon!
+```
 
 
 
-#TODO Running Linux
 
 
 
-#TODO Running on FPGA
-
-
-#TODO
-RISCV tool chain explanation (we currently support IA extension)
-
-[![asciicast](https://asciinema.org/a/286568.svg)](https://asciinema.org/a/286568)
-
diff --git a/litex/soc/cores/cpu/blackparrot/bp_fpga/ExampleBlackParrotSystem_Linux_Simulation.v b/litex/soc/cores/cpu/blackparrot/bp_fpga/ExampleBlackParrotSystem_Linux_Simulation.v
deleted file mode 100644
index 3c053f218..000000000
--- a/litex/soc/cores/cpu/blackparrot/bp_fpga/ExampleBlackParrotSystem_Linux_Simulation.v
+++ /dev/null
@@ -1,356 +0,0 @@
-/**
-  *
-  * ExampleBlackParrotSystem.v
-  *
-  */
-  
-`include "bsg_noc_links.vh"
-
-module ExampleBlackParrotSystem
- import bp_common_pkg::*;
- import bp_common_aviary_pkg::*;
- import bp_be_pkg::*;
- import bp_common_rv64_pkg::*;
- import bp_cce_pkg::*;
- import bp_me_pkg::*;
- import bp_common_cfg_link_pkg::*;
- import bsg_noc_pkg::*;
- #(parameter bp_params_e bp_params_p = e_bp_softcore_cfg
-   `declare_bp_proc_params(bp_params_p)
-   `declare_bp_me_if_widths(paddr_width_p, cce_block_width_p, lce_id_width_p, lce_assoc_p)
-
-   // Tracing parameters
-   , parameter calc_trace_p                = 0
-   , parameter cce_trace_p                 = 0
-   , parameter cmt_trace_p                 = 0
-   , parameter dram_trace_p                = 0
-   , parameter npc_trace_p                 = 0
-   , parameter dcache_trace_p              = 0
-   , parameter vm_trace_p                  = 0
-   , parameter preload_mem_p               = 1
-   , parameter load_nbf_p                  = 0
-   , parameter skip_init_p                 = 0
-   , parameter cosim_p                     = 0
-   , parameter cosim_cfg_file_p            = "prog.cfg"
-
-   , parameter mem_zero_p         = 1
-   , parameter mem_file_p         = "prog.mem"
-   , parameter mem_cap_in_bytes_p = 2**25
-   , parameter [paddr_width_p-1:0] mem_offset_p = paddr_width_p'(32'h8000_0000)
-
-   // Number of elements in the fake BlackParrot memory
-   , parameter use_max_latency_p      = 1
-   , parameter use_random_latency_p   = 0
-   , parameter use_dramsim2_latency_p = 0
-
-   , parameter max_latency_p = 15
-
-   , parameter dram_clock_period_in_ps_p = 1000
-   , parameter dram_cfg_p                = "dram_ch.ini"
-   , parameter dram_sys_cfg_p            = "dram_sys.ini"
-   , parameter dram_capacity_p           = 16384
-   )
-  (input clk_i
-   , input reset_i
-      //Wishbone interface
-   , input  [63:0]  wbm_dat_i
-   , output [63:0]  wbm_dat_o
-   , input          wbm_ack_i
-   , input          wbm_err_i
-//   , input          wbm_rty_i
-   , output [36:0]  wbm_adr_o //TODO parametrize this
-   , output         wbm_stb_o
-   , output         wbm_cyc_o
-   , output [7:0]   wbm_sel_o //TODO: how many  bits ? check
-   , output         wbm_we_o
-   , output [2:0]   wbm_cti_o //TODO:
-   , output [1:0]   wbm_bte_o
-  // , input  [3:0]   interrupts
-   );
-
-`declare_bp_me_if(paddr_width_p, cce_block_width_p, lce_id_width_p, lce_assoc_p)
-
-bp_cce_mem_msg_s proc_mem_cmd_lo;
-logic proc_mem_cmd_v_lo, proc_mem_cmd_ready_li;
-bp_cce_mem_msg_s proc_mem_resp_li;
-logic proc_mem_resp_v_li, proc_mem_resp_yumi_lo;
-
-bp_cce_mem_msg_s proc_io_cmd_lo;
-logic proc_io_cmd_v_lo, proc_io_cmd_ready_li;
-bp_cce_mem_msg_s proc_io_resp_li;
-logic proc_io_resp_v_li, proc_io_resp_yumi_lo;
-
-bp_cce_mem_msg_s io_cmd_lo;
-logic io_cmd_v_lo, io_cmd_ready_li;
-bp_cce_mem_msg_s io_resp_li;
-logic io_resp_v_li, io_resp_yumi_lo;
-bp_softcore
- #(.bp_params_p(bp_params_p))
- softcore
-  (.clk_i(clk_i)
-   ,.reset_i(reset_i)
-
-   ,.io_cmd_o(proc_io_cmd_lo)
-   ,.io_cmd_v_o(proc_io_cmd_v_lo)
-   ,.io_cmd_ready_i(proc_io_cmd_ready_li)
-
-   ,.io_resp_i(proc_io_resp_li)
-   ,.io_resp_v_i(proc_io_resp_v_li)
-   ,.io_resp_yumi_o(proc_io_resp_yumi_lo)
-
-   ,.mem_cmd_o(proc_mem_cmd_lo)
-   ,.mem_cmd_v_o(proc_mem_cmd_v_lo)
-   ,.mem_cmd_ready_i(proc_mem_cmd_ready_li)
-
-   ,.mem_resp_i(proc_mem_resp_li)
-   ,.mem_resp_v_i(proc_mem_resp_v_li)
-   ,.mem_resp_yumi_o(proc_mem_resp_yumi_lo)
-   );
-
- bp2wb_convertor
-   #(.bp_params_p(bp_params_p))
-   bp2wb
-    (.clk_i(clk_i)
-     ,.reset_i(reset_i)
-    ,.mem_cmd_i(proc_mem_cmd_lo)
-     ,.mem_cmd_v_i(proc_mem_cmd_v_lo & proc_mem_cmd_ready_li)
-     ,.mem_cmd_ready_o(proc_mem_cmd_ready_li)
-
-     ,.mem_resp_o(proc_mem_resp_li)
-     ,.mem_resp_v_o(proc_mem_resp_v_li)
-     ,.mem_resp_yumi_i(proc_mem_resp_yumi_lo)
-
-     ,.dat_i(wbm_dat_i)
-     ,.dat_o(wbm_dat_o)
-     ,.ack_i(wbm_ack_i)
-     ,.adr_o(wbm_adr_o)
-     ,.stb_o(wbm_stb_o)
-     ,.cyc_o(wbm_cyc_o)
-     ,.sel_o(wbm_sel_o )
-     ,.we_o(wbm_we_o)
-     ,.cti_o(wbm_cti_o)
-     ,.bte_o(wbm_bte_o )
-    // ,.rty_i(wbm_rty_i)
-     ,.err_i(wbm_err_i)
-     );
-
-/*
-bp_mem
- mem
-  (.clk_i(clk_i)
-   ,.reset_i(reset_i)
- 
-   ,.mem_cmd_i(proc_mem_cmd_lo)
-   ,.mem_cmd_v_i(proc_mem_cmd_v_lo & proc_mem_cmd_ready_li)
-   ,.mem_cmd_ready_o(proc_mem_cmd_ready_li)
- 
-   ,.mem_resp_o(proc_mem_resp_li)
-   ,.mem_resp_v_o(proc_mem_resp_v_li)
-   ,.mem_resp_yumi_i(proc_mem_resp_yumi_lo)
-   );
-*/
-logic program_finish_lo;
-bp_nonsynth_host
- #(.bp_params_p(bp_params_p))
- host
-  (.clk_i(clk_i)
-   ,.reset_i(reset_i)
-
-   ,.io_cmd_i(proc_io_cmd_lo)
-   ,.io_cmd_v_i(proc_io_cmd_v_lo & proc_io_cmd_ready_li)
-   ,.io_cmd_ready_o(proc_io_cmd_ready_li)
-
-   ,.io_resp_o(proc_io_resp_li)
-   ,.io_resp_v_o(proc_io_resp_v_li)
-   ,.io_resp_yumi_i(proc_io_resp_yumi_lo)
-
-   ,.program_finish_o(program_finish_lo)
-   );
-
-/*bind bp_be_top
-  bp_nonsynth_commit_tracer
-   #(.bp_params_p(bp_params_p))
-   commit_tracer
-    (.clk_i(clk_i & (ExampleBlackParrotSystem.cmt_trace_p == 1))
-     ,.reset_i(reset_i)
-     ,.freeze_i('0)
-
-     ,.mhartid_i('0)
-
-     ,.commit_v_i(be_calculator.commit_pkt.instret)
-     ,.commit_pc_i(be_calculator.commit_pkt.pc)
-     ,.commit_instr_i(be_calculator.commit_pkt.instr)
-
-     ,.rd_w_v_i(be_calculator.wb_pkt.rd_w_v)
-     ,.rd_addr_i(be_calculator.wb_pkt.rd_addr)
-     ,.rd_data_i(be_calculator.wb_pkt.rd_data)
-     );
-*/
-/*  bind bp_be_top
-    bp_nonsynth_cosim
-     #(.bp_params_p(bp_params_p))
-      cosim
-      (.clk_i(clk_i)
-       ,.reset_i(reset_i)
-       ,.en_i(ExampleBlackParrotSystem.cosim_p == 1)
-
-       ,.mhartid_i(be_checker.scheduler.int_regfile.cfg_bus.core_id)
-       // Want to pass config file as a parameter, but cannot in Verilator 4.025
-       // Parameter-resolved constants must not use dotted references
-       ,.config_file_i(ExampleBlackParrotSystem.cosim_cfg_file_p)
-
-       ,.commit_v_i(be_calculator.commit_pkt.instret)
-       ,.commit_pc_i(be_calculator.commit_pkt.pc)
-       ,.commit_instr_i(be_calculator.commit_pkt.instr)
-
-       ,.rd_w_v_i(be_calculator.wb_pkt.rd_w_v)
-       ,.rd_addr_i(be_calculator.wb_pkt.rd_addr)
-       ,.rd_data_i(be_calculator.wb_pkt.rd_data)
-
-       ,.interrupt_v_i(be_mem.csr.trap_pkt_cast_o._interrupt)
-       ,.cause_i(be_mem.csr.trap_pkt_cast_o.cause)
-       );
-*/
-/*bind bp_be_top
-  bp_be_nonsynth_perf
-   #(.bp_params_p(bp_params_p))
-   perf
-    (.clk_i(clk_i)
-     ,.reset_i(reset_i)
-
-     ,.mhartid_i(be_checker.scheduler.int_regfile.cfg_bus.core_id)
-
-     ,.fe_nop_i(be_calculator.exc_stage_r[2].fe_nop_v)
-     ,.be_nop_i(be_calculator.exc_stage_r[2].be_nop_v)
-     ,.me_nop_i(be_calculator.exc_stage_r[2].me_nop_v)
-     ,.poison_i(be_calculator.exc_stage_r[2].poison_v)
-     ,.roll_i(be_calculator.exc_stage_r[2].roll_v)
-
-     ,.instr_cmt_i(be_calculator.commit_pkt.instret)
-
-     ,.program_finish_i(ExampleBlackParrotSystem.program_finish_lo)
-     );
-*/
- /* bind bp_be_director
-    bp_be_nonsynth_npc_tracer
-     #(.bp_params_p(bp_params_p))
-     npc_tracer
-      (.clk_i(clk_i & (ExampleBlackParrotSystem.npc_trace_p == 1))
-       ,.reset_i(reset_i)
-       ,.freeze_i('0)
-
-       ,.mhartid_i(be_checker.scheduler.int_regfile.cfg_bus.core_id)
-
-       ,.npc_w_v(npc_w_v)
-       ,.npc_n(npc_n)
-       ,.npc_r(npc_r)
-       ,.expected_npc_o(expected_npc_o)
-
-       ,.fe_cmd_i(fe_cmd)
-       ,.fe_cmd_v(fe_cmd_v)
-
-       ,.commit_pkt_i(commit_pkt)
-       );
-*/
-  /*bind bp_be_dcache
-    bp_be_nonsynth_dcache_tracer
-     #(.bp_params_p(bp_params_p))
-     dcache_tracer
-      (.clk_i(clk_i & (ExampleBlackParrotSystem.dcache_trace_p == 1))
-       ,.reset_i(reset_i)
-       ,.freeze_i('0)
-
-       ,.mhartid_i(cfg_bus_cast_i.core_id)
-
-       ,.v_tv_r(v_tv_r)
-       //,.cache_miss_i(cache_miss_i)
-
-       ,.paddr_tv_r(paddr_tv_r)
-       ,.uncached_tv_r(uncached_tv_r)
-       ,.load_op_tv_r(load_op_tv_r)
-       ,.store_op_tv_r(store_op_tv_r)
-       ,.lr_op_tv_r(lr_op_tv_r)
-       ,.sc_op_tv_r(sc_op_tv_r)
-       ,.store_data(data_tv_r)
-       ,.load_data(data_o)
-       );*/
-/*
-  bind bp_be_top
-    bp_be_nonsynth_calc_tracer
-     #(.bp_params_p(bp_params_p))
-     calc_tracer
-      (.clk_i(clk_i & (ExampleBlackParrotSystem.calc_trace_p == 1))
-       ,.reset_i(reset_i)
-       ,.freeze_i('0)
-
-       ,.mhartid_i(be_checker.scheduler.int_regfile.cfg_bus.core_id)
-
-       ,.issue_pkt_i(be_checker.scheduler.issue_pkt)
-       ,.issue_pkt_v_i(be_checker.scheduler.fe_queue_yumi_o)
-
-       ,.fe_nop_v_i(be_calculator.exc_stage_n[0].fe_nop_v)
-       ,.be_nop_v_i(be_calculator.exc_stage_n[0].be_nop_v)
-       ,.me_nop_v_i(be_calculator.exc_stage_n[0].me_nop_v)
-       ,.dispatch_pkt_i(be_calculator.dispatch_pkt)
-
-       ,.ex1_br_tgt_i(be_calculator.calc_status.ex1_npc)
-       ,.ex1_btaken_i(be_calculator.pipe_int.btaken)
-       ,.iwb_result_i(be_calculator.comp_stage_n[3])
-       ,.fwb_result_i(be_calculator.comp_stage_n[4])
-
-       ,.cmt_trace_exc_i(be_calculator.exc_stage_n[1+:5])
-
-       ,.trap_v_i(be_mem.csr.trap_pkt_cast_o._interrupt | be_mem.csr.trap_pkt_cast_o.exception)
-       ,.mtvec_i(be_mem.csr.mtvec_n)
-       ,.mtval_i(be_mem.csr.mtval_n[0+:vaddr_width_p])
-       ,.ret_v_i(be_mem.csr.trap_pkt_cast_o.eret)
-       ,.mepc_i(be_mem.csr.mepc_n[0+:vaddr_width_p])
-       ,.mcause_i(be_mem.csr.mcause_n)
-
-       ,.priv_mode_i(be_mem.csr.priv_mode_n)
-       ,.mpp_i(be_mem.csr.mstatus_n.mpp)
-       );
-
-  bind bp_core_minimal
-    bp_be_nonsynth_vm_tracer
-    #(.bp_params_p(bp_params_p))
-    vm_tracer
-      (.clk_i(clk_i & (ExampleBlackParrotSystem.vm_trace_p == 1))
-       ,.reset_i(reset_i)
-       ,.freeze_i('0)
-
-       ,.mhartid_i(be.be_checker.scheduler.int_regfile.cfg_bus.core_id)
-
-       ,.itlb_clear_i(fe.mem.itlb.flush_i)
-       ,.itlb_fill_v_i(fe.mem.itlb.v_i & fe.mem.itlb.w_i)
-       ,.itlb_vtag_i(fe.mem.itlb.vtag_i)
-       ,.itlb_entry_i(fe.mem.itlb.entry_i)
-
-       ,.dtlb_clear_i(be.be_mem.dtlb.flush_i)
-       ,.dtlb_fill_v_i(be.be_mem.dtlb.v_i & be.be_mem.dtlb.w_i)
-       ,.dtlb_vtag_i(be.be_mem.dtlb.vtag_i)
-       ,.dtlb_entry_i(be.be_mem.dtlb.entry_i)
-       );
-*/
-  /*bp_mem_nonsynth_tracer
-   #(.bp_params_p(bp_params_p))
-   bp_mem_tracer
-    (.clk_i(clk_i & (ExampleBlackParrotSystem.dram_trace_p == 1))
-     ,.reset_i(reset_i)
-
-     ,.mem_cmd_i(proc_mem_cmd_lo)
-     ,.mem_cmd_v_i(proc_mem_cmd_v_lo & proc_mem_cmd_ready_li)
-     ,.mem_cmd_ready_i(proc_mem_cmd_ready_li)
-
-     ,.mem_resp_i(proc_mem_resp_li)
-     ,.mem_resp_v_i(proc_mem_resp_v_li)
-     ,.mem_resp_yumi_i(proc_mem_resp_yumi_lo)
-     );
-*/
-/*bp_nonsynth_if_verif
- #(.bp_params_p(bp_params_p))
- if_verif
-  ();
-*/
-endmodule
-
diff --git a/litex/soc/cores/cpu/blackparrot/bp_fpga/ExampleBlackParrotSystem_UART.v b/litex/soc/cores/cpu/blackparrot/bp_fpga/ExampleBlackParrotSystem_UART.v
deleted file mode 100644
index c226c3316..000000000
--- a/litex/soc/cores/cpu/blackparrot/bp_fpga/ExampleBlackParrotSystem_UART.v
+++ /dev/null
@@ -1,357 +0,0 @@
-/**
-  *
-  * ExampleBlackParrotSystem.v
-  *
-  */
-  
-`include "bsg_noc_links.vh"
-
-module ExampleBlackParrotSystem
- import bp_common_pkg::*;
- import bp_common_aviary_pkg::*;
- import bp_be_pkg::*;
- import bp_common_rv64_pkg::*;
- import bp_cce_pkg::*;
- import bp_me_pkg::*;
- import bp_common_cfg_link_pkg::*;
- import bsg_noc_pkg::*;
- #(parameter bp_params_e bp_params_p = e_bp_softcore_cfg
-   `declare_bp_proc_params(bp_params_p)
-   `declare_bp_me_if_widths(paddr_width_p, cce_block_width_p, lce_id_width_p, lce_assoc_p)
-
-   // Tracing parameters
-   , parameter calc_trace_p                = 0
-   , parameter cce_trace_p                 = 0
-   , parameter cmt_trace_p                 = 1
-   , parameter dram_trace_p                = 1
-   , parameter npc_trace_p                 = 0
-   , parameter dcache_trace_p              = 0
-   , parameter vm_trace_p                  = 0
-   , parameter preload_mem_p               = 1
-   , parameter load_nbf_p                  = 0
-   , parameter skip_init_p                 = 0
-   , parameter cosim_p                     = 0
-   , parameter cosim_cfg_file_p            = "prog.cfg"
-
-   , parameter mem_zero_p         = 1
-   , parameter mem_file_p         = "prog.mem"
-   , parameter mem_cap_in_bytes_p = 2**25
-   , parameter [paddr_width_p-1:0] mem_offset_p = paddr_width_p'(32'h8000_0000)
-
-   // Number of elements in the fake BlackParrot memory
-   , parameter use_max_latency_p      = 1
-   , parameter use_random_latency_p   = 0
-   , parameter use_dramsim2_latency_p = 0
-
-   , parameter max_latency_p = 15
-
-   , parameter dram_clock_period_in_ps_p = 1000
-   , parameter dram_cfg_p                = "dram_ch.ini"
-   , parameter dram_sys_cfg_p            = "dram_sys.ini"
-   , parameter dram_capacity_p           = 16384
-   )
-  (input clk_i
-   , input reset_i
-      //Wishbone interface
-   , input  [63:0]  wbm_dat_i
-   , output [63:0]  wbm_dat_o
-   , input          wbm_ack_i
-   , input          wbm_err_i
-//   , input          wbm_rty_i
-   , output [36:0]  wbm_adr_o //TODO parametrize this
-   , output         wbm_stb_o
-   , output         wbm_cyc_o
-   , output [7:0]   wbm_sel_o //TODO: how many  bits ? check
-   , output         wbm_we_o
-   , output [2:0]   wbm_cti_o //TODO:
-   , output [1:0]   wbm_bte_o
-  // , input  [3:0]   interrupts
-   );
-
-`declare_bp_me_if(paddr_width_p, cce_block_width_p, lce_id_width_p, lce_assoc_p)
-
-bp_cce_mem_msg_s proc_mem_cmd_lo;
-logic proc_mem_cmd_v_lo, proc_mem_cmd_ready_li;
-bp_cce_mem_msg_s proc_mem_resp_li;
-logic proc_mem_resp_v_li, proc_mem_resp_yumi_lo;
-
-bp_cce_mem_msg_s proc_io_cmd_lo;
-logic proc_io_cmd_v_lo, proc_io_cmd_ready_li;
-bp_cce_mem_msg_s proc_io_resp_li;
-logic proc_io_resp_v_li, proc_io_resp_yumi_lo;
-
-bp_cce_mem_msg_s io_cmd_lo;
-logic io_cmd_v_lo, io_cmd_ready_li;
-bp_cce_mem_msg_s io_resp_li;
-logic io_resp_v_li, io_resp_yumi_lo;
-bp_softcore
- #(.bp_params_p(bp_params_p))
- softcore
-  (.clk_i(clk_i)
-   ,.reset_i(reset_i)
-
-   ,.io_cmd_o(proc_io_cmd_lo)
-   ,.io_cmd_v_o(proc_io_cmd_v_lo)
-   ,.io_cmd_ready_i(proc_io_cmd_ready_li)
-
-   ,.io_resp_i(proc_io_resp_li)
-   ,.io_resp_v_i(proc_io_resp_v_li)
-   ,.io_resp_yumi_o(proc_io_resp_yumi_lo)
-
-   ,.mem_cmd_o(proc_mem_cmd_lo)
-   ,.mem_cmd_v_o(proc_mem_cmd_v_lo)
-   ,.mem_cmd_ready_i(proc_mem_cmd_ready_li)
-
-   ,.mem_resp_i(proc_mem_resp_li)
-   ,.mem_resp_v_i(proc_mem_resp_v_li)
-   ,.mem_resp_yumi_o(proc_mem_resp_yumi_lo)
-   );
-
- bp2wb_convertor
-   #(.bp_params_p(bp_params_p))
-   bp2wb
-    (.clk_i(clk_i)
-     ,.reset_i(reset_i)
-    ,.mem_cmd_i(proc_mem_cmd_lo)
-     ,.mem_cmd_v_i(proc_mem_cmd_v_lo & proc_mem_cmd_ready_li)
-     ,.mem_cmd_ready_o(proc_mem_cmd_ready_li)
-
-     ,.mem_resp_o(proc_mem_resp_li)
-     ,.mem_resp_v_o(proc_mem_resp_v_li)
-     ,.mem_resp_yumi_i(proc_mem_resp_yumi_lo)
-
-     ,.dat_i(wbm_dat_i)
-     ,.dat_o(wbm_dat_o)
-     ,.ack_i(wbm_ack_i)
-     ,.adr_o(wbm_adr_o)
-     ,.stb_o(wbm_stb_o)
-     ,.cyc_o(wbm_cyc_o)
-     ,.sel_o(wbm_sel_o )
-     ,.we_o(wbm_we_o)
-     ,.cti_o(wbm_cti_o)
-     ,.bte_o(wbm_bte_o )
-    // ,.rty_i(wbm_rty_i)
-     ,.err_i(wbm_err_i)
-     );
-
-/*
-bp_mem
- mem
-  (.clk_i(clk_i)
-   ,.reset_i(reset_i)
- 
-   ,.mem_cmd_i(proc_mem_cmd_lo)
-   ,.mem_cmd_v_i(proc_mem_cmd_v_lo & proc_mem_cmd_ready_li)
-   ,.mem_cmd_ready_o(proc_mem_cmd_ready_li)
- 
-   ,.mem_resp_o(proc_mem_resp_li)
-   ,.mem_resp_v_o(proc_mem_resp_v_li)
-   ,.mem_resp_yumi_i(proc_mem_resp_yumi_lo)
-   );
-*/
-logic program_finish_lo;
-assign proc_io_cmd_ready_li = 1;
-/*bp_nonsynth_host
- #(.bp_params_p(bp_params_p))
- host
-  (.clk_i(clk_i)
-   ,.reset_i(reset_i)
-
-   ,.io_cmd_i(proc_io_cmd_lo)
-   ,.io_cmd_v_i(proc_io_cmd_v_lo & proc_io_cmd_ready_li)
-   ,.io_cmd_ready_o(proc_io_cmd_ready_li)
-
-   ,.io_resp_o(proc_io_resp_li)
-   ,.io_resp_v_o(proc_io_resp_v_li)
-   ,.io_resp_yumi_i(proc_io_resp_yumi_lo)
-
-   ,.program_finish_o(program_finish_lo)
-   );
-*/
-bind bp_be_top
-  bp_nonsynth_commit_tracer
-   #(.bp_params_p(bp_params_p))
-   commit_tracer
-    (.clk_i(clk_i & (ExampleBlackParrotSystem.cmt_trace_p == 1))
-     ,.reset_i(reset_i)
-     ,.freeze_i('0)
-
-     ,.mhartid_i('0)
-
-     ,.commit_v_i(be_calculator.commit_pkt.instret)
-     ,.commit_pc_i(be_calculator.commit_pkt.pc)
-     ,.commit_instr_i(be_calculator.commit_pkt.instr)
-
-     ,.rd_w_v_i(be_calculator.wb_pkt.rd_w_v)
-     ,.rd_addr_i(be_calculator.wb_pkt.rd_addr)
-     ,.rd_data_i(be_calculator.wb_pkt.rd_data)
-     );
-
-/*  bind bp_be_top
-    bp_nonsynth_cosim
-     #(.bp_params_p(bp_params_p))
-      cosim
-      (.clk_i(clk_i)
-       ,.reset_i(reset_i)
-       ,.en_i(ExampleBlackParrotSystem.cosim_p == 1)
-
-       ,.mhartid_i(be_checker.scheduler.int_regfile.cfg_bus.core_id)
-       // Want to pass config file as a parameter, but cannot in Verilator 4.025
-       // Parameter-resolved constants must not use dotted references
-       ,.config_file_i(ExampleBlackParrotSystem.cosim_cfg_file_p)
-
-       ,.commit_v_i(be_calculator.commit_pkt.instret)
-       ,.commit_pc_i(be_calculator.commit_pkt.pc)
-       ,.commit_instr_i(be_calculator.commit_pkt.instr)
-
-       ,.rd_w_v_i(be_calculator.wb_pkt.rd_w_v)
-       ,.rd_addr_i(be_calculator.wb_pkt.rd_addr)
-       ,.rd_data_i(be_calculator.wb_pkt.rd_data)
-
-       ,.interrupt_v_i(be_mem.csr.trap_pkt_cast_o._interrupt)
-       ,.cause_i(be_mem.csr.trap_pkt_cast_o.cause)
-       );
-*/
-/*bind bp_be_top
-  bp_be_nonsynth_perf
-   #(.bp_params_p(bp_params_p))
-   perf
-    (.clk_i(clk_i)
-     ,.reset_i(reset_i)
-
-     ,.mhartid_i(be_checker.scheduler.int_regfile.cfg_bus.core_id)
-
-     ,.fe_nop_i(be_calculator.exc_stage_r[2].fe_nop_v)
-     ,.be_nop_i(be_calculator.exc_stage_r[2].be_nop_v)
-     ,.me_nop_i(be_calculator.exc_stage_r[2].me_nop_v)
-     ,.poison_i(be_calculator.exc_stage_r[2].poison_v)
-     ,.roll_i(be_calculator.exc_stage_r[2].roll_v)
-
-     ,.instr_cmt_i(be_calculator.commit_pkt.instret)
-
-     ,.program_finish_i(ExampleBlackParrotSystem.program_finish_lo)
-     );
-*/
- /* bind bp_be_director
-    bp_be_nonsynth_npc_tracer
-     #(.bp_params_p(bp_params_p))
-     npc_tracer
-      (.clk_i(clk_i & (ExampleBlackParrotSystem.npc_trace_p == 1))
-       ,.reset_i(reset_i)
-       ,.freeze_i('0)
-
-       ,.mhartid_i(be_checker.scheduler.int_regfile.cfg_bus.core_id)
-
-       ,.npc_w_v(npc_w_v)
-       ,.npc_n(npc_n)
-       ,.npc_r(npc_r)
-       ,.expected_npc_o(expected_npc_o)
-
-       ,.fe_cmd_i(fe_cmd)
-       ,.fe_cmd_v(fe_cmd_v)
-
-       ,.commit_pkt_i(commit_pkt)
-       );
-*/
-  /*bind bp_be_dcache
-    bp_be_nonsynth_dcache_tracer
-     #(.bp_params_p(bp_params_p))
-     dcache_tracer
-      (.clk_i(clk_i & (ExampleBlackParrotSystem.dcache_trace_p == 1))
-       ,.reset_i(reset_i)
-       ,.freeze_i('0)
-
-       ,.mhartid_i(cfg_bus_cast_i.core_id)
-
-       ,.v_tv_r(v_tv_r)
-       //,.cache_miss_i(cache_miss_i)
-
-       ,.paddr_tv_r(paddr_tv_r)
-       ,.uncached_tv_r(uncached_tv_r)
-       ,.load_op_tv_r(load_op_tv_r)
-       ,.store_op_tv_r(store_op_tv_r)
-       ,.lr_op_tv_r(lr_op_tv_r)
-       ,.sc_op_tv_r(sc_op_tv_r)
-       ,.store_data(data_tv_r)
-       ,.load_data(data_o)
-       );*/
-/*
-  bind bp_be_top
-    bp_be_nonsynth_calc_tracer
-     #(.bp_params_p(bp_params_p))
-     calc_tracer
-      (.clk_i(clk_i & (ExampleBlackParrotSystem.calc_trace_p == 1))
-       ,.reset_i(reset_i)
-       ,.freeze_i('0)
-
-       ,.mhartid_i(be_checker.scheduler.int_regfile.cfg_bus.core_id)
-
-       ,.issue_pkt_i(be_checker.scheduler.issue_pkt)
-       ,.issue_pkt_v_i(be_checker.scheduler.fe_queue_yumi_o)
-
-       ,.fe_nop_v_i(be_calculator.exc_stage_n[0].fe_nop_v)
-       ,.be_nop_v_i(be_calculator.exc_stage_n[0].be_nop_v)
-       ,.me_nop_v_i(be_calculator.exc_stage_n[0].me_nop_v)
-       ,.dispatch_pkt_i(be_calculator.dispatch_pkt)
-
-       ,.ex1_br_tgt_i(be_calculator.calc_status.ex1_npc)
-       ,.ex1_btaken_i(be_calculator.pipe_int.btaken)
-       ,.iwb_result_i(be_calculator.comp_stage_n[3])
-       ,.fwb_result_i(be_calculator.comp_stage_n[4])
-
-       ,.cmt_trace_exc_i(be_calculator.exc_stage_n[1+:5])
-
-       ,.trap_v_i(be_mem.csr.trap_pkt_cast_o._interrupt | be_mem.csr.trap_pkt_cast_o.exception)
-       ,.mtvec_i(be_mem.csr.mtvec_n)
-       ,.mtval_i(be_mem.csr.mtval_n[0+:vaddr_width_p])
-       ,.ret_v_i(be_mem.csr.trap_pkt_cast_o.eret)
-       ,.mepc_i(be_mem.csr.mepc_n[0+:vaddr_width_p])
-       ,.mcause_i(be_mem.csr.mcause_n)
-
-       ,.priv_mode_i(be_mem.csr.priv_mode_n)
-       ,.mpp_i(be_mem.csr.mstatus_n.mpp)
-       );
-
-  bind bp_core_minimal
-    bp_be_nonsynth_vm_tracer
-    #(.bp_params_p(bp_params_p))
-    vm_tracer
-      (.clk_i(clk_i & (ExampleBlackParrotSystem.vm_trace_p == 1))
-       ,.reset_i(reset_i)
-       ,.freeze_i('0)
-
-       ,.mhartid_i(be.be_checker.scheduler.int_regfile.cfg_bus.core_id)
-
-       ,.itlb_clear_i(fe.mem.itlb.flush_i)
-       ,.itlb_fill_v_i(fe.mem.itlb.v_i & fe.mem.itlb.w_i)
-       ,.itlb_vtag_i(fe.mem.itlb.vtag_i)
-       ,.itlb_entry_i(fe.mem.itlb.entry_i)
-
-       ,.dtlb_clear_i(be.be_mem.dtlb.flush_i)
-       ,.dtlb_fill_v_i(be.be_mem.dtlb.v_i & be.be_mem.dtlb.w_i)
-       ,.dtlb_vtag_i(be.be_mem.dtlb.vtag_i)
-       ,.dtlb_entry_i(be.be_mem.dtlb.entry_i)
-       );
-*/
-/*  bp_mem_nonsynth_tracer
-   #(.bp_params_p(bp_params_p))
-   bp_mem_tracer
-    (.clk_i(clk_i & (ExampleBlackParrotSystem.dram_trace_p == 1))
-     ,.reset_i(reset_i)
-
-     ,.mem_cmd_i(proc_mem_cmd_lo)
-     ,.mem_cmd_v_i(proc_mem_cmd_v_lo & proc_mem_cmd_ready_li)
-     ,.mem_cmd_ready_i(proc_mem_cmd_ready_li)
-
-     ,.mem_resp_i(proc_mem_resp_li)
-     ,.mem_resp_v_i(proc_mem_resp_v_li)
-     ,.mem_resp_yumi_i(proc_mem_resp_yumi_lo)
-     );
-*/
-/*bp_nonsynth_if_verif
- #(.bp_params_p(bp_params_p))
- if_verif
-  ();
-*/
-endmodule
-
diff --git a/litex/soc/cores/cpu/blackparrot/bp_fpga/bp2wb_convertor.v b/litex/soc/cores/cpu/blackparrot/bp_fpga/bp2wb_convertor.v
deleted file mode 100644
index 90ed0854e..000000000
--- a/litex/soc/cores/cpu/blackparrot/bp_fpga/bp2wb_convertor.v
+++ /dev/null
@@ -1,267 +0,0 @@
-/**
- * bp2wb_convertor.v
- * DESCRIPTION: THIS MODULE ADAPTS BP MEMORY BUS TO 64-BIT WISHBONE
- */
-
-module bp2wb_convertor
-  import bp_common_pkg::*;
-  import bp_common_aviary_pkg::*;
-  import bp_cce_pkg::*;
-  import bp_me_pkg::*;
-  #(parameter bp_params_e bp_params_p = e_bp_single_core_cfg
-   `declare_bp_proc_params(bp_params_p)
-   `declare_bp_me_if_widths(paddr_width_p, cce_block_width_p, lce_id_width_p, lce_assoc_p)
-
-//   , parameter [paddr_width_p-1:0] dram_offset_p = '0
-   , localparam num_block_words_lp   = cce_block_width_p / 64
-   , localparam num_block_bytes_lp   = cce_block_width_p / 8
-   , localparam num_word_bytes_lp    = dword_width_p / 8
-   , localparam block_offset_bits_lp = `BSG_SAFE_CLOG2(num_block_bytes_lp)
-   , localparam word_offset_bits_lp  = `BSG_SAFE_CLOG2(num_block_words_lp)
-   , localparam byte_offset_bits_lp  = `BSG_SAFE_CLOG2(num_word_bytes_lp)
-   , localparam wbone_data_width  = 64
-   , localparam wbone_addr_ubound = paddr_width_p
-   , localparam mem_granularity = 64 //TODO: adapt selection bit parametrized
-   , localparam wbone_addr_lbound = 3 //`BSG_SAFE_CLOG2(wbone_data_width / mem_granularity) //dword granularity
-   , localparam total_datafetch_cycle_lp   = cce_block_width_p / wbone_data_width
-   , localparam total_datafetch_cycle_width = `BSG_SAFE_CLOG2(total_datafetch_cycle_lp)
-   , localparam cached_addr_base =  32'h7000_0000//6000_0000 //32'h4000_4000//   
-   )
-  (                            input                                 clk_i
-   ,(* mark_debug = "true" *)  input                               reset_i
-
-   // BP side 
-   ,(* mark_debug = "true" *)  input [cce_mem_msg_width_lp-1:0]    mem_cmd_i
-   ,(* mark_debug = "true" *)  input                               mem_cmd_v_i
-   ,(* mark_debug = "true" *)  output                              mem_cmd_ready_o
-
-   ,                           output [cce_mem_msg_width_lp-1:0]   mem_resp_o
-   , (* mark_debug = "true" *) output                              mem_resp_v_o
-   , (* mark_debug = "true" *) input                               mem_resp_yumi_i
-
-   // Wishbone side
-   , (* mark_debug = "true" *) input [63:0]                        dat_i
-   , (* mark_debug = "true" *) output logic [63:0]                 dat_o
-   , (* mark_debug = "true" *) input                               ack_i
-   , input                               err_i
-//   , input                               rty_i
-   , (* mark_debug = "true" *) output logic [wbone_addr_ubound-wbone_addr_lbound-1:0] adr_o//TODO: Double check!!!    
-   , (* mark_debug = "true" *) output logic stb_o
-   , output                              cyc_o
-   , output [7:0]                        sel_o //TODO: double check!!!
-   , (* mark_debug = "true" *) output                              we_o
-   , output [2:0]                        cti_o //TODO: hardwire in Litex
-   , output [1:0]                        bte_o //TODO: hardwire in Litex
- 
-   );
-
-  `declare_bp_me_if(paddr_width_p, cce_block_width_p, lce_id_width_p, lce_assoc_p);
-  
-  //locals
- (* mark_debug = "true" *) logic  [total_datafetch_cycle_width:0] ack_ctr  = 0;
- (* mark_debug = "true" *) bp_cce_mem_msg_s  mem_cmd_cast_i, mem_resp_cast_o,  mem_cmd_debug;//, mem_cmd_debug2
- (* mark_debug = "true" *) logic ready_li, v_li, stb_justgotack;
-  (* mark_debug = "true" *) logic [cce_block_width_p-1:0] data_lo; 
-  (* mark_debug = "true" *) logic  [cce_block_width_p-1:0] data_li;
-  (* mark_debug = "true" *) wire [paddr_width_p-1:0]  mem_cmd_addr_l;
-  (* mark_debug = "true" *) logic set_stb;
-
-
-  //Handshaking between Wishbone and BlackParrot through convertor  
-  //3.1.3:At every rising edge of [CLK_I] the terminating signal(ACK) is sampled.  If it
-  //is asserted, then  [STB_O]  is  negated. 
-  
-  assign ready_li = ( ack_ctr == 0 ) & !set_stb & !mem_resp_v_o;
-  assign mem_cmd_ready_o = ready_li;//!stb_o then ready to take!
- // assign v_li =  (ack_ctr == total_datafetch_cycle_lp-1);
-  assign mem_resp_v_o =  v_li;
-  assign stb_o = (set_stb) && !stb_justgotack; 
-  assign cyc_o = stb_o; 
-  assign sel_o = 8'b11111111; 
-  assign cti_o = 0;
-  assign bte_o = 0;
-
-  initial begin
-    ack_ctr = 0;
-  end
-  
-
-//Flip stb after each ack--->RULE 3.20:
-// Every time we get an ACK from WB, increment counter until the counter reaches to total_datafetch_cycle_lp
-  always_ff @(posedge clk_i)
-    begin
-      
-      if(reset_i)
-      begin
-        ack_ctr <= 0;
-        set_stb <= 0;
-        v_li <=0;
-      end
-      else if (v_li)
-      begin
-        if (mem_resp_yumi_i)
-        begin
-          v_li <= 0;
-          ack_ctr <= 0;
-        end
-      end
-      else if (mem_cmd_v_i)
-      begin
-        //data_li <= 0;
-        set_stb <= 1;
-        v_li <= 0;
-        stb_justgotack <= 0;
-      end
-      
-      else
-      begin
-        if (ack_i)//stb should be negated after ack
-        begin
-          stb_justgotack <= 1;
-          data_li[(ack_ctr*wbone_data_width) +: wbone_data_width] <= dat_i;
-          if ((ack_ctr == total_datafetch_cycle_lp-1) || (mem_cmd_addr_l < cached_addr_base && mem_cmd_r.header.msg_type == e_cce_mem_uc_wr )) //if uncached store, just one cycle is fine
-          begin 
-            v_li <=1;
-            set_stb <= 0;
-          end
-          else 
-            ack_ctr <= ack_ctr + 1; 
-        end
-        else
-        begin
-          stb_justgotack <= 0;
-          v_li <=0;
-        end
-      end
-    end
-
-  //Packet Pass from BP to BP2WB
-  assign mem_cmd_cast_i = mem_cmd_i;
-   bp_cce_mem_msg_s mem_cmd_r;
-   bsg_dff_reset_en
-  #(.width_p(cce_mem_msg_width_lp))
-    mshr_reg
-     (.clk_i(clk_i)
-      ,.reset_i(reset_i)
-      ,.en_i(mem_cmd_v_i)//when
-      ,.data_i(mem_cmd_i)
-      ,.data_o(mem_cmd_r)
-      );
-
- //Addr && Data && Command  Pass from BP2WB to WB 
-  logic [wbone_addr_lbound-1:0] throw_away; 
-  assign mem_cmd_addr_l =  mem_cmd_r.header.addr;
-  assign data_lo = mem_cmd_r.data;
-  logic [39:0] mem_cmd_addr_l_zero64;
-  always_comb begin
-    if( mem_cmd_addr_l < cached_addr_base )
-    begin 
-      adr_o = mem_cmd_addr_l[wbone_addr_ubound-1:wbone_addr_lbound];//no need to change address for uncached stores/loads
-      dat_o = data_lo[(0*wbone_data_width) +: wbone_data_width];//unchached data is stored in LS 64bits
-    end
-
-    else
-    begin
-      mem_cmd_addr_l_zero64 = mem_cmd_addr_l >> 6 << 6;
-      {adr_o,throw_away} =  mem_cmd_addr_l_zero64 + (ack_ctr*8);//TODO:careful
-      dat_o = data_lo[(ack_ctr*wbone_data_width) +: wbone_data_width];
-     end
-  end
-
-   assign we_o = (mem_cmd_r.header.msg_type inside {e_cce_mem_uc_wr, e_cce_mem_wb});
-
-//Data Pass from BP2WB to BP
-
-wire [cce_block_width_p-1:0]  rd_word_offset = mem_cmd_r.header.addr[3+:3];
-//wire [cce_block_width_p-1:0]  rd_byte_offset = mem_cmd_r.addr[0+:3];
-wire [cce_block_width_p-1:0]    rd_bit_shift = rd_word_offset*64; // We rely on receiver to adjust bits
-
-(* mark_debug = "true" *) wire [cce_block_width_p-1:0] data_li_resp = (mem_cmd_r.header.msg_type == e_cce_mem_uc_rd)
-                                            ? data_li >> rd_bit_shift
-                                            : data_li;
-
-
-
-assign mem_resp_cast_o = '{data     : data_li_resp
-                                ,header :'{payload : mem_cmd_r.header.payload
-                                ,size    : mem_cmd_r.header.size
-                                ,addr    : mem_cmd_r.header.addr
-                                ,msg_type: mem_cmd_r.header.msg_type
-                                }
-                                };
- 
-assign mem_resp_o = mem_resp_cast_o;
-
-/*********************************************/
-/*DEBUG SECTION*/
-  
-/*  always_comb
-  begin
-    if (mem_cmd_yumi_o == 1)// && mem_cmd_addr_l >=32'h8000_0000)
-    begin
-    mem_cmd_debug = mem_cmd_i;
-      if(mem_cmd_debug.addr >= 32'h80000000)
-      begin
-      $display("myarray == %x", mem_cmd_debug.addr);
-      $display("myarray == %x", mem_cmd_debug.msg_type);
-      if(mem_cmd_debug.msg_type>=3)
-      $display("myarray == %x", mem_cmd_debug.data);
-
-      end
-    end
-  end
-
-always_comb
-begin
-  if(mem_resp_v_o)
-  begin
-    mem_cmd_debug2 = mem_resp_o;
-    if(mem_cmd_debug2.addr >= 32'h80000000)
-    begin
-     $display("myresp == %x", mem_cmd_debug2.addr);
-    $display("myresp == %x", mem_cmd_debug2.msg_type);
-     if(mem_cmd_debug2.msg_type<=1)
-      $display("myresp == %x", mem_cmd_debug2.data);
-    end
-  end
-end
-*/
-
-/*wire [3:0] fake_msg_type;
-wire [10:0] fake_payload;
-wire [2:0] fake_size;
-wire [39:0] fake_addr;
-assign fake_payload = mem_cmd_r.header.payload;
-assign fake_size = mem_cmd_r.header.size;
-assign fake_addr = mem_cmd_r.header.addr;
-assign fake_msg_type = mem_cmd_r.header.msg_type;
-*/
-(* mark_debug = "true" *) logic debug_wire;
-  initial begin
-    debug_wire = 0;
-  end
-
-  assign mem_cmd_debug = mem_cmd_i;
-
-always_ff @(posedge clk_i)
-debug_wire <= (ack_i && mem_cmd_debug.header.addr >= 32'h80000000);
-
-/*  always_ff @(posedge clk_i)
-  begin
-      if(mem_cmd_v_i && mem_cmd_debug.header.addr >= 32'h80000000)
-      begin
-        debug_wire <= 1;
-        //        $display("addr == %x", mem_cmd_debug.header.addr);
-      end*/
-/*      if (mem_resp_v_o && debug_ctr < 64 && mem_cmd_debug.header.addr >= 32'h80000000)
-      begin
-        debug_gotdata[((debug_ctr-1)*512) +: 512] <= data_li_resp;
-        $display("data == %x", data_li_resp);
-      end*/
-//  end
-
-wire [3:0] typean;
-assign typean = mem_cmd_r.header.msg_type;
-
-endmodule
-
diff --git a/litex/soc/cores/cpu/blackparrot/bp_fpga/bsg_mem_1rw_sync_mask_write_bit.v b/litex/soc/cores/cpu/blackparrot/bp_fpga/bsg_mem_1rw_sync_mask_write_bit.v
deleted file mode 100644
index a6fdae9a6..000000000
--- a/litex/soc/cores/cpu/blackparrot/bp_fpga/bsg_mem_1rw_sync_mask_write_bit.v
+++ /dev/null
@@ -1,55 +0,0 @@
-/*
-* bsg_mem_1rw_sync_mask_write_bit.v
-*
-* distributed synchronous 1-port ram for xilinx ultrascale or ultrascale plus FPGA
-* Write mode: No-change | Read mode: No-change
-* Note:
-* There are 2 basic BRAM library primitives, RAMB18E2 and RAMB36E2 in Vivado.
-* But none of them support bit-wise mask. They have Byte-wide write enable ports though.
-* So we use the RAM_STYLE attribute to instruct the tool to infer distributed LUT RAM instead.
-*
-* To save resources, the code is written to be inferred as Signle-port distributed ram RAM64X1S.
-* https://www.xilinx.com/support/documentation/user_guides/ug574-ultrascale-clb.pdf
-*
-*/
-
-
-module bsg_mem_1rw_sync_mask_write_bit #(
-  parameter width_p = "inv"
-  , parameter els_p = "inv"
-  , parameter latch_last_read_p=0
-  , parameter enable_clock_gating_p=0
-  , localparam addr_width_lp = `BSG_SAFE_CLOG2(els_p)
-) (
-  input                      clk_i
-  , input                      reset_i
-  , input  [      width_p-1:0] data_i
-  , input  [addr_width_lp-1:0] addr_i
-  , input                      v_i
-  , input  [      width_p-1:0] w_mask_i
-  , input                      w_i
-  , output [      width_p-1:0] data_o
-);
-
-  wire unused = reset_i;
-
-  (* ram_style = "distributed" *) logic [width_p-1:0] mem [els_p-1:0];
-
-  logic [width_p-1:0] data_r;
-  always_ff @(posedge clk_i) begin
-    if (v_i & ~w_i)
-      data_r <= mem[addr_i];
-  end
-
-  assign data_o = data_r;
-
-  for (genvar i=0; i<width_p; i=i+1) begin
-    always_ff @(posedge clk_i) begin
-      if (v_i)
-        if (w_i & w_mask_i[i])
-          mem[addr_i][i] <= data_i[i];
-    end
-  end
-
-endmodule
-
diff --git a/litex/soc/cores/cpu/blackparrot/bp_fpga/fpga/ExampleBlackParrotSystem.v b/litex/soc/cores/cpu/blackparrot/bp_fpga/fpga/ExampleBlackParrotSystem.v
deleted file mode 100644
index 6e52cc209..000000000
--- a/litex/soc/cores/cpu/blackparrot/bp_fpga/fpga/ExampleBlackParrotSystem.v
+++ /dev/null
@@ -1,357 +0,0 @@
-/**
-  *
-  * ExampleBlackParrotSystem.v
-  *
-  */
-  
-`include "bsg_noc_links.vh"
-
-module ExampleBlackParrotSystem
- import bp_common_pkg::*;
- import bp_common_aviary_pkg::*;
- import bp_be_pkg::*;
- import bp_common_rv64_pkg::*;
- import bp_cce_pkg::*;
- import bp_me_pkg::*;
- import bp_common_cfg_link_pkg::*;
- import bsg_noc_pkg::*;
- #(parameter bp_params_e bp_params_p = e_bp_softcore_cfg
-   `declare_bp_proc_params(bp_params_p)
-   `declare_bp_me_if_widths(paddr_width_p, cce_block_width_p, lce_id_width_p, lce_assoc_p)
-
-   // Tracing parameters
-   , parameter calc_trace_p                = 0
-   , parameter cce_trace_p                 = 0
-   , parameter cmt_trace_p                 = 1
-   , parameter dram_trace_p                = 1
-   , parameter npc_trace_p                 = 0
-   , parameter dcache_trace_p              = 0
-   , parameter vm_trace_p                  = 0
-   , parameter preload_mem_p               = 1
-   , parameter load_nbf_p                  = 0
-   , parameter skip_init_p                 = 0
-   , parameter cosim_p                     = 0
-   , parameter cosim_cfg_file_p            = "prog.cfg"
-
-   , parameter mem_zero_p         = 1
-   , parameter mem_file_p         = "prog.mem"
-   , parameter mem_cap_in_bytes_p = 2**25
-   , parameter [paddr_width_p-1:0] mem_offset_p = paddr_width_p'(32'h8000_0000)
-
-   // Number of elements in the fake BlackParrot memory
-   , parameter use_max_latency_p      = 1
-   , parameter use_random_latency_p   = 0
-   , parameter use_dramsim2_latency_p = 0
-
-   , parameter max_latency_p = 15
-
-   , parameter dram_clock_period_in_ps_p = 1000
-   , parameter dram_cfg_p                = "dram_ch.ini"
-   , parameter dram_sys_cfg_p            = "dram_sys.ini"
-   , parameter dram_capacity_p           = 16384
-   )
-  (input clk_i
-   , input reset_i
-      //Wishbone interface
-   , input  [63:0]  wbm_dat_i
-   , output [63:0]  wbm_dat_o
-   , input          wbm_ack_i
-   , input          wbm_err_i
-//   , input          wbm_rty_i
-   , output [36:0]  wbm_adr_o //TODO parametrize this
-   , output         wbm_stb_o
-   , output         wbm_cyc_o
-   , output [7:0]   wbm_sel_o //TODO: how many  bits ? check
-   , output         wbm_we_o
-   , output [2:0]   wbm_cti_o //TODO:
-   , output [1:0]   wbm_bte_o
-  // , input  [3:0]   interrupts
-   );
-
-`declare_bp_me_if(paddr_width_p, cce_block_width_p, lce_id_width_p, lce_assoc_p)
-
-bp_cce_mem_msg_s proc_mem_cmd_lo;
-logic proc_mem_cmd_v_lo, proc_mem_cmd_ready_li;
-bp_cce_mem_msg_s proc_mem_resp_li;
-logic proc_mem_resp_v_li, proc_mem_resp_yumi_lo;
-
-bp_cce_mem_msg_s proc_io_cmd_lo;
-logic proc_io_cmd_v_lo, proc_io_cmd_ready_li;
-bp_cce_mem_msg_s proc_io_resp_li;
-logic proc_io_resp_v_li, proc_io_resp_yumi_lo;
-
-bp_cce_mem_msg_s io_cmd_lo;
-logic io_cmd_v_lo, io_cmd_ready_li;
-bp_cce_mem_msg_s io_resp_li;
-logic io_resp_v_li, io_resp_yumi_lo;
-bp_softcore
- #(.bp_params_p(bp_params_p))
- softcore
-  (.clk_i(clk_i)
-   ,.reset_i(reset_i)
-
-   ,.io_cmd_o(proc_io_cmd_lo)
-   ,.io_cmd_v_o(proc_io_cmd_v_lo)
-   ,.io_cmd_ready_i(proc_io_cmd_ready_li)
-
-   ,.io_resp_i(proc_io_resp_li)
-   ,.io_resp_v_i(proc_io_resp_v_li)
-   ,.io_resp_yumi_o(proc_io_resp_yumi_lo)
-
-   ,.mem_cmd_o(proc_mem_cmd_lo)
-   ,.mem_cmd_v_o(proc_mem_cmd_v_lo)
-   ,.mem_cmd_ready_i(proc_mem_cmd_ready_li)
-
-   ,.mem_resp_i(proc_mem_resp_li)
-   ,.mem_resp_v_i(proc_mem_resp_v_li)
-   ,.mem_resp_yumi_o(proc_mem_resp_yumi_lo)
-   );
-
- bp2wb_convertor
-   #(.bp_params_p(bp_params_p))
-   bp2wb
-    (.clk_i(clk_i)
-     ,.reset_i(reset_i)
-    ,.mem_cmd_i(proc_mem_cmd_lo)
-     ,.mem_cmd_v_i(proc_mem_cmd_v_lo & proc_mem_cmd_ready_li)
-     ,.mem_cmd_ready_o(proc_mem_cmd_ready_li)
-
-     ,.mem_resp_o(proc_mem_resp_li)
-     ,.mem_resp_v_o(proc_mem_resp_v_li)
-     ,.mem_resp_yumi_i(proc_mem_resp_yumi_lo)
-
-     ,.dat_i(wbm_dat_i)
-     ,.dat_o(wbm_dat_o)
-     ,.ack_i(wbm_ack_i)
-     ,.adr_o(wbm_adr_o)
-     ,.stb_o(wbm_stb_o)
-     ,.cyc_o(wbm_cyc_o)
-     ,.sel_o(wbm_sel_o )
-     ,.we_o(wbm_we_o)
-     ,.cti_o(wbm_cti_o)
-     ,.bte_o(wbm_bte_o )
-    // ,.rty_i(wbm_rty_i)
-     ,.err_i(wbm_err_i)
-     );
-
-/*
-bp_mem
- mem
-  (.clk_i(clk_i)
-   ,.reset_i(reset_i)
- 
-   ,.mem_cmd_i(proc_mem_cmd_lo)
-   ,.mem_cmd_v_i(proc_mem_cmd_v_lo & proc_mem_cmd_ready_li)
-   ,.mem_cmd_ready_o(proc_mem_cmd_ready_li)
- 
-   ,.mem_resp_o(proc_mem_resp_li)
-   ,.mem_resp_v_o(proc_mem_resp_v_li)
-   ,.mem_resp_yumi_i(proc_mem_resp_yumi_lo)
-   );
-*/
-logic program_finish_lo;
-assign proc_io_cmd_ready_li = 1;
-/*bp_nonsynth_host
- #(.bp_params_p(bp_params_p))
- host
-  (.clk_i(clk_i)
-   ,.reset_i(reset_i)
-
-   ,.io_cmd_i(proc_io_cmd_lo)
-   ,.io_cmd_v_i(proc_io_cmd_v_lo & proc_io_cmd_ready_li)
-   ,.io_cmd_ready_o(proc_io_cmd_ready_li)
-
-   ,.io_resp_o(proc_io_resp_li)
-   ,.io_resp_v_o(proc_io_resp_v_li)
-   ,.io_resp_yumi_i(proc_io_resp_yumi_lo)
-
-   ,.program_finish_o(program_finish_lo)
-   );
-*/
-/*bind bp_be_top
-  bp_nonsynth_commit_tracer
-   #(.bp_params_p(bp_params_p))
-   commit_tracer
-    (.clk_i(clk_i & (ExampleBlackParrotSystem.cmt_trace_p == 1))
-     ,.reset_i(reset_i)
-     ,.freeze_i('0)
-
-     ,.mhartid_i('0)
-
-     ,.commit_v_i(be_calculator.commit_pkt.instret)
-     ,.commit_pc_i(be_calculator.commit_pkt.pc)
-     ,.commit_instr_i(be_calculator.commit_pkt.instr)
-
-     ,.rd_w_v_i(be_calculator.wb_pkt.rd_w_v)
-     ,.rd_addr_i(be_calculator.wb_pkt.rd_addr)
-     ,.rd_data_i(be_calculator.wb_pkt.rd_data)
-     );
-*/
-/*  bind bp_be_top
-    bp_nonsynth_cosim
-     #(.bp_params_p(bp_params_p))
-      cosim
-      (.clk_i(clk_i)
-       ,.reset_i(reset_i)
-       ,.en_i(ExampleBlackParrotSystem.cosim_p == 1)
-
-       ,.mhartid_i(be_checker.scheduler.int_regfile.cfg_bus.core_id)
-       // Want to pass config file as a parameter, but cannot in Verilator 4.025
-       // Parameter-resolved constants must not use dotted references
-       ,.config_file_i(ExampleBlackParrotSystem.cosim_cfg_file_p)
-
-       ,.commit_v_i(be_calculator.commit_pkt.instret)
-       ,.commit_pc_i(be_calculator.commit_pkt.pc)
-       ,.commit_instr_i(be_calculator.commit_pkt.instr)
-
-       ,.rd_w_v_i(be_calculator.wb_pkt.rd_w_v)
-       ,.rd_addr_i(be_calculator.wb_pkt.rd_addr)
-       ,.rd_data_i(be_calculator.wb_pkt.rd_data)
-
-       ,.interrupt_v_i(be_mem.csr.trap_pkt_cast_o._interrupt)
-       ,.cause_i(be_mem.csr.trap_pkt_cast_o.cause)
-       );
-*/
-/*bind bp_be_top
-  bp_be_nonsynth_perf
-   #(.bp_params_p(bp_params_p))
-   perf
-    (.clk_i(clk_i)
-     ,.reset_i(reset_i)
-
-     ,.mhartid_i(be_checker.scheduler.int_regfile.cfg_bus.core_id)
-
-     ,.fe_nop_i(be_calculator.exc_stage_r[2].fe_nop_v)
-     ,.be_nop_i(be_calculator.exc_stage_r[2].be_nop_v)
-     ,.me_nop_i(be_calculator.exc_stage_r[2].me_nop_v)
-     ,.poison_i(be_calculator.exc_stage_r[2].poison_v)
-     ,.roll_i(be_calculator.exc_stage_r[2].roll_v)
-
-     ,.instr_cmt_i(be_calculator.commit_pkt.instret)
-
-     ,.program_finish_i(ExampleBlackParrotSystem.program_finish_lo)
-     );
-*/
- /* bind bp_be_director
-    bp_be_nonsynth_npc_tracer
-     #(.bp_params_p(bp_params_p))
-     npc_tracer
-      (.clk_i(clk_i & (ExampleBlackParrotSystem.npc_trace_p == 1))
-       ,.reset_i(reset_i)
-       ,.freeze_i('0)
-
-       ,.mhartid_i(be_checker.scheduler.int_regfile.cfg_bus.core_id)
-
-       ,.npc_w_v(npc_w_v)
-       ,.npc_n(npc_n)
-       ,.npc_r(npc_r)
-       ,.expected_npc_o(expected_npc_o)
-
-       ,.fe_cmd_i(fe_cmd)
-       ,.fe_cmd_v(fe_cmd_v)
-
-       ,.commit_pkt_i(commit_pkt)
-       );
-*/
-  /*bind bp_be_dcache
-    bp_be_nonsynth_dcache_tracer
-     #(.bp_params_p(bp_params_p))
-     dcache_tracer
-      (.clk_i(clk_i & (ExampleBlackParrotSystem.dcache_trace_p == 1))
-       ,.reset_i(reset_i)
-       ,.freeze_i('0)
-
-       ,.mhartid_i(cfg_bus_cast_i.core_id)
-
-       ,.v_tv_r(v_tv_r)
-       //,.cache_miss_i(cache_miss_i)
-
-       ,.paddr_tv_r(paddr_tv_r)
-       ,.uncached_tv_r(uncached_tv_r)
-       ,.load_op_tv_r(load_op_tv_r)
-       ,.store_op_tv_r(store_op_tv_r)
-       ,.lr_op_tv_r(lr_op_tv_r)
-       ,.sc_op_tv_r(sc_op_tv_r)
-       ,.store_data(data_tv_r)
-       ,.load_data(data_o)
-       );*/
-/*
-  bind bp_be_top
-    bp_be_nonsynth_calc_tracer
-     #(.bp_params_p(bp_params_p))
-     calc_tracer
-      (.clk_i(clk_i & (ExampleBlackParrotSystem.calc_trace_p == 1))
-       ,.reset_i(reset_i)
-       ,.freeze_i('0)
-
-       ,.mhartid_i(be_checker.scheduler.int_regfile.cfg_bus.core_id)
-
-       ,.issue_pkt_i(be_checker.scheduler.issue_pkt)
-       ,.issue_pkt_v_i(be_checker.scheduler.fe_queue_yumi_o)
-
-       ,.fe_nop_v_i(be_calculator.exc_stage_n[0].fe_nop_v)
-       ,.be_nop_v_i(be_calculator.exc_stage_n[0].be_nop_v)
-       ,.me_nop_v_i(be_calculator.exc_stage_n[0].me_nop_v)
-       ,.dispatch_pkt_i(be_calculator.dispatch_pkt)
-
-       ,.ex1_br_tgt_i(be_calculator.calc_status.ex1_npc)
-       ,.ex1_btaken_i(be_calculator.pipe_int.btaken)
-       ,.iwb_result_i(be_calculator.comp_stage_n[3])
-       ,.fwb_result_i(be_calculator.comp_stage_n[4])
-
-       ,.cmt_trace_exc_i(be_calculator.exc_stage_n[1+:5])
-
-       ,.trap_v_i(be_mem.csr.trap_pkt_cast_o._interrupt | be_mem.csr.trap_pkt_cast_o.exception)
-       ,.mtvec_i(be_mem.csr.mtvec_n)
-       ,.mtval_i(be_mem.csr.mtval_n[0+:vaddr_width_p])
-       ,.ret_v_i(be_mem.csr.trap_pkt_cast_o.eret)
-       ,.mepc_i(be_mem.csr.mepc_n[0+:vaddr_width_p])
-       ,.mcause_i(be_mem.csr.mcause_n)
-
-       ,.priv_mode_i(be_mem.csr.priv_mode_n)
-       ,.mpp_i(be_mem.csr.mstatus_n.mpp)
-       );
-
-  bind bp_core_minimal
-    bp_be_nonsynth_vm_tracer
-    #(.bp_params_p(bp_params_p))
-    vm_tracer
-      (.clk_i(clk_i & (ExampleBlackParrotSystem.vm_trace_p == 1))
-       ,.reset_i(reset_i)
-       ,.freeze_i('0)
-
-       ,.mhartid_i(be.be_checker.scheduler.int_regfile.cfg_bus.core_id)
-
-       ,.itlb_clear_i(fe.mem.itlb.flush_i)
-       ,.itlb_fill_v_i(fe.mem.itlb.v_i & fe.mem.itlb.w_i)
-       ,.itlb_vtag_i(fe.mem.itlb.vtag_i)
-       ,.itlb_entry_i(fe.mem.itlb.entry_i)
-
-       ,.dtlb_clear_i(be.be_mem.dtlb.flush_i)
-       ,.dtlb_fill_v_i(be.be_mem.dtlb.v_i & be.be_mem.dtlb.w_i)
-       ,.dtlb_vtag_i(be.be_mem.dtlb.vtag_i)
-       ,.dtlb_entry_i(be.be_mem.dtlb.entry_i)
-       );
-*/
-/*  bp_mem_nonsynth_tracer
-   #(.bp_params_p(bp_params_p))
-   bp_mem_tracer
-    (.clk_i(clk_i & (ExampleBlackParrotSystem.dram_trace_p == 1))
-     ,.reset_i(reset_i)
-
-     ,.mem_cmd_i(proc_mem_cmd_lo)
-     ,.mem_cmd_v_i(proc_mem_cmd_v_lo & proc_mem_cmd_ready_li)
-     ,.mem_cmd_ready_i(proc_mem_cmd_ready_li)
-
-     ,.mem_resp_i(proc_mem_resp_li)
-     ,.mem_resp_v_i(proc_mem_resp_v_li)
-     ,.mem_resp_yumi_i(proc_mem_resp_yumi_lo)
-     );
-*/
-/*bp_nonsynth_if_verif
- #(.bp_params_p(bp_params_p))
- if_verif
-  ();
-*/
-endmodule
-
diff --git a/litex/soc/cores/cpu/blackparrot/bp_fpga/simulation/ExampleBlackParrotSystem.v b/litex/soc/cores/cpu/blackparrot/bp_fpga/simulation/ExampleBlackParrotSystem.v
deleted file mode 100644
index 48fa4b482..000000000
--- a/litex/soc/cores/cpu/blackparrot/bp_fpga/simulation/ExampleBlackParrotSystem.v
+++ /dev/null
@@ -1,357 +0,0 @@
-/**
-  *
-  * ExampleBlackParrotSystem.v
-  *
-  */
-  
-`include "bsg_noc_links.vh"
-
-module ExampleBlackParrotSystem
- import bp_common_pkg::*;
- import bp_common_aviary_pkg::*;
- import bp_be_pkg::*;
- import bp_common_rv64_pkg::*;
- import bp_cce_pkg::*;
- import bp_me_pkg::*;
- import bp_common_cfg_link_pkg::*;
- import bsg_noc_pkg::*;
- #(parameter bp_params_e bp_params_p = e_bp_softcore_cfg
-   `declare_bp_proc_params(bp_params_p)
-   `declare_bp_me_if_widths(paddr_width_p, cce_block_width_p, lce_id_width_p, lce_assoc_p)
-
-   // Tracing parameters
-   , parameter calc_trace_p                = 0
-   , parameter cce_trace_p                 = 0
-   , parameter cmt_trace_p                 = 1
-   , parameter dram_trace_p                = 1
-   , parameter npc_trace_p                 = 0
-   , parameter dcache_trace_p              = 0
-   , parameter vm_trace_p                  = 0
-   , parameter preload_mem_p               = 1
-   , parameter load_nbf_p                  = 0
-   , parameter skip_init_p                 = 0
-   , parameter cosim_p                     = 0
-   , parameter cosim_cfg_file_p            = "prog.cfg"
-
-   , parameter mem_zero_p         = 1
-   , parameter mem_file_p         = "prog.mem"
-   , parameter mem_cap_in_bytes_p = 2**25
-   , parameter [paddr_width_p-1:0] mem_offset_p = paddr_width_p'(32'h8000_0000)
-
-   // Number of elements in the fake BlackParrot memory
-   , parameter use_max_latency_p      = 1
-   , parameter use_random_latency_p   = 0
-   , parameter use_dramsim2_latency_p = 0
-
-   , parameter max_latency_p = 15
-
-   , parameter dram_clock_period_in_ps_p = 1000
-   , parameter dram_cfg_p                = "dram_ch.ini"
-   , parameter dram_sys_cfg_p            = "dram_sys.ini"
-   , parameter dram_capacity_p           = 16384
-   )
-  (input clk_i
-   , input reset_i
-      //Wishbone interface
-   , input  [63:0]  wbm_dat_i
-   , output [63:0]  wbm_dat_o
-   , input          wbm_ack_i
-   , input          wbm_err_i
-//   , input          wbm_rty_i
-   , output [36:0]  wbm_adr_o //TODO parametrize this
-   , output         wbm_stb_o
-   , output         wbm_cyc_o
-   , output [7:0]   wbm_sel_o //TODO: how many  bits ? check
-   , output         wbm_we_o
-   , output [2:0]   wbm_cti_o //TODO:
-   , output [1:0]   wbm_bte_o
-  // , input  [3:0]   interrupts
-   );
-
-`declare_bp_me_if(paddr_width_p, cce_block_width_p, lce_id_width_p, lce_assoc_p)
-
-bp_cce_mem_msg_s proc_mem_cmd_lo;
-logic proc_mem_cmd_v_lo, proc_mem_cmd_ready_li;
-bp_cce_mem_msg_s proc_mem_resp_li;
-logic proc_mem_resp_v_li, proc_mem_resp_yumi_lo;
-
-bp_cce_mem_msg_s proc_io_cmd_lo;
-logic proc_io_cmd_v_lo, proc_io_cmd_ready_li;
-bp_cce_mem_msg_s proc_io_resp_li;
-logic proc_io_resp_v_li, proc_io_resp_yumi_lo;
-
-bp_cce_mem_msg_s io_cmd_lo;
-logic io_cmd_v_lo, io_cmd_ready_li;
-bp_cce_mem_msg_s io_resp_li;
-logic io_resp_v_li, io_resp_yumi_lo;
-bp_softcore
- #(.bp_params_p(bp_params_p))
- softcore
-  (.clk_i(clk_i)
-   ,.reset_i(reset_i)
-
-   ,.io_cmd_o(proc_io_cmd_lo)
-   ,.io_cmd_v_o(proc_io_cmd_v_lo)
-   ,.io_cmd_ready_i(proc_io_cmd_ready_li)
-
-   ,.io_resp_i(proc_io_resp_li)
-   ,.io_resp_v_i(proc_io_resp_v_li)
-   ,.io_resp_yumi_o(proc_io_resp_yumi_lo)
-
-   ,.mem_cmd_o(proc_mem_cmd_lo)
-   ,.mem_cmd_v_o(proc_mem_cmd_v_lo)
-   ,.mem_cmd_ready_i(proc_mem_cmd_ready_li)
-
-   ,.mem_resp_i(proc_mem_resp_li)
-   ,.mem_resp_v_i(proc_mem_resp_v_li)
-   ,.mem_resp_yumi_o(proc_mem_resp_yumi_lo)
-   );
-
- bp2wb_convertor
-   #(.bp_params_p(bp_params_p))
-   bp2wb
-    (.clk_i(clk_i)
-     ,.reset_i(reset_i)
-    ,.mem_cmd_i(proc_mem_cmd_lo)
-     ,.mem_cmd_v_i(proc_mem_cmd_v_lo & proc_mem_cmd_ready_li)
-     ,.mem_cmd_ready_o(proc_mem_cmd_ready_li)
-
-     ,.mem_resp_o(proc_mem_resp_li)
-     ,.mem_resp_v_o(proc_mem_resp_v_li)
-     ,.mem_resp_yumi_i(proc_mem_resp_yumi_lo)
-
-     ,.dat_i(wbm_dat_i)
-     ,.dat_o(wbm_dat_o)
-     ,.ack_i(wbm_ack_i)
-     ,.adr_o(wbm_adr_o)
-     ,.stb_o(wbm_stb_o)
-     ,.cyc_o(wbm_cyc_o)
-     ,.sel_o(wbm_sel_o )
-     ,.we_o(wbm_we_o)
-     ,.cti_o(wbm_cti_o)
-     ,.bte_o(wbm_bte_o )
-    // ,.rty_i(wbm_rty_i)
-     ,.err_i(wbm_err_i)
-     );
-
-/*
-bp_mem
- mem
-  (.clk_i(clk_i)
-   ,.reset_i(reset_i)
- 
-   ,.mem_cmd_i(proc_mem_cmd_lo)
-   ,.mem_cmd_v_i(proc_mem_cmd_v_lo & proc_mem_cmd_ready_li)
-   ,.mem_cmd_ready_o(proc_mem_cmd_ready_li)
- 
-   ,.mem_resp_o(proc_mem_resp_li)
-   ,.mem_resp_v_o(proc_mem_resp_v_li)
-   ,.mem_resp_yumi_i(proc_mem_resp_yumi_lo)
-   );
-*/
-logic program_finish_lo;
-assign proc_io_cmd_ready_li = 1;
-/*bp_nonsynth_host
- #(.bp_params_p(bp_params_p))
- host
-  (.clk_i(clk_i)
-   ,.reset_i(reset_i)
-
-   ,.io_cmd_i(proc_io_cmd_lo)
-   ,.io_cmd_v_i(proc_io_cmd_v_lo & proc_io_cmd_ready_li)
-   ,.io_cmd_ready_o(proc_io_cmd_ready_li)
-
-   ,.io_resp_o(proc_io_resp_li)
-   ,.io_resp_v_o(proc_io_resp_v_li)
-   ,.io_resp_yumi_i(proc_io_resp_yumi_lo)
-
-   ,.program_finish_o(program_finish_lo)
-   );
-*/
-bind bp_be_top
-  bp_nonsynth_commit_tracer
-   #(.bp_params_p(bp_params_p))
-   commit_tracer
-    (.clk_i(clk_i & (ExampleBlackParrotSystem.cmt_trace_p == 1))
-     ,.reset_i(reset_i)
-     ,.freeze_i('0)
-
-     ,.mhartid_i('0)
-
-     ,.commit_v_i(be_calculator.commit_pkt.instret)
-     ,.commit_pc_i(be_calculator.commit_pkt.pc)
-     ,.commit_instr_i(be_calculator.commit_pkt.instr)
-
-     ,.rd_w_v_i(be_calculator.wb_pkt.rd_w_v)
-     ,.rd_addr_i(be_calculator.wb_pkt.rd_addr)
-     ,.rd_data_i(be_calculator.wb_pkt.rd_data)
-     );
-
-/*  bind bp_be_top
-    bp_nonsynth_cosim
-     #(.bp_params_p(bp_params_p))
-      cosim
-      (.clk_i(clk_i)
-       ,.reset_i(reset_i)
-       ,.en_i(ExampleBlackParrotSystem.cosim_p == 1)
-
-       ,.mhartid_i(be_checker.scheduler.int_regfile.cfg_bus.core_id)
-       // Want to pass config file as a parameter, but cannot in Verilator 4.025
-       // Parameter-resolved constants must not use dotted references
-       ,.config_file_i(ExampleBlackParrotSystem.cosim_cfg_file_p)
-
-       ,.commit_v_i(be_calculator.commit_pkt.instret)
-       ,.commit_pc_i(be_calculator.commit_pkt.pc)
-       ,.commit_instr_i(be_calculator.commit_pkt.instr)
-
-       ,.rd_w_v_i(be_calculator.wb_pkt.rd_w_v)
-       ,.rd_addr_i(be_calculator.wb_pkt.rd_addr)
-       ,.rd_data_i(be_calculator.wb_pkt.rd_data)
-
-       ,.interrupt_v_i(be_mem.csr.trap_pkt_cast_o._interrupt)
-       ,.cause_i(be_mem.csr.trap_pkt_cast_o.cause)
-       );
-*/
-/*bind bp_be_top
-  bp_be_nonsynth_perf
-   #(.bp_params_p(bp_params_p))
-   perf
-    (.clk_i(clk_i)
-     ,.reset_i(reset_i)
-
-     ,.mhartid_i(be_checker.scheduler.int_regfile.cfg_bus.core_id)
-
-     ,.fe_nop_i(be_calculator.exc_stage_r[2].fe_nop_v)
-     ,.be_nop_i(be_calculator.exc_stage_r[2].be_nop_v)
-     ,.me_nop_i(be_calculator.exc_stage_r[2].me_nop_v)
-     ,.poison_i(be_calculator.exc_stage_r[2].poison_v)
-     ,.roll_i(be_calculator.exc_stage_r[2].roll_v)
-
-     ,.instr_cmt_i(be_calculator.commit_pkt.instret)
-
-     ,.program_finish_i(ExampleBlackParrotSystem.program_finish_lo)
-     );
-*/
- /* bind bp_be_director
-    bp_be_nonsynth_npc_tracer
-     #(.bp_params_p(bp_params_p))
-     npc_tracer
-      (.clk_i(clk_i & (ExampleBlackParrotSystem.npc_trace_p == 1))
-       ,.reset_i(reset_i)
-       ,.freeze_i('0)
-
-       ,.mhartid_i(be_checker.scheduler.int_regfile.cfg_bus.core_id)
-
-       ,.npc_w_v(npc_w_v)
-       ,.npc_n(npc_n)
-       ,.npc_r(npc_r)
-       ,.expected_npc_o(expected_npc_o)
-
-       ,.fe_cmd_i(fe_cmd)
-       ,.fe_cmd_v(fe_cmd_v)
-
-       ,.commit_pkt_i(commit_pkt)
-       );
-*/
-  /*bind bp_be_dcache
-    bp_be_nonsynth_dcache_tracer
-     #(.bp_params_p(bp_params_p))
-     dcache_tracer
-      (.clk_i(clk_i & (ExampleBlackParrotSystem.dcache_trace_p == 1))
-       ,.reset_i(reset_i)
-       ,.freeze_i('0)
-
-       ,.mhartid_i(cfg_bus_cast_i.core_id)
-
-       ,.v_tv_r(v_tv_r)
-       //,.cache_miss_i(cache_miss_i)
-
-       ,.paddr_tv_r(paddr_tv_r)
-       ,.uncached_tv_r(uncached_tv_r)
-       ,.load_op_tv_r(load_op_tv_r)
-       ,.store_op_tv_r(store_op_tv_r)
-       ,.lr_op_tv_r(lr_op_tv_r)
-       ,.sc_op_tv_r(sc_op_tv_r)
-       ,.store_data(data_tv_r)
-       ,.load_data(data_o)
-       );*/
-/*
-  bind bp_be_top
-    bp_be_nonsynth_calc_tracer
-     #(.bp_params_p(bp_params_p))
-     calc_tracer
-      (.clk_i(clk_i & (ExampleBlackParrotSystem.calc_trace_p == 1))
-       ,.reset_i(reset_i)
-       ,.freeze_i('0)
-
-       ,.mhartid_i(be_checker.scheduler.int_regfile.cfg_bus.core_id)
-
-       ,.issue_pkt_i(be_checker.scheduler.issue_pkt)
-       ,.issue_pkt_v_i(be_checker.scheduler.fe_queue_yumi_o)
-
-       ,.fe_nop_v_i(be_calculator.exc_stage_n[0].fe_nop_v)
-       ,.be_nop_v_i(be_calculator.exc_stage_n[0].be_nop_v)
-       ,.me_nop_v_i(be_calculator.exc_stage_n[0].me_nop_v)
-       ,.dispatch_pkt_i(be_calculator.dispatch_pkt)
-
-       ,.ex1_br_tgt_i(be_calculator.calc_status.ex1_npc)
-       ,.ex1_btaken_i(be_calculator.pipe_int.btaken)
-       ,.iwb_result_i(be_calculator.comp_stage_n[3])
-       ,.fwb_result_i(be_calculator.comp_stage_n[4])
-
-       ,.cmt_trace_exc_i(be_calculator.exc_stage_n[1+:5])
-
-       ,.trap_v_i(be_mem.csr.trap_pkt_cast_o._interrupt | be_mem.csr.trap_pkt_cast_o.exception)
-       ,.mtvec_i(be_mem.csr.mtvec_n)
-       ,.mtval_i(be_mem.csr.mtval_n[0+:vaddr_width_p])
-       ,.ret_v_i(be_mem.csr.trap_pkt_cast_o.eret)
-       ,.mepc_i(be_mem.csr.mepc_n[0+:vaddr_width_p])
-       ,.mcause_i(be_mem.csr.mcause_n)
-
-       ,.priv_mode_i(be_mem.csr.priv_mode_n)
-       ,.mpp_i(be_mem.csr.mstatus_n.mpp)
-       );
-
-  bind bp_core_minimal
-    bp_be_nonsynth_vm_tracer
-    #(.bp_params_p(bp_params_p))
-    vm_tracer
-      (.clk_i(clk_i & (ExampleBlackParrotSystem.vm_trace_p == 1))
-       ,.reset_i(reset_i)
-       ,.freeze_i('0)
-
-       ,.mhartid_i(be.be_checker.scheduler.int_regfile.cfg_bus.core_id)
-
-       ,.itlb_clear_i(fe.mem.itlb.flush_i)
-       ,.itlb_fill_v_i(fe.mem.itlb.v_i & fe.mem.itlb.w_i)
-       ,.itlb_vtag_i(fe.mem.itlb.vtag_i)
-       ,.itlb_entry_i(fe.mem.itlb.entry_i)
-
-       ,.dtlb_clear_i(be.be_mem.dtlb.flush_i)
-       ,.dtlb_fill_v_i(be.be_mem.dtlb.v_i & be.be_mem.dtlb.w_i)
-       ,.dtlb_vtag_i(be.be_mem.dtlb.vtag_i)
-       ,.dtlb_entry_i(be.be_mem.dtlb.entry_i)
-       );
-*/
-  bp_mem_nonsynth_tracer
-   #(.bp_params_p(bp_params_p))
-   bp_mem_tracer
-    (.clk_i(clk_i & (ExampleBlackParrotSystem.dram_trace_p == 1))
-     ,.reset_i(reset_i)
-
-     ,.mem_cmd_i(proc_mem_cmd_lo)
-     ,.mem_cmd_v_i(proc_mem_cmd_v_lo & proc_mem_cmd_ready_li)
-     ,.mem_cmd_ready_i(proc_mem_cmd_ready_li)
-
-     ,.mem_resp_i(proc_mem_resp_li)
-     ,.mem_resp_v_i(proc_mem_resp_v_li)
-     ,.mem_resp_yumi_i(proc_mem_resp_yumi_lo)
-     );
-
-/*bp_nonsynth_if_verif
- #(.bp_params_p(bp_params_p))
- if_verif
-  ();
-*/
-endmodule
-
diff --git a/litex/soc/cores/cpu/blackparrot/bp_hardware/bp_cce_mmio_cfg_loader.v b/litex/soc/cores/cpu/blackparrot/bp_hardware/bp_cce_mmio_cfg_loader.v
deleted file mode 100644
index 84f0cc01a..000000000
--- a/litex/soc/cores/cpu/blackparrot/bp_hardware/bp_cce_mmio_cfg_loader.v
+++ /dev/null
@@ -1,231 +0,0 @@
-/**
- *
- * Name:
- *   bp_cce_mmio_cfg_loader.v
- *
- * Description:
- *
- */
-
-module bp_cce_mmio_cfg_loader
-  import bp_common_pkg::*;
-  import bp_common_aviary_pkg::*;
-  import bp_cce_pkg::*;
-  import bp_cfg_link_pkg::*;
-  import bp_be_pkg::*;
-  import bp_be_dcache_pkg::*;
-  import bp_me_pkg::*;
-  #(parameter bp_cfg_e cfg_p = e_bp_inv_cfg
-    `declare_bp_proc_params(cfg_p)
-    `declare_bp_me_if_widths(paddr_width_p, cce_block_width_p, num_lce_p, lce_assoc_p)
-
-    , parameter inst_width_p          = "inv"
-    , parameter inst_ram_addr_width_p = "inv"
-    , parameter inst_ram_els_p        = "inv"
-    , parameter cce_ucode_filename_p  = "/tmp/cce_ucode.mem"
-    , parameter skip_ram_init_p       = 0
-    
-    , localparam bp_pc_entry_point_gp=39'h00_5000_0000 //SC_add
-    )
-  (input                                             clk_i
-   , input                                           reset_i
-
-   // Config channel
-   , output logic [cce_mem_msg_width_lp-1:0]         mem_cmd_o
-   , output logic                                    mem_cmd_v_o
-   , input                                           mem_cmd_yumi_i
-
-   // We don't need a response from the cfg network
-   , input [cce_mem_msg_width_lp-1:0]                mem_resp_i
-   , input                                           mem_resp_v_i
-   , output                                          mem_resp_ready_o
-   );
-
-  wire unused0 = &{mem_resp_i, mem_resp_v_i};
-  assign mem_resp_ready_o = 1'b1;
-   
- `declare_bp_me_if(paddr_width_p, cce_block_width_p, num_lce_p, lce_assoc_p);
-
-  bp_cce_mem_msg_s mem_cmd_cast_o;
-
-  assign mem_cmd_o = mem_cmd_cast_o;
-  
-  logic [`bp_cce_inst_width-1:0]    cce_inst_boot_rom [0:inst_ram_els_p-1];
-  logic [inst_ram_addr_width_p-1:0] cce_inst_boot_rom_addr;
-  logic [`bp_cce_inst_width-1:0]    cce_inst_boot_rom_data;
-  
-  initial $readmemb(cce_ucode_filename_p, cce_inst_boot_rom);
-
-  assign cce_inst_boot_rom_data = cce_inst_boot_rom[cce_inst_boot_rom_addr];
-
-  logic                        cfg_v_lo;
-  logic [cfg_core_width_p-1:0] cfg_core_lo;
-  logic [cfg_addr_width_p-1:0] cfg_addr_lo;
-  logic [cfg_data_width_p-1:0] cfg_data_lo;
-
-  (* mark_debug = "true" *) enum logic [3:0] {
-    RESET
-    ,BP_RESET_SET
-    ,BP_FREEZE_SET
-    ,BP_RESET_CLR
-    ,SEND_RAM_LO
-    ,SEND_RAM_HI
-    ,SEND_CCE_NORMAL
-    ,SEND_ICACHE_NORMAL
-    ,SEND_DCACHE_NORMAL
-    ,SEND_PC_LO
-    ,SEND_PC_HI
-    ,BP_FREEZE_CLR
-    ,DONE
-  } state_n, state_r;
-
-  logic [cfg_addr_width_p-1:0] ucode_cnt_r;
-  logic ucode_cnt_clr, ucode_cnt_inc;
-  bsg_counter_clear_up
-   #(.max_val_p(2**cfg_addr_width_p-1)
-     ,.init_val_p(0)
-     )
-   ucode_counter
-    (.clk_i(clk_i)
-     ,.reset_i(reset_i)
-
-     ,.clear_i(ucode_cnt_clr)
-     ,.up_i(ucode_cnt_inc & mem_cmd_yumi_i)
-
-     ,.count_o(ucode_cnt_r)
-     );
-
-  wire ucode_prog_done = (ucode_cnt_r == cfg_addr_width_p'(inst_ram_els_p-1));
-
-  always_ff @(posedge clk_i) 
-    begin
-      if (reset_i)
-        state_r <= RESET;
-      else if (mem_cmd_yumi_i || (state_r == RESET))
-        state_r <= state_n;
-    end
-
-  wire [7:0] unused;
-  assign {unused, cce_inst_boot_rom_addr} = cfg_addr_lo >> 1'b1;
-
-  always_comb
-    begin
-      mem_cmd_v_o = cfg_v_lo;
-
-      // uncached store
-      mem_cmd_cast_o.msg_type      = e_cce_mem_uc_wr;
-      mem_cmd_cast_o.addr          = bp_cfg_base_addr_gp;
-      mem_cmd_cast_o.payload       = '0;
-      mem_cmd_cast_o.size          = e_mem_size_8;
-      mem_cmd_cast_o.data          = cce_block_width_p'({cfg_core_lo, cfg_addr_lo, cfg_data_lo});
-    end
-
-  always_comb 
-    begin
-      ucode_cnt_clr = 1'b0;
-      ucode_cnt_inc = 1'b0;
-
-      cfg_v_lo = '0;
-      cfg_core_lo = 8'hff;
-      cfg_addr_lo = '0;
-      cfg_data_lo = '0;
-
-      case (state_r)
-        RESET: begin
-          state_n = skip_ram_init_p ? BP_FREEZE_CLR : BP_RESET_SET;
-
-          ucode_cnt_clr = 1'b1;
-        end
-        BP_RESET_SET: begin
-          state_n = BP_FREEZE_SET;
-
-          cfg_v_lo = 1'b1;
-          cfg_addr_lo = bp_cfg_reg_reset_gp;
-          cfg_data_lo = cfg_data_width_p'(1);
-        end
-        BP_FREEZE_SET: begin
-          state_n = BP_RESET_CLR;
-
-          cfg_v_lo = 1'b1;
-          cfg_addr_lo = bp_cfg_reg_freeze_gp;
-          cfg_data_lo = cfg_data_width_p'(1);
-        end
-        BP_RESET_CLR: begin
-          state_n = SEND_RAM_LO;
-
-          cfg_v_lo = 1'b1;
-          cfg_addr_lo = bp_cfg_reg_reset_gp;
-          cfg_data_lo = cfg_data_width_p'(0);
-        end
-        SEND_RAM_LO: begin
-          state_n = SEND_RAM_HI;
-
-          cfg_v_lo = 1'b1;
-          cfg_addr_lo = cfg_addr_width_p'(bp_cfg_mem_base_cce_ucode_gp) + (ucode_cnt_r << 1);
-          cfg_data_lo = cce_inst_boot_rom_data[0+:cfg_data_width_p];
-          // TODO: This is nonsynth, won't work on FPGA
-          cfg_data_lo = (|cfg_data_lo === 'X) ? '0 : cfg_data_lo;
-        end
-        SEND_RAM_HI: begin
-          state_n = ucode_prog_done ? SEND_CCE_NORMAL : SEND_RAM_LO;
-
-          ucode_cnt_inc = 1'b1;
-
-          cfg_v_lo = 1'b1;
-          cfg_addr_lo = cfg_addr_width_p'(bp_cfg_mem_base_cce_ucode_gp) + (ucode_cnt_r << 1) + 1'b1;
-          cfg_data_lo = cfg_data_width_p'(cce_inst_boot_rom_data[inst_width_p-1:cfg_data_width_p]);
-          // TODO: This is nonsynth, won't work on FPGA
-          cfg_data_lo = (|cfg_data_lo === 'X) ? '0 : cfg_data_lo;
-        end
-        SEND_CCE_NORMAL: begin
-          state_n = SEND_ICACHE_NORMAL;
-
-          cfg_v_lo = 1'b1;
-          cfg_addr_lo = bp_cfg_reg_cce_mode_gp;
-          cfg_data_lo = cfg_data_width_p'(e_cce_mode_normal);
-        end
-        SEND_ICACHE_NORMAL: begin
-          state_n = SEND_DCACHE_NORMAL;
-
-          cfg_v_lo = 1'b1;
-          cfg_addr_lo = cfg_addr_width_p'(bp_cfg_reg_icache_mode_gp);
-          cfg_data_lo = cfg_data_width_p'(e_dcache_lce_mode_normal); // TODO: tapeout hack, change to icache
-        end
-        SEND_DCACHE_NORMAL: begin
-          state_n = SEND_PC_LO;
-
-          cfg_v_lo = 1'b1;
-          cfg_addr_lo = cfg_addr_width_p'(bp_cfg_reg_dcache_mode_gp);
-          cfg_data_lo = cfg_data_width_p'(e_dcache_lce_mode_normal);
-        end
-        SEND_PC_LO: begin
-          state_n = SEND_PC_HI;
-
-          cfg_v_lo = 1'b1;
-          cfg_addr_lo = cfg_addr_width_p'(bp_cfg_reg_start_pc_lo_gp);
-          cfg_data_lo = bp_pc_entry_point_gp[0+:cfg_data_width_p];
-        end
-        SEND_PC_HI: begin
-          state_n = BP_FREEZE_CLR;
-
-          cfg_v_lo = 1'b1;
-          cfg_addr_lo = cfg_addr_width_p'(bp_cfg_reg_start_pc_hi_gp);
-          cfg_data_lo = cfg_data_width_p'(bp_pc_entry_point_gp[vaddr_width_p-1:cfg_data_width_p]);
-        end
-        BP_FREEZE_CLR: begin
-          state_n = DONE;
-
-          cfg_v_lo = 1'b1;
-          cfg_addr_lo = cfg_addr_width_p'(bp_cfg_reg_freeze_gp);
-          cfg_data_lo = cfg_data_width_p'(0);;
-        end
-        DONE: begin
-          state_n = DONE;
-        end
-        default: begin
-          state_n = RESET;
-        end
-      endcase
-    end
-
-endmodule
diff --git a/litex/soc/cores/cpu/blackparrot/bp_hardware/bp_common_pkg.vh b/litex/soc/cores/cpu/blackparrot/bp_hardware/bp_common_pkg.vh
deleted file mode 100644
index 9500673b8..000000000
--- a/litex/soc/cores/cpu/blackparrot/bp_hardware/bp_common_pkg.vh
+++ /dev/null
@@ -1,55 +0,0 @@
-/* 
- * bp_common_pkg.vh
- *
- * Contains the interface structures used for communicating between FE, BE, ME in BlackParrot.
- * Additionally contains global parameters used to configure the system. In the future, when 
- *   multiple configurations are supported, these global parameters will belong to groups 
- *   e.g. SV39, VM-disabled, ...
- *
- */
-
-package bp_common_pkg;
-
-  `include "bsg_defines.v"
-  `include "bp_common_defines.vh"
-  `include "bp_common_fe_be_if.vh"
-  `include "bp_common_me_if.vh"
-
-  /*
-   * RV64 specifies a 64b effective address and 32b instruction.
-   * BlackParrot supports SV39 virtual memory, which specifies 39b virtual / 56b physical address.
-   * Effective addresses must have bits 39-63 match bit 38 
-   *   or a page fault exception will occur during translation.
-   * Currently, we only support a very limited number of parameter configurations.
-   * Thought: We could have a `define surrounding core instantiations of each parameter and then
-   * when they import this package, `declare the if structs. No more casting!
-   */
-
-  localparam bp_eaddr_width_gp = 64;
-  localparam bp_instr_width_gp = 32;
-
-  parameter bp_sv39_page_table_depth_gp = 3;
-  parameter bp_sv39_pte_width_gp = 64;
-  parameter bp_sv39_vaddr_width_gp = 39;
-  parameter bp_sv39_paddr_width_gp = 56;
-  parameter bp_sv39_ppn_width_gp = 44;
-  parameter bp_page_size_in_bytes_gp = 4096;
-  parameter bp_page_offset_width_gp = `BSG_SAFE_CLOG2(bp_page_size_in_bytes_gp);
-
-  parameter bp_data_resp_num_flit_gp = 4;
-  parameter bp_data_cmd_num_flit_gp = 4;
- 
-  localparam dram_base_addr_gp         = 32'h5000_0000;
- 
-  localparam cfg_link_dev_base_addr_gp = 32'h01??_????;
-  localparam clint_dev_base_addr_gp    = 32'h02??_????;
-  localparam host_dev_base_addr_gp     = 32'h03??_????;
-  localparam plic_dev_base_addr_gp     = 32'h0c??_????;
-  
-  localparam mipi_reg_base_addr_gp     = 32'h0200_0???;
-  localparam mtimecmp_reg_base_addr_gp = 32'h0200_4???;
-  localparam mtime_reg_addr_gp         = 32'h0200_bff8;
-  localparam plic_reg_base_addr_gp     = 32'h0c00_0???;
-
-endpackage : bp_common_pkg
-
diff --git a/litex/soc/cores/cpu/blackparrot/bp_hardware/bp_nonsynth_host.v b/litex/soc/cores/cpu/blackparrot/bp_hardware/bp_nonsynth_host.v
deleted file mode 100644
index e64ce690a..000000000
--- a/litex/soc/cores/cpu/blackparrot/bp_hardware/bp_nonsynth_host.v
+++ /dev/null
@@ -1,190 +0,0 @@
-
-module bp_nonsynth_host
- import bp_common_pkg::*;
- import bp_common_aviary_pkg::*;
- import bp_be_pkg::*;
- import bp_common_rv64_pkg::*;
- import bp_cce_pkg::*;
- import bsg_noc_pkg::*;
- import bp_cfg_link_pkg::*;
- #(parameter bp_cfg_e cfg_p = e_bp_inv_cfg
-   `declare_bp_proc_params(cfg_p)
-   `declare_bp_me_if_widths(paddr_width_p, cce_block_width_p, num_lce_p, lce_assoc_p)
-   )
-  (input clk_i
-   , input reset_i
-
-   , input [cce_mem_msg_width_lp-1:0]              mem_cmd_i
-   , input                                         mem_cmd_v_i
-   , output logic                                  mem_cmd_yumi_o
-
-   , output logic [cce_mem_msg_width_lp-1:0]       mem_resp_o
-   , output logic                                  mem_resp_v_o
-   , input                                         mem_resp_ready_i
-
-   , output [num_core_p-1:0]                       program_finish_o
-   ,(* mark_debug = "true" *) output logic                                  all_finished_debug_o //SC_add
-   , (* mark_debug = "true" *) output logic                                 core_passed_debug
-   , (* mark_debug = "true" *) output logic                                 core_failed_debug
-   );
-
-`declare_bp_me_if(paddr_width_p, cce_block_width_p, num_lce_p, lce_assoc_p);
-
-// HOST I/O mappings
-//localparam host_dev_base_addr_gp     = 32'h03??_????;
-
-// Host I/O mappings (arbitrarily decided for now)
-//   Overall host controls 32'h0300_0000-32'h03FF_FFFF
-
-localparam hprint_base_addr_gp = paddr_width_p'(32'h0300_0???);
-localparam cprint_base_addr_gp = paddr_width_p'(64'h0300_1???);
-localparam finish_base_addr_gp = paddr_width_p'(64'h0300_2???);
-
-bp_cce_mem_msg_s  mem_cmd_cast_i;
-
-assign mem_cmd_cast_i = mem_cmd_i;
-
-localparam lg_num_core_lp = `BSG_SAFE_CLOG2(num_core_p);
-
-logic hprint_data_cmd_v;
-logic cprint_data_cmd_v;
-logic finish_data_cmd_v;
-
-always_comb
-  begin
-    hprint_data_cmd_v = 1'b0;
-    cprint_data_cmd_v = 1'b0;
-    finish_data_cmd_v = 1'b0;
-
-    unique
-    casez (mem_cmd_cast_i.addr)
-      hprint_base_addr_gp: hprint_data_cmd_v = mem_cmd_v_i; 
-      cprint_base_addr_gp: cprint_data_cmd_v = mem_cmd_v_i;
-      finish_base_addr_gp: finish_data_cmd_v = mem_cmd_v_i;
-      default: begin end
-    endcase
-  end
-
-logic [num_core_p-1:0] hprint_w_v_li;
-logic [num_core_p-1:0] cprint_w_v_li;
-logic [num_core_p-1:0] finish_w_v_li;
-
-// Memory-mapped I/O is 64 bit aligned
-localparam byte_offset_width_lp = 3;
-wire [lg_num_core_lp-1:0] mem_cmd_core_enc =
-  mem_cmd_cast_i.addr[byte_offset_width_lp+:lg_num_core_lp];
-
-bsg_decode_with_v
- #(.num_out_p(num_core_p))
- hprint_data_cmd_decoder
-  (.v_i(hprint_data_cmd_v)
-   ,.i(mem_cmd_core_enc)
-   
-   ,.o(hprint_w_v_li)
-   );
-
-bsg_decode_with_v
- #(.num_out_p(num_core_p))
- cprint_data_cmd_decoder
-  (.v_i(cprint_data_cmd_v)
-   ,.i(mem_cmd_core_enc)
-
-   ,.o(cprint_w_v_li)
-   );
-
-bsg_decode_with_v
- #(.num_out_p(num_core_p))
- finish_data_cmd_decoder
-  (.v_i(finish_data_cmd_v)
-   ,.i(mem_cmd_core_enc)
-
-   ,.o(finish_w_v_li)
-   );
-
-logic [num_core_p-1:0] finish_r;
-bsg_dff_reset
- #(.width_p(num_core_p))
- finish_accumulator
-  (.clk_i(clk_i)
-   ,.reset_i(reset_i)
-
-   ,.data_i(finish_r | finish_w_v_li)
-   ,.data_o(finish_r)
-   );
-
-logic all_finished_r;
-bsg_dff_reset
- #(.width_p(1))
- all_finished_reg
-  (.clk_i(clk_i)
-   ,.reset_i(reset_i)
-
-   ,.data_i(&finish_r)
-   ,.data_o(all_finished_r)
-   );
-
-assign program_finish_o = finish_r;
-
-always_ff @(negedge clk_i)
-  begin
-    for (integer i = 0; i < num_core_p; i++)
-      begin
-        if (hprint_w_v_li[i] & mem_cmd_yumi_o)
-          $display("[CORE%0x PRT] %x", i, mem_cmd_cast_i.data[0+:8]);
-        if (cprint_w_v_li[i] & mem_cmd_yumi_o)
-          $display("[CORE%0x PRT] %c", i, mem_cmd_cast_i.data[0+:8]);
-        if (finish_w_v_li[i] & mem_cmd_yumi_o & ~mem_cmd_cast_i.data[0])
-        begin
-          $display("[CORE%0x FSH] PASS", i);
-          core_passed_debug <= 1;
-        end  
-        if (finish_w_v_li[i] & mem_cmd_yumi_o &  mem_cmd_cast_i.data[0])
-        begin
-          $display("[CORE%0x FSH] FAIL", i);
-          core_failed_debug <=1;
-        end
-      end
-
-    if (all_finished_r)
-      begin
-        $display("All cores finished! Terminating...");
-        $finish();
-        all_finished_debug_o <= 1;
-      end
-    if (reset_i)
-    begin
-      all_finished_debug_o <= 0;
-      core_passed_debug <= 0;
-      core_failed_debug <= 0;
-    end
-  end
-bp_cce_mem_msg_s mem_resp_lo;
-logic mem_resp_v_lo, mem_resp_ready_lo;
-assign mem_cmd_yumi_o = mem_cmd_v_i & mem_resp_ready_lo;
-bsg_one_fifo
- #(.width_p(cce_mem_msg_width_lp))
- mem_resp_buffer
-  (.clk_i(clk_i)
-   ,.reset_i(reset_i)
-
-   ,.data_i(mem_resp_lo)
-   ,.v_i(mem_cmd_yumi_o)
-   ,.ready_o(mem_resp_ready_lo)
-
-   ,.data_o(mem_resp_o)
-   ,.v_o(mem_resp_v_lo)
-   ,.yumi_i(mem_resp_ready_i & mem_resp_v_lo)
-   );
-assign mem_resp_v_o = mem_resp_v_lo & mem_resp_ready_i;
-
-assign mem_resp_lo =
-  '{msg_type       : mem_cmd_cast_i.msg_type
-    ,addr          : mem_cmd_cast_i.addr
-    ,payload       : mem_cmd_cast_i.payload
-    ,size          : mem_cmd_cast_i.size
-    ,data          : '0
-    };
-
-
-endmodule : bp_nonsynth_host
-
diff --git a/litex/soc/cores/cpu/blackparrot/bp_software/cce_ucode.mem b/litex/soc/cores/cpu/blackparrot/bp_software/cce_ucode.mem
deleted file mode 100644
index 5815a7323..000000000
--- a/litex/soc/cores/cpu/blackparrot/bp_software/cce_ucode.mem
+++ /dev/null
@@ -1,96 +0,0 @@
-010001000001111100000000000000000000000001000000
-001000000001111100000000000010110000000000000000
-000001000000000011111000000000000000100000000000
-010001000011111100000000000000000000000000000010
-001000000011111100000000000000010000000000000000
-000001000010000111111000000000000000100000000000
-010001000101111100000000000000000000000000001000
-001000000101111100000000000001000000000000000000
-000001000100001011111000000000000000100000000000
-101001000000010010100110100000000000000000000000
-001111000000000000000000000001110000000000000000
-010001000001111100000000000000000000000000000000
-010001000011111100000000000000000000000000000010
-001101000010000000000000000110000000000000000000
-010001000101111100000000000000000000000000000000
-010001000111111100000000000000000000000001000000
-010001001001111100000000000000000000000000000000
-001101000110001000000000000101100000000000000000
-111001000001000001001100100100000000000000000000
-000000000100001011111000000000000000100000000000
-000000001000010011111000000000100000000000000000
-001111000000000000000000000100010000000000000000
-000000000000000011111000000000000000100000000000
-001111000000000000000000000011010000000000000000
-010001000001111100000000000000000000000000000000
-010001000011111100000000000000000000000000000010
-010001000111111100000000000000000000000000000000
-001101000010000000000000001000010000000000000000
-111001000000000010101100100100000000000000000000
-111010011001000000000000000000000000000000000000
-001001000110010000000000010111110000000000000000
-000000000000000011111000000000000000100000000000
-001111000000000000000000000110110000000000000000
-111000010000000000000000000000000000000000000000
-110001000000000000000000000000000000000000000000
-111011000000000000000000000000000000000000000000
-001010000011111100000000010110010000000000000001
-100000100000000000000000000000000000000000000000
-001010001001111100000000001000010000000000000001
-111010000000000000000000000000000000000000000000
-100001100010000000100000000000000000000000000000
-110000000000000000000000000000000000000000000000
-001010000001111100000000001100010000000000000001
-001010000101111100000000001011110000000000000001
-001010001101111100000000001011110000000000000001
-010100000001111100000000000000000000000000000010
-001111000000000000000000001100100000000000000000
-010100000001111100000000000000000000000000000001
-001111000000000000000000001100100000000000000000
-010100000001111100000000000000000000000000000110
-001010011011111100000000010000110000000000000000
-010001000001111100000000000000000000000000000000
-010001000011111100000000000000000000000000000010
-010001000101111100000000000000000000000000000000
-010001000111111100000000000000000000000000000001
-001101000010000000000000001111110000000000000000
-001011000001111100000000001111010000000000000000
-001011010000000000000000001111010000000000000000
-000000000100001011111000000000000000100000000000
-111001000110000010001010100100000000000000000000
-101010100000001010100100000000000000000000000000
-000000000000000011111000000000000000100000000000
-001111000000000000000000001101110000000000000000
-001000000101111100000000010000110000000000000000
-111010011001000000000000000000000000000000000000
-000001000100001011111000000000000000100000000000
-001111000000000000000000001111110000000000000000
-001010011001111100000000010001110000000000000000
-101010100010001000100000000000000000000000000000
-111001000101100010001000100100000000000000000000
-001111000000000000000000001000010000000000000000
-101001100010001001100010000000000000000000000000
-001010010111111100000000010011110000000000000000
-111001000011100010011011100100000000000000000000
-111011011000000000000000000000000000000000000000
-001010011101111100000000010011010000000000000001
-111001010100101010101100100000000000000000000000
-111010011000000000000000000000000000000000000000
-011000010110000000000000000000000000000000000000
-001010010101111100000000010101110000000000000000
-111001000010100110001001100100000000000000000000
-111001000011100110001001100100000000000000000000
-111011011000000000000000000000000000000000000000
-001010011101111100000000010101010000000000000001
-111001010100101010101100100100000000000000000000
-111010011000000000000000000000000000000000000000
-001111000000000000000000001000010000000000000000
-111001010000101010101100100100000000000000000000
-001111000000000000000000001000010000000000000000
-111010000000000000000000000000000000000000000000
-001010000001111100000000010111010000000000000001
-111001010000101010101100100100000000000000000000
-001111000000000000000000001000010000000000000000
-111001010000101010101100100100000000000000000000
-001111000000000000000000001000010000000000000000
-110111000000000000000000000000000000000000000000
diff --git a/litex/soc/cores/cpu/blackparrot/bp_software/udivmoddi4.c b/litex/soc/cores/cpu/blackparrot/bp_software/udivmoddi4.c
deleted file mode 100644
index a57c6e0e6..000000000
--- a/litex/soc/cores/cpu/blackparrot/bp_software/udivmoddi4.c
+++ /dev/null
@@ -1,358 +0,0 @@
-/* ===-- udivmoddi4.c - Implement __udivmoddi4 -----------------------------===
- *
- *                     The LLVM Compiler Infrastructure
- *
- * This file is dual licensed under the MIT and the University of Illinois Open
- * Source Licenses. See LICENSE.TXT for details.
- *
- * ===----------------------------------------------------------------------===
- *
- * This file implements __udivmoddi4 for the compiler_rt library.
- *
- * ===----------------------------------------------------------------------===
- */
-
-#ifndef __blackparrot__
-#include "int_lib.h"
-
-/* Effects: if rem != 0, *rem = a % b
- * Returns: a / b
- */
-
-/* Translated from Figure 3-40 of The PowerPC Compiler Writer's Guide */
-
-COMPILER_RT_ABI du_int
-__udivmoddi4(du_int a, du_int b, du_int* rem)
-{
-    const unsigned n_uword_bits = sizeof(su_int) * CHAR_BIT;
-    const unsigned n_udword_bits = sizeof(du_int) * CHAR_BIT;
-    udwords n;
-    n.all = a;
-    udwords d;
-    d.all = b;
-    udwords q;
-    udwords r;
-    unsigned sr;
-    /* special cases, X is unknown, K != 0 */
-    if (n.s.high == 0)
-    {
-        if (d.s.high == 0)
-        {
-            /* 0 X
-             * ---
-             * 0 X
-             */
-            if (rem)
-                *rem = n.s.low % d.s.low;
-            return n.s.low / d.s.low;
-        }
-        /* 0 X
-         * ---
-         * K X
-         */
-        if (rem)
-            *rem = n.s.low;
-        return 0;
-    }
-    /* n.s.high != 0 */
-    if (d.s.low == 0)
-    {
-        if (d.s.high == 0)
-        {
-            /* K X
-             * ---
-             * 0 0
-             */ 
-            if (rem)
-                *rem = n.s.high % d.s.low;
-            return n.s.high / d.s.low;
-        }
-        /* d.s.high != 0 */
-        if (n.s.low == 0)
-        {
-            /* K 0
-             * ---
-             * K 0
-             */
-            if (rem)
-            {
-                r.s.high = n.s.high % d.s.high;
-                r.s.low = 0;
-                *rem = r.all;
-            }
-            return n.s.high / d.s.high;
-        }
-        /* K K
-         * ---
-         * K 0
-         */
-        if ((d.s.high & (d.s.high - 1)) == 0)     /* if d is a power of 2 */
-        {
-            if (rem)
-            {
-                r.s.low = n.s.low;
-                r.s.high = n.s.high & (d.s.high - 1);
-                *rem = r.all;
-            }
-            return n.s.high >> __builtin_ctz(d.s.high);
-        }
-        /* K K
-         * ---
-         * K 0
-         */
-        sr = __builtin_clz(d.s.high) - __builtin_clz(n.s.high);
-        /* 0 <= sr <= n_uword_bits - 2 or sr large */
-        if (sr > n_uword_bits - 2)
-        {
-           if (rem)
-                *rem = n.all;
-            return 0;
-        }
-        ++sr;
-        /* 1 <= sr <= n_uword_bits - 1 */
-        /* q.all = n.all << (n_udword_bits - sr); */
-        q.s.low = 0;
-        q.s.high = n.s.low << (n_uword_bits - sr);
-        /* r.all = n.all >> sr; */
-        r.s.high = n.s.high >> sr;
-        r.s.low = (n.s.high << (n_uword_bits - sr)) | (n.s.low >> sr);
-    }
-    else  /* d.s.low != 0 */
-    {
-        if (d.s.high == 0)
-        {
-            /* K X
-             * ---
-             * 0 K
-             */
-            if ((d.s.low & (d.s.low - 1)) == 0)     /* if d is a power of 2 */
-            {
-                if (rem)
-                    *rem = n.s.low & (d.s.low - 1);
-                if (d.s.low == 1)
-                    return n.all;
-                sr = __builtin_ctz(d.s.low);
-                q.s.high = n.s.high >> sr;
-                q.s.low = (n.s.high << (n_uword_bits - sr)) | (n.s.low >> sr);
-                return q.all;
-            }
-            /* K X
-             * ---
-             * 0 K
-             */
-            sr = 1 + n_uword_bits + __builtin_clz(d.s.low) - __builtin_clz(n.s.high);
-            /* 2 <= sr <= n_udword_bits - 1
-             * q.all = n.all << (n_udword_bits - sr);
-             * r.all = n.all >> sr;
-             */
-            if (sr == n_uword_bits)
-            {
-                q.s.low = 0;
-                q.s.high = n.s.low;
-                r.s.high = 0;
-                r.s.low = n.s.high;
-            }
-            else if (sr < n_uword_bits)  // 2 <= sr <= n_uword_bits - 1
-            {
-                q.s.low = 0;
-                q.s.high = n.s.low << (n_uword_bits - sr);
-                r.s.high = n.s.high >> sr;
-                r.s.low = (n.s.high << (n_uword_bits - sr)) | (n.s.low >> sr);
-            }
-            else              // n_uword_bits + 1 <= sr <= n_udword_bits - 1
-            {
-                q.s.low = n.s.low << (n_udword_bits - sr);
-                q.s.high = (n.s.high << (n_udword_bits - sr)) |
-                           (n.s.low >> (sr - n_uword_bits));
-                r.s.high = 0;
-                r.s.low = n.s.high >> (sr - n_uword_bits);
-            }
-        }
-        else
-        {
-            /* K X
-             * ---
-             * K K
-             */
-            sr = __builtin_clz(d.s.high) - __builtin_clz(n.s.high);
-            /* 0 <= sr <= n_uword_bits - 1 or sr large */
-            if (sr > n_uword_bits - 1)
-            {
-                if (rem)
-                    *rem = n.all;
-                return 0;
-            }
-            ++sr;
-            /* 1 <= sr <= n_uword_bits */
-            /*  q.all = n.all << (n_udword_bits - sr); */
-            q.s.low = 0;
-            if (sr == n_uword_bits)
-            {
-                q.s.high = n.s.low;
-                r.s.high = 0;
-                r.s.low = n.s.high;
-            }
-            else
-            {
-                q.s.high = n.s.low << (n_uword_bits - sr);
-                r.s.high = n.s.high >> sr;
-                r.s.low = (n.s.high << (n_uword_bits - sr)) | (n.s.low >> sr);
-            }
-        }
-    }
-    /* Not a special case
-     * q and r are initialized with:
-     * q.all = n.all << (n_udword_bits - sr);
-     * r.all = n.all >> sr;
-     * 1 <= sr <= n_udword_bits - 1
-     */
-    su_int carry = 0;
-    for (; sr > 0; --sr)
-    {
-        /* r:q = ((r:q)  << 1) | carry */
-        r.s.high = (r.s.high << 1) | (r.s.low  >> (n_uword_bits - 1));
-        r.s.low  = (r.s.low  << 1) | (q.s.high >> (n_uword_bits - 1));
-        q.s.high = (q.s.high << 1) | (q.s.low  >> (n_uword_bits - 1));
-        q.s.low  = (q.s.low  << 1) | carry;
-        /* carry = 0;
-         * if (r.all >= d.all)
-         * {
-         *      r.all -= d.all;
-         *      carry = 1;
-         * }
-         */
-        const di_int s = (di_int)(d.all - r.all - 1) >> (n_udword_bits - 1);
-        carry = s & 1;
-        r.all -= d.all & s;
-    }
-    q.all = (q.all << 1) | carry;
-    if (rem)
-        *rem = r.all;
-    return q.all;
-}
-#else
-
-/* More subroutines needed by GCC output code on some machines.  */
-/* Compile this one with gcc.  */
-/* Copyright (C) 1989-2014 Free Software Foundation, Inc.
-
-This file is part of GCC.
-
-GCC is free software; you can redistribute it and/or modify it under
-the terms of the GNU General Public License as published by the Free
-Software Foundation; either version 3, or (at your option) any later
-version.
-
-GCC is distributed in the hope that it will be useful, but WITHOUT ANY
-WARRANTY; without even the implied warranty of MERCHANTABILITY or
-FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
-for more details.
-
-Under Section 7 of GPL version 3, you are granted additional
-permissions described in the GCC Runtime Library Exception, version
-3.1, as published by the Free Software Foundation.
-
-You should have received a copy of the GNU General Public License and
-a copy of the GCC Runtime Library Exception along with this program;
-see the files COPYING3 and COPYING.RUNTIME respectively.  If not, see
-<http://www.gnu.org/licenses/>.  */
-
-/* This is extracted from gcc's libgcc/libgcc2.c with these typedefs added: */
-typedef short Wtype;
-typedef int DWtype;
-typedef unsigned int UWtype;
-typedef unsigned long long UDWtype;
-#if __BYTE_ORDER__ != __ORDER_LITTLE_ENDIAN__
-struct DWstruct {Wtype high, low;};
-#else
-struct DWstruct {Wtype low, high;};
-#endif
-typedef union {
-  struct DWstruct s;
-  DWtype ll;
-} DWunion;
-
-UDWtype
-__udivmoddi4 (UDWtype n, UDWtype d, UDWtype *rp)
-{
-  UDWtype q = 0, r = n, y = d;
-  UWtype lz1, lz2, i, k;
-
-  /* Implements align divisor shift dividend method. This algorithm
-     aligns the divisor under the dividend and then perform number of
-     test-subtract iterations which shift the dividend left. Number of
-     iterations is k + 1 where k is the number of bit positions the
-     divisor must be shifted left  to align it under the dividend.
-     quotient bits can be saved in the rightmost positions of the dividend
-     as it shifts left on each test-subtract iteration. */
-
-  if (y <= r)
-    {
-      lz1 = __builtin_clzll (d);
-      lz2 = __builtin_clzll (n);
-
-      k = lz1 - lz2;
-      y = (y << k);
-
-      /* Dividend can exceed 2 ^ (width − 1) − 1 but still be less than the
-         aligned divisor. Normal iteration can drops the high order bit
-         of the dividend. Therefore, first test-subtract iteration is a
-         special case, saving its quotient bit in a separate location and
-         not shifting the dividend. */
-      if (r >= y)
-        {
-          r = r - y;
-          q =  (1ULL << k);
-        }
-
-      if (k > 0)
-        {
-          y = y >> 1;
-
-          /* k additional iterations where k regular test subtract shift
-            dividend iterations are done.  */
-          i = k;
-          do
-            {
-              if (r >= y)
-                r = ((r - y) << 1) + 1;
-              else
-                r =  (r << 1);
-              i = i - 1;
-            } while (i != 0);
-
-          /* First quotient bit is combined with the quotient bits resulting
-             from the k regular iterations.  */
-          q = q + r;
-          r = r >> k;
-          q = q - (r << k);
-        }
-    }
-
-  if (rp)
-    *rp = r;
-  return q;
-}
-
-DWtype
-__moddi3 (DWtype u, DWtype v)
-{
-  Wtype c = 0;
-  DWunion uu = {.ll = u};
-  DWunion vv = {.ll = v};
-  DWtype w;
-
-  if (uu.s.high < 0)
-    c = ~c,
-    uu.ll = -uu.ll;
-  if (vv.s.high < 0)
-    vv.ll = -vv.ll;
-
-  (void) __udivmoddi4 (uu.ll, vv.ll, (UDWtype*)&w);
-  if (c)
-    w = -w;
-
-  return w;
-}
-
-#endif
diff --git a/litex/soc/cores/cpu/blackparrot/core.py b/litex/soc/cores/cpu/blackparrot/core.py
index 5a9738d05..6b15a964a 100644
--- a/litex/soc/cores/cpu/blackparrot/core.py
+++ b/litex/soc/cores/cpu/blackparrot/core.py
@@ -40,7 +40,7 @@ from litex.soc.cores.cpu import CPU
 CPU_VARIANTS = {
     "standard": "freechips.rocketchip.system.LitexConfig",
 }
-# -mcmodel=medany
+
 GCC_FLAGS = {
     "standard": "-march=rv64ia -mabi=lp64 -O0  ",
 }
@@ -104,7 +104,6 @@ class BlackParrotRV64(CPU):
             o_wbm_we_o = idbus.we,
             o_wbm_cti_o = idbus.cti,
             o_wbm_bte_o = idbus.bte,
-
             )
      
            # add verilog sources
@@ -120,7 +119,7 @@ class BlackParrotRV64(CPU):
     def add_sources(platform, variant="standard"):
         vdir = get_data_mod("cpu", "blackparrot").data_location
         bp_litex_dir = os.path.join(vdir,"bp_litex")
-        simulation = 0
+        simulation = 1
         if (simulation == 1):
             filename= os.path.join(bp_litex_dir,"flist.verilator")
         else:
@@ -137,7 +136,6 @@ class BlackParrotRV64(CPU):
                     a = os.popen('echo '+ str(dir_))
                     dir_start = a.read()
                     vdir = dir_start[:-1] + line[s2:-1]
-                    #print("INCDIR" + vdir)
                     platform.add_verilog_include_path(vdir)  #this line might be changed
                 elif (temp[0]=='$') :
                     s2 = line.find('/')
@@ -145,7 +143,6 @@ class BlackParrotRV64(CPU):
                     a = os.popen('echo '+ str(dir_))
                     dir_start = a.read()
                     vdir = dir_start[:-1]+ line[s2:-1]
-                    #print(vdir)
                     platform.add_source(vdir) #this line might be changed
                 elif (temp[0] == '/'):
                     assert("No support for absolute path for now")
diff --git a/litex/soc/cores/cpu/blackparrot/flist.fpga b/litex/soc/cores/cpu/blackparrot/flist.fpga
deleted file mode 100644
index 6ca19de8b..000000000
--- a/litex/soc/cores/cpu/blackparrot/flist.fpga
+++ /dev/null
@@ -1,250 +0,0 @@
-+incdir+$BASEJUMP_STL_DIR/bsg_dataflow
-+incdir+$BASEJUMP_STL_DIR/bsg_mem
-+incdir+$BASEJUMP_STL_DIR/bsg_misc
-+incdir+$BASEJUMP_STL_DIR/bsg_test
-+incdir+$BASEJUMP_STL_DIR/bsg_noc
-+incdir+$BP_COMMON_DIR/src/include
-+incdir+$BP_FE_DIR/src/include
-+incdir+$BP_BE_DIR/src/include
-+incdir+$BP_BE_DIR/src/include/bp_be_dcache
-+incdir+$BP_ME_DIR/src/include/v
-+incdir+$BP_TOP_DIR/src/include
-$BASEJUMP_STL_DIR/bsg_cache/bsg_cache_pkg.v
-$BASEJUMP_STL_DIR/bsg_noc/bsg_noc_pkg.v
-$BASEJUMP_STL_DIR/bsg_noc/bsg_wormhole_router_pkg.v
-$BP_COMMON_DIR/src/include/bp_common_rv64_pkg.vh
-$BP_COMMON_DIR/src/include/bp_common_pkg.vh
-$BP_COMMON_DIR/src/include/bp_common_aviary_pkg.vh
-$BP_COMMON_DIR/src/include/bp_common_cfg_link_pkg.vh
-$BP_FE_DIR/src/include/bp_fe_icache_pkg.vh
-$BP_FE_DIR/src/include/bp_fe_pkg.vh
-$BP_BE_DIR/src/include/bp_be_pkg.vh
-$BP_BE_DIR/src/include/bp_be_dcache/bp_be_dcache_pkg.vh
-$BP_ME_DIR/src/include/v/bp_cce_pkg.v
-$BP_ME_DIR/src/include/v/bp_me_pkg.vh
-$BASEJUMP_STL_DIR/bsg_async/bsg_async_fifo.v
-$BASEJUMP_STL_DIR/bsg_async/bsg_launch_sync_sync.v
-$BASEJUMP_STL_DIR/bsg_async/bsg_async_ptr_gray.v
-$BASEJUMP_STL_DIR/bsg_cache/bsg_cache.v
-$BASEJUMP_STL_DIR/bsg_cache/bsg_cache_dma.v
-$BASEJUMP_STL_DIR/bsg_cache/bsg_cache_miss.v
-$BASEJUMP_STL_DIR/bsg_cache/bsg_cache_decode.v
-$BASEJUMP_STL_DIR/bsg_cache/bsg_cache_sbuf.v
-$BASEJUMP_STL_DIR/bsg_cache/bsg_cache_sbuf_queue.v
-$BASEJUMP_STL_DIR/bsg_dataflow/bsg_channel_tunnel.v
-$BASEJUMP_STL_DIR/bsg_dataflow/bsg_channel_tunnel_in.v
-$BASEJUMP_STL_DIR/bsg_dataflow/bsg_channel_tunnel_out.v
-$BASEJUMP_STL_DIR/bsg_dataflow/bsg_1_to_n_tagged_fifo.v
-$BASEJUMP_STL_DIR/bsg_dataflow/bsg_1_to_n_tagged.v
-$BASEJUMP_STL_DIR/bsg_dataflow/bsg_fifo_1r1w_large.v
-$BASEJUMP_STL_DIR/bsg_dataflow/bsg_fifo_1r1w_pseudo_large.v
-$BASEJUMP_STL_DIR/bsg_dataflow/bsg_fifo_1r1w_small.v
-$BASEJUMP_STL_DIR/bsg_dataflow/bsg_fifo_1r1w_small_unhardened.v
-$BASEJUMP_STL_DIR/bsg_dataflow/bsg_fifo_1rw_large.v
-$BASEJUMP_STL_DIR/bsg_dataflow/bsg_fifo_tracker.v
-$BASEJUMP_STL_DIR/bsg_dataflow/bsg_flow_counter.v
-$BASEJUMP_STL_DIR/bsg_dataflow/bsg_one_fifo.v
-$BASEJUMP_STL_DIR/bsg_dataflow/bsg_parallel_in_serial_out.v
-$BASEJUMP_STL_DIR/bsg_dataflow/bsg_parallel_in_serial_out_dynamic.v
-$BASEJUMP_STL_DIR/bsg_dataflow/bsg_round_robin_1_to_n.v
-$BASEJUMP_STL_DIR/bsg_dataflow/bsg_round_robin_2_to_2.v
-$BASEJUMP_STL_DIR/bsg_dataflow/bsg_round_robin_n_to_1.v
-$BASEJUMP_STL_DIR/bsg_dataflow/bsg_serial_in_parallel_out.v
-$BASEJUMP_STL_DIR/bsg_dataflow/bsg_serial_in_parallel_out_dynamic.v
-$BASEJUMP_STL_DIR/bsg_dataflow/bsg_serial_in_parallel_out_full.v
-$BASEJUMP_STL_DIR/bsg_dataflow/bsg_shift_reg.v
-$BASEJUMP_STL_DIR/bsg_dataflow/bsg_two_fifo.v
-$BASEJUMP_STL_DIR/bsg_mem/bsg_cam_1r1w.v
-$BASEJUMP_STL_DIR/bsg_mem/bsg_mem_1r1w.v
-$BASEJUMP_STL_DIR/bsg_mem/bsg_mem_1r1w_sync.v
-$BASEJUMP_STL_DIR/bsg_mem/bsg_mem_1r1w_sync_synth.v
-$BASEJUMP_STL_DIR/bsg_mem/bsg_mem_1r1w_synth.v
-$BASEJUMP_STL_DIR/bsg_mem/bsg_mem_1rw_sync.v
-//$BASEJUMP_STL_DIR/bsg_mem/bsg_mem_1rw_sync_mask_write_bit.v
-$BP_FPGA_DIR/bsg_mem_1rw_sync_mask_write_bit.v
-$BASEJUMP_STL_DIR/bsg_mem/bsg_mem_1rw_sync_mask_write_bit_synth.v
-$BASEJUMP_STL_DIR/bsg_mem/bsg_mem_1rw_sync_mask_write_byte.v
-$BASEJUMP_STL_DIR/bsg_mem/bsg_mem_1rw_sync_mask_write_byte_synth.v
-$BASEJUMP_STL_DIR/bsg_mem/bsg_mem_1rw_sync_synth.v
-$BASEJUMP_STL_DIR/bsg_mem/bsg_mem_2r1w_sync.v
-$BASEJUMP_STL_DIR/bsg_mem/bsg_mem_2r1w_sync_synth.v
-$BASEJUMP_STL_DIR/bsg_misc/bsg_adder_ripple_carry.v
-$BASEJUMP_STL_DIR/bsg_misc/bsg_arb_fixed.v
-$BASEJUMP_STL_DIR/bsg_misc/bsg_array_concentrate_static.v
-$BASEJUMP_STL_DIR/bsg_misc/bsg_buf.v
-$BASEJUMP_STL_DIR/bsg_misc/bsg_circular_ptr.v
-$BASEJUMP_STL_DIR/bsg_misc/bsg_concentrate_static.v
-$BASEJUMP_STL_DIR/bsg_misc/bsg_counter_clear_up.v
-$BASEJUMP_STL_DIR/bsg_misc/bsg_counter_set_down.v
-$BASEJUMP_STL_DIR/bsg_misc/bsg_counter_set_en.v
-$BASEJUMP_STL_DIR/bsg_misc/bsg_counter_up_down.v
-$BASEJUMP_STL_DIR/bsg_misc/bsg_counter_up_down_variable.v
-$BASEJUMP_STL_DIR/bsg_misc/bsg_crossbar_o_by_i.v
-$BASEJUMP_STL_DIR/bsg_misc/bsg_cycle_counter.v
-$BASEJUMP_STL_DIR/bsg_misc/bsg_decode.v
-$BASEJUMP_STL_DIR/bsg_misc/bsg_decode_with_v.v
-$BASEJUMP_STL_DIR/bsg_misc/bsg_dff.v
-$BASEJUMP_STL_DIR/bsg_misc/bsg_dff_en_bypass.v
-$BASEJUMP_STL_DIR/bsg_misc/bsg_dff_reset_en_bypass.v
-$BASEJUMP_STL_DIR/bsg_misc/bsg_dff_chain.v
-$BASEJUMP_STL_DIR/bsg_misc/bsg_dff_en.v
-$BASEJUMP_STL_DIR/bsg_misc/bsg_dff_reset.v
-$BASEJUMP_STL_DIR/bsg_misc/bsg_dff_reset_en.v
-$BASEJUMP_STL_DIR/bsg_misc/bsg_edge_detect.v
-$BASEJUMP_STL_DIR/bsg_misc/bsg_encode_one_hot.v
-$BASEJUMP_STL_DIR/bsg_misc/bsg_expand_bitmask.v
-$BASEJUMP_STL_DIR/bsg_misc/bsg_hash_bank.v
-$BASEJUMP_STL_DIR/bsg_misc/bsg_hash_bank_reverse.v
-$BASEJUMP_STL_DIR/bsg_misc/bsg_lfsr.v
-$BASEJUMP_STL_DIR/bsg_misc/bsg_lru_pseudo_tree_decode.v
-$BASEJUMP_STL_DIR/bsg_misc/bsg_lru_pseudo_tree_encode.v
-$BASEJUMP_STL_DIR/bsg_misc/bsg_mux.v
-$BASEJUMP_STL_DIR/bsg_misc/bsg_mux_butterfly.v
-$BASEJUMP_STL_DIR/bsg_misc/bsg_mux_one_hot.v
-$BASEJUMP_STL_DIR/bsg_misc/bsg_mux_segmented.v
-$BASEJUMP_STL_DIR/bsg_misc/bsg_muxi2_gatestack.v
-$BASEJUMP_STL_DIR/bsg_misc/bsg_nor3.v
-$BASEJUMP_STL_DIR/bsg_misc/bsg_nand.v
-$BASEJUMP_STL_DIR/bsg_misc/bsg_priority_encode.v
-$BASEJUMP_STL_DIR/bsg_misc/bsg_priority_encode_one_hot_out.v
-$BASEJUMP_STL_DIR/bsg_misc/bsg_reduce.v
-$BASEJUMP_STL_DIR/bsg_misc/bsg_reduce_segmented.v
-$BASEJUMP_STL_DIR/bsg_misc/bsg_round_robin_arb.v
-$BASEJUMP_STL_DIR/bsg_misc/bsg_scan.v
-$BASEJUMP_STL_DIR/bsg_misc/bsg_strobe.v
-$BASEJUMP_STL_DIR/bsg_misc/bsg_swap.v
-$BASEJUMP_STL_DIR/bsg_misc/bsg_thermometer_count.v
-$BASEJUMP_STL_DIR/bsg_misc/bsg_transpose.v
-$BASEJUMP_STL_DIR/bsg_misc/bsg_unconcentrate_static.v
-$BASEJUMP_STL_DIR/bsg_misc/bsg_xnor.v
-$BASEJUMP_STL_DIR/bsg_noc/bsg_mesh_stitch.v
-$BASEJUMP_STL_DIR/bsg_noc/bsg_noc_repeater_node.v
-$BASEJUMP_STL_DIR/bsg_noc/bsg_wormhole_concentrator.v
-$BASEJUMP_STL_DIR/bsg_noc/bsg_wormhole_concentrator_in.v
-$BASEJUMP_STL_DIR/bsg_noc/bsg_wormhole_concentrator_out.v
-$BASEJUMP_STL_DIR/bsg_noc/bsg_wormhole_router.v
-$BASEJUMP_STL_DIR/bsg_noc/bsg_wormhole_router_adapter.v
-$BASEJUMP_STL_DIR/bsg_noc/bsg_wormhole_router_adapter_in.v
-$BASEJUMP_STL_DIR/bsg_noc/bsg_wormhole_router_adapter_out.v
-$BASEJUMP_STL_DIR/bsg_noc/bsg_wormhole_router_decoder_dor.v
-$BASEJUMP_STL_DIR/bsg_noc/bsg_wormhole_router_input_control.v  
-$BASEJUMP_STL_DIR/bsg_noc/bsg_wormhole_router_output_control.v 
-$BP_COMMON_DIR/src/v/bsg_fifo_1r1w_rolly.v
-$BP_COMMON_DIR/src/v/bp_pma.v
-$BP_COMMON_DIR/src/v/bp_tlb.v
-$BP_COMMON_DIR/src/v/bp_tlb_replacement.v
-$BP_BE_DIR/src/v/bp_be_top.v
-$BP_BE_DIR/src/v/bp_be_calculator/bp_be_bypass.v
-$BP_BE_DIR/src/v/bp_be_calculator/bp_be_calculator_top.v
-$BP_BE_DIR/src/v/bp_be_calculator/bp_be_instr_decoder.v
-$BP_BE_DIR/src/v/bp_be_calculator/bp_be_int_alu.v
-$BP_BE_DIR/src/v/bp_be_calculator/bp_be_pipe_fp.v
-$BP_BE_DIR/src/v/bp_be_calculator/bp_be_pipe_int.v
-$BP_BE_DIR/src/v/bp_be_calculator/bp_be_pipe_mem.v
-$BP_BE_DIR/src/v/bp_be_calculator/bp_be_pipe_mul.v
-$BP_BE_DIR/src/v/bp_be_calculator/bp_be_regfile.v
-$BP_BE_DIR/src/v/bp_be_checker/bp_be_checker_top.v
-$BP_BE_DIR/src/v/bp_be_checker/bp_be_detector.v
-$BP_BE_DIR/src/v/bp_be_checker/bp_be_director.v
-$BP_BE_DIR/src/v/bp_be_checker/bp_be_scheduler.v
-$BP_BE_DIR/src/v/bp_be_mem/bp_be_ptw.v
-$BP_BE_DIR/src/v/bp_be_mem/bp_be_csr.v
-$BP_BE_DIR/src/v/bp_be_mem/bp_be_dcache/bp_be_dcache.v
-$BP_BE_DIR/src/v/bp_be_mem/bp_be_dcache/bp_be_dcache_lce_cmd.v
-$BP_BE_DIR/src/v/bp_be_mem/bp_be_dcache/bp_be_dcache_lce.v
-$BP_BE_DIR/src/v/bp_be_mem/bp_be_dcache/bp_be_dcache_lce_req.v
-$BP_BE_DIR/src/v/bp_be_mem/bp_be_dcache/bp_be_dcache_wbuf.v
-$BP_BE_DIR/src/v/bp_be_mem/bp_be_dcache/bp_be_dcache_wbuf_queue.v
-$BP_BE_DIR/src/v/bp_be_mem/bp_be_mem_top.v
-$BP_FE_DIR/src/v/bp_fe_bht.v
-$BP_FE_DIR/src/v/bp_fe_btb.v
-$BP_FE_DIR/src/v/bp_fe_lce_cmd.v
-$BP_FE_DIR/src/v/bp_fe_icache.v
-$BP_FE_DIR/src/v/bp_fe_instr_scan.v
-$BP_FE_DIR/src/v/bp_fe_lce.v
-$BP_FE_DIR/src/v/bp_fe_lce_req.v
-$BP_FE_DIR/src/v/bp_fe_mem.v
-$BP_FE_DIR/src/v/bp_fe_pc_gen.v
-$BP_FE_DIR/src/v/bp_fe_top.v
-$BP_ME_DIR/src/v/cache/bp_me_cache_dma_to_cce.v
-$BP_ME_DIR/src/v/cache/bp_me_cache_slice.v
-$BP_ME_DIR/src/v/cache/bp_me_cce_to_cache.v
-$BP_ME_DIR/src/v/cache/bp_me_cce_to_cache_buffered.v
-$BP_ME_DIR/src/v/cce/bp_cce.v
-$BP_ME_DIR/src/v/cce/bp_cce_alu.v
-$BP_ME_DIR/src/v/cce/bp_cce_buffered.v
-$BP_ME_DIR/src/v/cce/bp_cce_dir.v
-$BP_ME_DIR/src/v/cce/bp_cce_dir_tag_checker.v
-$BP_ME_DIR/src/v/cce/bp_cce_dir_lru_extract.v
-$BP_ME_DIR/src/v/cce/bp_cce_gad.v
-$BP_ME_DIR/src/v/cce/bp_cce_inst_decode.v
-$BP_ME_DIR/src/v/cce/bp_cce_msg.v
-$BP_ME_DIR/src/v/cce/bp_cce_msg_cached.v
-$BP_ME_DIR/src/v/cce/bp_cce_msg_uncached.v
-$BP_ME_DIR/src/v/cce/bp_cce_pc.v
-$BP_ME_DIR/src/v/cce/bp_cce_pending.v
-$BP_ME_DIR/src/v/cce/bp_cce_reg.v
-$BP_ME_DIR/src/v/cce/bp_cce_spec.v
-$BP_ME_DIR/src/v/cce/bp_io_cce.v
-$BP_ME_DIR/src/v/cce/bp_uce.v
-$BP_ME_DIR/src/v/wormhole/bp_me_addr_to_cce_id.v
-$BP_ME_DIR/src/v/wormhole/bp_me_cce_id_to_cord.v
-$BP_ME_DIR/src/v/wormhole/bp_me_cce_to_mem_link_bidir.v
-$BP_ME_DIR/src/v/wormhole/bp_me_cce_to_mem_link_client.v
-$BP_ME_DIR/src/v/wormhole/bp_me_cce_to_mem_link_master.v
-$BP_ME_DIR/src/v/wormhole/bp_me_cord_to_id.v
-$BP_ME_DIR/src/v/wormhole/bp_me_lce_id_to_cord.v
-$BP_ME_DIR/src/v/wormhole/bp_me_wormhole_packet_encode_lce_cmd.v
-$BP_ME_DIR/src/v/wormhole/bp_me_wormhole_packet_encode_lce_req.v
-$BP_ME_DIR/src/v/wormhole/bp_me_wormhole_packet_encode_lce_resp.v
-$BP_ME_DIR/src/v/wormhole/bp_me_wormhole_packet_encode_mem_cmd.v
-$BP_ME_DIR/src/v/wormhole/bp_me_wormhole_packet_encode_mem_resp.v
-//$BP_TOP_DIR/src/v/bp_accelerator_complex.v
-$BP_TOP_DIR/src/v/bp_cfg.v
-$BP_TOP_DIR/src/v/bp_cfg_buffered.v
-$BP_TOP_DIR/src/v/bp_core.v
-//$BP_TOP_DIR/src/v/bp_core_complex.v
-$BP_TOP_DIR/src/v/bp_core_minimal.v
-//$BP_TOP_DIR/src/v/bp_clint.v
-$BP_TOP_DIR/src/v/bp_clint_node.v
-$BP_TOP_DIR/src/v/bp_clint_slice.v
-$BP_TOP_DIR/src/v/bp_clint_slice_buffered.v
-//$BP_TOP_DIR/src/v/bp_l2e_tile.v
-//$BP_TOP_DIR/src/v/bp_l2e_tile_node.v
-$BP_TOP_DIR/src/v/bp_io_complex.v
-$BP_TOP_DIR/src/v/bp_io_link_to_lce.v
-$BP_TOP_DIR/src/v/bp_io_tile.v
-$BP_TOP_DIR/src/v/bp_io_tile_node.v
-$BP_TOP_DIR/src/v/bp_mem_complex.v
-//$BP_TOP_DIR/src/v/bp_processor.v
-$BP_TOP_DIR/src/v/bp_softcore.v
-//$BP_TOP_DIR/src/v/bp_tile.v
-//$BP_TOP_DIR/src/v/bp_tile_node.v
-$BP_TOP_DIR/src/v/bsg_async_noc_link.v
-//$BASEJUMP_STL_DIR/bsg_test/bsg_nonsynth_reset_gen.v
-//$BASEJUMP_STL_DIR/bsg_test/bsg_nonsynth_clock_gen.v
-//$BASEJUMP_STL_DIR/bsg_fsb/bsg_fsb_node_trace_replay.v
-//$BP_BE_DIR/test/common/bp_be_nonsynth_calc_tracer.v
-//$BP_BE_DIR/test/common/bp_be_nonsynth_dcache_tracer.v
-//$BP_BE_DIR/test/common/bp_be_nonsynth_perf.v
-//$BP_BE_DIR/test/common/bp_be_nonsynth_npc_tracer.v
-//$BP_BE_DIR/test/common/bp_be_nonsynth_vm_tracer.v
-//$BP_ME_DIR/test/common/bp_mem.v
-//$BP_ME_DIR/test/common/bp_mem_transducer.v
-//$BP_ME_DIR/test/common/bp_mem_delay_model.v
-//$BP_ME_DIR/test/common/bp_mem_storage_sync.v
-//$BP_ME_DIR/test/common/bp_cce_mmio_cfg_loader.v
-//$BP_ME_DIR/test/common/dramsim2_wrapper.cpp
-//$BP_ME_DIR/test/common/bp_mem_utils.cpp
-//$BP_ME_DIR/test/common/bp_cce_nonsynth_tracer.v
-$BP_ME_DIR/test/common/bp_mem_nonsynth_tracer.v
-//$BP_TOP_DIR/test/common/bp_nonsynth_cosim.v
-//$BP_TOP_DIR/test/common/bp_nonsynth_host.v
-//$BP_TOP_DIR/test/common/bp_nonsynth_if_verif.v
-$BP_TOP_DIR/test/common/bp_nonsynth_commit_tracer.v
-//$BP_TOP_DIR/test/common/bp_nonsynth_nbf_loader.v
-//$BP_TOP_DIR/test/common/bp_monitor.cpp
-//$BP_TOP_DIR/test/common/dromajo_cosim.cpp
-//$BP_FPGA_DIR/wrapper.v
-$BP_FPGA_DIR/bp2wb_convertor.v
-$BP_FPGA_DIR/fpga/ExampleBlackParrotSystem.v
diff --git a/litex/soc/cores/cpu/blackparrot/flist.verilator b/litex/soc/cores/cpu/blackparrot/flist.verilator
deleted file mode 100644
index 551f5ea5d..000000000
--- a/litex/soc/cores/cpu/blackparrot/flist.verilator
+++ /dev/null
@@ -1,250 +0,0 @@
-+incdir+$BASEJUMP_STL_DIR/bsg_dataflow
-+incdir+$BASEJUMP_STL_DIR/bsg_mem
-+incdir+$BASEJUMP_STL_DIR/bsg_misc
-+incdir+$BASEJUMP_STL_DIR/bsg_test
-+incdir+$BASEJUMP_STL_DIR/bsg_noc
-+incdir+$BP_COMMON_DIR/src/include
-+incdir+$BP_FE_DIR/src/include
-+incdir+$BP_BE_DIR/src/include
-+incdir+$BP_BE_DIR/src/include/bp_be_dcache
-+incdir+$BP_ME_DIR/src/include/v
-+incdir+$BP_TOP_DIR/src/include
-$BASEJUMP_STL_DIR/bsg_cache/bsg_cache_pkg.v
-$BASEJUMP_STL_DIR/bsg_noc/bsg_noc_pkg.v
-$BASEJUMP_STL_DIR/bsg_noc/bsg_wormhole_router_pkg.v
-$BP_COMMON_DIR/src/include/bp_common_rv64_pkg.vh
-$BP_COMMON_DIR/src/include/bp_common_pkg.vh
-$BP_COMMON_DIR/src/include/bp_common_aviary_pkg.vh
-$BP_COMMON_DIR/src/include/bp_common_cfg_link_pkg.vh
-$BP_FE_DIR/src/include/bp_fe_icache_pkg.vh
-$BP_FE_DIR/src/include/bp_fe_pkg.vh
-$BP_BE_DIR/src/include/bp_be_pkg.vh
-$BP_BE_DIR/src/include/bp_be_dcache/bp_be_dcache_pkg.vh
-$BP_ME_DIR/src/include/v/bp_cce_pkg.v
-$BP_ME_DIR/src/include/v/bp_me_pkg.vh
-$BASEJUMP_STL_DIR/bsg_async/bsg_async_fifo.v
-$BASEJUMP_STL_DIR/bsg_async/bsg_launch_sync_sync.v
-$BASEJUMP_STL_DIR/bsg_async/bsg_async_ptr_gray.v
-$BASEJUMP_STL_DIR/bsg_cache/bsg_cache.v
-$BASEJUMP_STL_DIR/bsg_cache/bsg_cache_dma.v
-$BASEJUMP_STL_DIR/bsg_cache/bsg_cache_miss.v
-$BASEJUMP_STL_DIR/bsg_cache/bsg_cache_decode.v
-$BASEJUMP_STL_DIR/bsg_cache/bsg_cache_sbuf.v
-$BASEJUMP_STL_DIR/bsg_cache/bsg_cache_sbuf_queue.v
-$BASEJUMP_STL_DIR/bsg_dataflow/bsg_channel_tunnel.v
-$BASEJUMP_STL_DIR/bsg_dataflow/bsg_channel_tunnel_in.v
-$BASEJUMP_STL_DIR/bsg_dataflow/bsg_channel_tunnel_out.v
-$BASEJUMP_STL_DIR/bsg_dataflow/bsg_1_to_n_tagged_fifo.v
-$BASEJUMP_STL_DIR/bsg_dataflow/bsg_1_to_n_tagged.v
-$BASEJUMP_STL_DIR/bsg_dataflow/bsg_fifo_1r1w_large.v
-$BASEJUMP_STL_DIR/bsg_dataflow/bsg_fifo_1r1w_pseudo_large.v
-$BASEJUMP_STL_DIR/bsg_dataflow/bsg_fifo_1r1w_small.v
-$BASEJUMP_STL_DIR/bsg_dataflow/bsg_fifo_1r1w_small_unhardened.v
-$BASEJUMP_STL_DIR/bsg_dataflow/bsg_fifo_1rw_large.v
-$BASEJUMP_STL_DIR/bsg_dataflow/bsg_fifo_tracker.v
-$BASEJUMP_STL_DIR/bsg_dataflow/bsg_flow_counter.v
-$BASEJUMP_STL_DIR/bsg_dataflow/bsg_one_fifo.v
-$BASEJUMP_STL_DIR/bsg_dataflow/bsg_parallel_in_serial_out.v
-$BASEJUMP_STL_DIR/bsg_dataflow/bsg_parallel_in_serial_out_dynamic.v
-$BASEJUMP_STL_DIR/bsg_dataflow/bsg_round_robin_1_to_n.v
-$BASEJUMP_STL_DIR/bsg_dataflow/bsg_round_robin_2_to_2.v
-$BASEJUMP_STL_DIR/bsg_dataflow/bsg_round_robin_n_to_1.v
-$BASEJUMP_STL_DIR/bsg_dataflow/bsg_serial_in_parallel_out.v
-$BASEJUMP_STL_DIR/bsg_dataflow/bsg_serial_in_parallel_out_dynamic.v
-$BASEJUMP_STL_DIR/bsg_dataflow/bsg_serial_in_parallel_out_full.v
-$BASEJUMP_STL_DIR/bsg_dataflow/bsg_shift_reg.v
-$BASEJUMP_STL_DIR/bsg_dataflow/bsg_two_fifo.v
-$BASEJUMP_STL_DIR/bsg_mem/bsg_cam_1r1w.v
-$BASEJUMP_STL_DIR/bsg_mem/bsg_mem_1r1w.v
-$BASEJUMP_STL_DIR/bsg_mem/bsg_mem_1r1w_sync.v
-$BASEJUMP_STL_DIR/bsg_mem/bsg_mem_1r1w_sync_synth.v
-$BASEJUMP_STL_DIR/bsg_mem/bsg_mem_1r1w_synth.v
-$BASEJUMP_STL_DIR/bsg_mem/bsg_mem_1rw_sync.v
-//$BASEJUMP_STL_DIR/bsg_mem/bsg_mem_1rw_sync_mask_write_bit.v
-$BP_FPGA_DIR/bsg_mem_1rw_sync_mask_write_bit.v
-$BASEJUMP_STL_DIR/bsg_mem/bsg_mem_1rw_sync_mask_write_bit_synth.v
-$BASEJUMP_STL_DIR/bsg_mem/bsg_mem_1rw_sync_mask_write_byte.v
-$BASEJUMP_STL_DIR/bsg_mem/bsg_mem_1rw_sync_mask_write_byte_synth.v
-$BASEJUMP_STL_DIR/bsg_mem/bsg_mem_1rw_sync_synth.v
-$BASEJUMP_STL_DIR/bsg_mem/bsg_mem_2r1w_sync.v
-$BASEJUMP_STL_DIR/bsg_mem/bsg_mem_2r1w_sync_synth.v
-$BASEJUMP_STL_DIR/bsg_misc/bsg_adder_ripple_carry.v
-$BASEJUMP_STL_DIR/bsg_misc/bsg_arb_fixed.v
-$BASEJUMP_STL_DIR/bsg_misc/bsg_array_concentrate_static.v
-$BASEJUMP_STL_DIR/bsg_misc/bsg_buf.v
-$BASEJUMP_STL_DIR/bsg_misc/bsg_circular_ptr.v
-$BASEJUMP_STL_DIR/bsg_misc/bsg_concentrate_static.v
-$BASEJUMP_STL_DIR/bsg_misc/bsg_counter_clear_up.v
-$BASEJUMP_STL_DIR/bsg_misc/bsg_counter_set_down.v
-$BASEJUMP_STL_DIR/bsg_misc/bsg_counter_set_en.v
-$BASEJUMP_STL_DIR/bsg_misc/bsg_counter_up_down.v
-$BASEJUMP_STL_DIR/bsg_misc/bsg_counter_up_down_variable.v
-$BASEJUMP_STL_DIR/bsg_misc/bsg_crossbar_o_by_i.v
-$BASEJUMP_STL_DIR/bsg_misc/bsg_cycle_counter.v
-$BASEJUMP_STL_DIR/bsg_misc/bsg_decode.v
-$BASEJUMP_STL_DIR/bsg_misc/bsg_decode_with_v.v
-$BASEJUMP_STL_DIR/bsg_misc/bsg_dff.v
-$BASEJUMP_STL_DIR/bsg_misc/bsg_dff_en_bypass.v
-$BASEJUMP_STL_DIR/bsg_misc/bsg_dff_reset_en_bypass.v
-$BASEJUMP_STL_DIR/bsg_misc/bsg_dff_chain.v
-$BASEJUMP_STL_DIR/bsg_misc/bsg_dff_en.v
-$BASEJUMP_STL_DIR/bsg_misc/bsg_dff_reset.v
-$BASEJUMP_STL_DIR/bsg_misc/bsg_dff_reset_en.v
-$BASEJUMP_STL_DIR/bsg_misc/bsg_edge_detect.v
-$BASEJUMP_STL_DIR/bsg_misc/bsg_encode_one_hot.v
-$BASEJUMP_STL_DIR/bsg_misc/bsg_expand_bitmask.v
-$BASEJUMP_STL_DIR/bsg_misc/bsg_hash_bank.v
-$BASEJUMP_STL_DIR/bsg_misc/bsg_hash_bank_reverse.v
-$BASEJUMP_STL_DIR/bsg_misc/bsg_lfsr.v
-$BASEJUMP_STL_DIR/bsg_misc/bsg_lru_pseudo_tree_decode.v
-$BASEJUMP_STL_DIR/bsg_misc/bsg_lru_pseudo_tree_encode.v
-$BASEJUMP_STL_DIR/bsg_misc/bsg_mux.v
-$BASEJUMP_STL_DIR/bsg_misc/bsg_mux_butterfly.v
-$BASEJUMP_STL_DIR/bsg_misc/bsg_mux_one_hot.v
-$BASEJUMP_STL_DIR/bsg_misc/bsg_mux_segmented.v
-$BASEJUMP_STL_DIR/bsg_misc/bsg_muxi2_gatestack.v
-$BASEJUMP_STL_DIR/bsg_misc/bsg_nor3.v
-$BASEJUMP_STL_DIR/bsg_misc/bsg_nand.v
-$BASEJUMP_STL_DIR/bsg_misc/bsg_priority_encode.v
-$BASEJUMP_STL_DIR/bsg_misc/bsg_priority_encode_one_hot_out.v
-$BASEJUMP_STL_DIR/bsg_misc/bsg_reduce.v
-$BASEJUMP_STL_DIR/bsg_misc/bsg_reduce_segmented.v
-$BASEJUMP_STL_DIR/bsg_misc/bsg_round_robin_arb.v
-$BASEJUMP_STL_DIR/bsg_misc/bsg_scan.v
-$BASEJUMP_STL_DIR/bsg_misc/bsg_strobe.v
-$BASEJUMP_STL_DIR/bsg_misc/bsg_swap.v
-$BASEJUMP_STL_DIR/bsg_misc/bsg_thermometer_count.v
-$BASEJUMP_STL_DIR/bsg_misc/bsg_transpose.v
-$BASEJUMP_STL_DIR/bsg_misc/bsg_unconcentrate_static.v
-$BASEJUMP_STL_DIR/bsg_misc/bsg_xnor.v
-$BASEJUMP_STL_DIR/bsg_noc/bsg_mesh_stitch.v
-$BASEJUMP_STL_DIR/bsg_noc/bsg_noc_repeater_node.v
-$BASEJUMP_STL_DIR/bsg_noc/bsg_wormhole_concentrator.v
-$BASEJUMP_STL_DIR/bsg_noc/bsg_wormhole_concentrator_in.v
-$BASEJUMP_STL_DIR/bsg_noc/bsg_wormhole_concentrator_out.v
-$BASEJUMP_STL_DIR/bsg_noc/bsg_wormhole_router.v
-$BASEJUMP_STL_DIR/bsg_noc/bsg_wormhole_router_adapter.v
-$BASEJUMP_STL_DIR/bsg_noc/bsg_wormhole_router_adapter_in.v
-$BASEJUMP_STL_DIR/bsg_noc/bsg_wormhole_router_adapter_out.v
-$BASEJUMP_STL_DIR/bsg_noc/bsg_wormhole_router_decoder_dor.v
-$BASEJUMP_STL_DIR/bsg_noc/bsg_wormhole_router_input_control.v  
-$BASEJUMP_STL_DIR/bsg_noc/bsg_wormhole_router_output_control.v 
-$BP_COMMON_DIR/src/v/bsg_fifo_1r1w_rolly.v
-$BP_COMMON_DIR/src/v/bp_pma.v
-$BP_COMMON_DIR/src/v/bp_tlb.v
-$BP_COMMON_DIR/src/v/bp_tlb_replacement.v
-$BP_BE_DIR/src/v/bp_be_top.v
-$BP_BE_DIR/src/v/bp_be_calculator/bp_be_bypass.v
-$BP_BE_DIR/src/v/bp_be_calculator/bp_be_calculator_top.v
-$BP_BE_DIR/src/v/bp_be_calculator/bp_be_instr_decoder.v
-$BP_BE_DIR/src/v/bp_be_calculator/bp_be_int_alu.v
-$BP_BE_DIR/src/v/bp_be_calculator/bp_be_pipe_fp.v
-$BP_BE_DIR/src/v/bp_be_calculator/bp_be_pipe_int.v
-$BP_BE_DIR/src/v/bp_be_calculator/bp_be_pipe_mem.v
-$BP_BE_DIR/src/v/bp_be_calculator/bp_be_pipe_mul.v
-$BP_BE_DIR/src/v/bp_be_calculator/bp_be_regfile.v
-$BP_BE_DIR/src/v/bp_be_checker/bp_be_checker_top.v
-$BP_BE_DIR/src/v/bp_be_checker/bp_be_detector.v
-$BP_BE_DIR/src/v/bp_be_checker/bp_be_director.v
-$BP_BE_DIR/src/v/bp_be_checker/bp_be_scheduler.v
-$BP_BE_DIR/src/v/bp_be_mem/bp_be_ptw.v
-$BP_BE_DIR/src/v/bp_be_mem/bp_be_csr.v
-$BP_BE_DIR/src/v/bp_be_mem/bp_be_dcache/bp_be_dcache.v
-$BP_BE_DIR/src/v/bp_be_mem/bp_be_dcache/bp_be_dcache_lce_cmd.v
-$BP_BE_DIR/src/v/bp_be_mem/bp_be_dcache/bp_be_dcache_lce.v
-$BP_BE_DIR/src/v/bp_be_mem/bp_be_dcache/bp_be_dcache_lce_req.v
-$BP_BE_DIR/src/v/bp_be_mem/bp_be_dcache/bp_be_dcache_wbuf.v
-$BP_BE_DIR/src/v/bp_be_mem/bp_be_dcache/bp_be_dcache_wbuf_queue.v
-$BP_BE_DIR/src/v/bp_be_mem/bp_be_mem_top.v
-$BP_FE_DIR/src/v/bp_fe_bht.v
-$BP_FE_DIR/src/v/bp_fe_btb.v
-$BP_FE_DIR/src/v/bp_fe_lce_cmd.v
-$BP_FE_DIR/src/v/bp_fe_icache.v
-$BP_FE_DIR/src/v/bp_fe_instr_scan.v
-$BP_FE_DIR/src/v/bp_fe_lce.v
-$BP_FE_DIR/src/v/bp_fe_lce_req.v
-$BP_FE_DIR/src/v/bp_fe_mem.v
-$BP_FE_DIR/src/v/bp_fe_pc_gen.v
-$BP_FE_DIR/src/v/bp_fe_top.v
-$BP_ME_DIR/src/v/cache/bp_me_cache_dma_to_cce.v
-$BP_ME_DIR/src/v/cache/bp_me_cache_slice.v
-$BP_ME_DIR/src/v/cache/bp_me_cce_to_cache.v
-$BP_ME_DIR/src/v/cache/bp_me_cce_to_cache_buffered.v
-$BP_ME_DIR/src/v/cce/bp_cce.v
-$BP_ME_DIR/src/v/cce/bp_cce_alu.v
-$BP_ME_DIR/src/v/cce/bp_cce_buffered.v
-$BP_ME_DIR/src/v/cce/bp_cce_dir.v
-$BP_ME_DIR/src/v/cce/bp_cce_dir_tag_checker.v
-$BP_ME_DIR/src/v/cce/bp_cce_dir_lru_extract.v
-$BP_ME_DIR/src/v/cce/bp_cce_gad.v
-$BP_ME_DIR/src/v/cce/bp_cce_inst_decode.v
-$BP_ME_DIR/src/v/cce/bp_cce_msg.v
-$BP_ME_DIR/src/v/cce/bp_cce_msg_cached.v
-$BP_ME_DIR/src/v/cce/bp_cce_msg_uncached.v
-$BP_ME_DIR/src/v/cce/bp_cce_pc.v
-$BP_ME_DIR/src/v/cce/bp_cce_pending.v
-$BP_ME_DIR/src/v/cce/bp_cce_reg.v
-$BP_ME_DIR/src/v/cce/bp_cce_spec.v
-$BP_ME_DIR/src/v/cce/bp_io_cce.v
-$BP_ME_DIR/src/v/cce/bp_uce.v
-$BP_ME_DIR/src/v/wormhole/bp_me_addr_to_cce_id.v
-$BP_ME_DIR/src/v/wormhole/bp_me_cce_id_to_cord.v
-$BP_ME_DIR/src/v/wormhole/bp_me_cce_to_mem_link_bidir.v
-$BP_ME_DIR/src/v/wormhole/bp_me_cce_to_mem_link_client.v
-$BP_ME_DIR/src/v/wormhole/bp_me_cce_to_mem_link_master.v
-$BP_ME_DIR/src/v/wormhole/bp_me_cord_to_id.v
-$BP_ME_DIR/src/v/wormhole/bp_me_lce_id_to_cord.v
-$BP_ME_DIR/src/v/wormhole/bp_me_wormhole_packet_encode_lce_cmd.v
-$BP_ME_DIR/src/v/wormhole/bp_me_wormhole_packet_encode_lce_req.v
-$BP_ME_DIR/src/v/wormhole/bp_me_wormhole_packet_encode_lce_resp.v
-$BP_ME_DIR/src/v/wormhole/bp_me_wormhole_packet_encode_mem_cmd.v
-$BP_ME_DIR/src/v/wormhole/bp_me_wormhole_packet_encode_mem_resp.v
-//$BP_TOP_DIR/src/v/bp_accelerator_complex.v
-$BP_TOP_DIR/src/v/bp_cfg.v
-$BP_TOP_DIR/src/v/bp_cfg_buffered.v
-$BP_TOP_DIR/src/v/bp_core.v
-//$BP_TOP_DIR/src/v/bp_core_complex.v
-$BP_TOP_DIR/src/v/bp_core_minimal.v
-//$BP_TOP_DIR/src/v/bp_clint.v
-$BP_TOP_DIR/src/v/bp_clint_node.v
-$BP_TOP_DIR/src/v/bp_clint_slice.v
-$BP_TOP_DIR/src/v/bp_clint_slice_buffered.v
-//$BP_TOP_DIR/src/v/bp_l2e_tile.v
-//$BP_TOP_DIR/src/v/bp_l2e_tile_node.v
-$BP_TOP_DIR/src/v/bp_io_complex.v
-$BP_TOP_DIR/src/v/bp_io_link_to_lce.v
-$BP_TOP_DIR/src/v/bp_io_tile.v
-$BP_TOP_DIR/src/v/bp_io_tile_node.v
-$BP_TOP_DIR/src/v/bp_mem_complex.v
-//$BP_TOP_DIR/src/v/bp_processor.v
-$BP_TOP_DIR/src/v/bp_softcore.v
-//$BP_TOP_DIR/src/v/bp_tile.v
-//$BP_TOP_DIR/src/v/bp_tile_node.v
-$BP_TOP_DIR/src/v/bsg_async_noc_link.v
-//$BASEJUMP_STL_DIR/bsg_test/bsg_nonsynth_reset_gen.v
-//$BASEJUMP_STL_DIR/bsg_test/bsg_nonsynth_clock_gen.v
-//$BASEJUMP_STL_DIR/bsg_fsb/bsg_fsb_node_trace_replay.v
-//$BP_BE_DIR/test/common/bp_be_nonsynth_calc_tracer.v
-//$BP_BE_DIR/test/common/bp_be_nonsynth_dcache_tracer.v
-//$BP_BE_DIR/test/common/bp_be_nonsynth_perf.v
-//$BP_BE_DIR/test/common/bp_be_nonsynth_npc_tracer.v
-//$BP_BE_DIR/test/common/bp_be_nonsynth_vm_tracer.v
-//$BP_ME_DIR/test/common/bp_mem.v
-//$BP_ME_DIR/test/common/bp_mem_transducer.v
-//$BP_ME_DIR/test/common/bp_mem_delay_model.v
-//$BP_ME_DIR/test/common/bp_mem_storage_sync.v
-//$BP_ME_DIR/test/common/bp_cce_mmio_cfg_loader.v
-//$BP_ME_DIR/test/common/dramsim2_wrapper.cpp
-//$BP_ME_DIR/test/common/bp_mem_utils.cpp
-//$BP_ME_DIR/test/common/bp_cce_nonsynth_tracer.v
-$BP_ME_DIR/test/common/bp_mem_nonsynth_tracer.v
-//$BP_TOP_DIR/test/common/bp_nonsynth_cosim.v
-//$BP_TOP_DIR/test/common/bp_nonsynth_host.v
-//$BP_TOP_DIR/test/common/bp_nonsynth_if_verif.v
-$BP_TOP_DIR/test/common/bp_nonsynth_commit_tracer.v
-//$BP_TOP_DIR/test/common/bp_nonsynth_nbf_loader.v
-//$BP_TOP_DIR/test/common/bp_monitor.cpp
-//$BP_TOP_DIR/test/common/dromajo_cosim.cpp
-//$BP_FPGA_DIR/wrapper.v
-$BP_FPGA_DIR/bp2wb_convertor.v
-$BP_FPGA_DIR/simulation/ExampleBlackParrotSystem.v
diff --git a/litex/soc/cores/cpu/blackparrot/flist_litex.verilator b/litex/soc/cores/cpu/blackparrot/flist_litex.verilator
deleted file mode 100644
index ba656dc14..000000000
--- a/litex/soc/cores/cpu/blackparrot/flist_litex.verilator
+++ /dev/null
@@ -1,229 +0,0 @@
-//// Includes
-// bsg_ip_cores includes
-+incdir+$BASEJUMP_STL_DIR/bsg_dataflow
-+incdir+$BASEJUMP_STL_DIR/bsg_mem
-+incdir+$BASEJUMP_STL_DIR/bsg_misc
-+incdir+$BASEJUMP_STL_DIR/bsg_test
-+incdir+$BASEJUMP_STL_DIR/bsg_noc
-// common includes
-+incdir+$BP_COMMON_DIR/src/include
-// fe includes
-+incdir+$BP_FE_DIR/src/include
-// be includes
-+incdir+$BP_BE_DIR/src/include
-+incdir+$BP_BE_DIR/src/include/bp_be_dcache
-// me includes 
-+incdir+$BP_ME_DIR/src/include/v
-// top includes
-+incdir+$BP_TOP_DIR/src/include
-//// Packages
-// bsg_ip_cores packages
-$BASEJUMP_STL_DIR/bsg_noc/bsg_noc_pkg.v
-$BASEJUMP_STL_DIR/bsg_noc/bsg_wormhole_router_pkg.v
-// Interface packages
-$BP_COMMON_DIR/src/include/bp_common_rv64_pkg.vh
-$BP_COMMON_DIR/src/include/bp_common_pkg.vh
-$BP_COMMON_DIR/src/include/bp_common_aviary_pkg.vh
-// FE packages
-$BP_FE_DIR/src/include/bp_fe_icache_pkg.vh
-$BP_FE_DIR/src/include/bp_fe_pkg.vh
-// BE packages
-$BP_BE_DIR/src/include/bp_be_pkg.vh
-$BP_BE_DIR/src/include/bp_be_dcache/bp_be_dcache_pkg.vh
-// ME packages
-$BP_ME_DIR/src/include/v/bp_cce_pkg.v
-$BP_ME_DIR/src/include/v/bp_me_pkg.vh
-// Top packages
-$BP_TOP_DIR/src/include/bp_cfg_link_pkg.vh
-//// bsg_ip_cores files
-$BASEJUMP_STL_DIR/bsg_async/bsg_async_fifo.v
-$BASEJUMP_STL_DIR/bsg_async/bsg_launch_sync_sync.v
-$BASEJUMP_STL_DIR/bsg_async/bsg_async_ptr_gray.v
-$BASEJUMP_STL_DIR/bsg_dataflow/bsg_channel_tunnel.v
-$BASEJUMP_STL_DIR/bsg_dataflow/bsg_channel_tunnel_in.v
-$BASEJUMP_STL_DIR/bsg_dataflow/bsg_channel_tunnel_out.v
-$BASEJUMP_STL_DIR/bsg_dataflow/bsg_1_to_n_tagged_fifo.v
-$BASEJUMP_STL_DIR/bsg_dataflow/bsg_1_to_n_tagged.v
-$BASEJUMP_STL_DIR/bsg_dataflow/bsg_fifo_1r1w_large.v
-$BASEJUMP_STL_DIR/bsg_dataflow/bsg_fifo_1rw_large.v
-$BASEJUMP_STL_DIR/bsg_dataflow/bsg_serial_in_parallel_out.v
-$BASEJUMP_STL_DIR/bsg_dataflow/bsg_one_fifo.v
-$BASEJUMP_STL_DIR/bsg_dataflow/bsg_round_robin_2_to_2.v
-$BASEJUMP_STL_DIR/bsg_dataflow/bsg_fifo_1r1w_pseudo_large.v
-$BASEJUMP_STL_DIR/bsg_dataflow/bsg_fifo_1r1w_small.v
-$BASEJUMP_STL_DIR/bsg_dataflow/bsg_fifo_tracker.v
-$BASEJUMP_STL_DIR/bsg_dataflow/bsg_flow_counter.v
-$BASEJUMP_STL_DIR/bsg_dataflow/bsg_parallel_in_serial_out_dynamic.v
-$BASEJUMP_STL_DIR/bsg_dataflow/bsg_round_robin_n_to_1.v
-$BASEJUMP_STL_DIR/bsg_dataflow/bsg_serial_in_parallel_out_dynamic.v
-$BASEJUMP_STL_DIR/bsg_dataflow/bsg_shift_reg.v
-$BASEJUMP_STL_DIR/bsg_dataflow/bsg_two_fifo.v
-$BASEJUMP_STL_DIR/bsg_mem/bsg_cam_1r1w.v
-$BASEJUMP_STL_DIR/bsg_mem/bsg_mem_1r1w.v
-$BASEJUMP_STL_DIR/bsg_mem/bsg_mem_1r1w_sync.v
-$BASEJUMP_STL_DIR/bsg_mem/bsg_mem_1r1w_sync_synth.v
-$BASEJUMP_STL_DIR/bsg_mem/bsg_mem_1r1w_synth.v
-$BASEJUMP_STL_DIR/bsg_mem/bsg_mem_1rw_sync.v
-// $BASEJUMP_STL_DIR/bsg_mem/bsg_mem_1rw_sync_mask_write_bit.v
-$BASEJUMP_STL_DIR/bsg_mem/bsg_mem_1rw_sync_mask_write_bit_synth.v
-$BASEJUMP_STL_DIR/bsg_mem/bsg_mem_1rw_sync_mask_write_byte.v
-$BASEJUMP_STL_DIR/bsg_mem/bsg_mem_1rw_sync_mask_write_byte_synth.v
-$BASEJUMP_STL_DIR/bsg_mem/bsg_mem_1rw_sync_synth.v
-$BASEJUMP_STL_DIR/bsg_mem/bsg_mem_2r1w_sync.v
-$BASEJUMP_STL_DIR/bsg_mem/bsg_mem_2r1w_sync_synth.v
-$BASEJUMP_STL_DIR/bsg_misc/bsg_adder_ripple_carry.v
-$BASEJUMP_STL_DIR/bsg_misc/bsg_arb_fixed.v
-$BASEJUMP_STL_DIR/bsg_misc/bsg_array_concentrate_static.v
-$BASEJUMP_STL_DIR/bsg_misc/bsg_circular_ptr.v
-$BASEJUMP_STL_DIR/bsg_misc/bsg_concentrate_static.v
-$BASEJUMP_STL_DIR/bsg_misc/bsg_counter_clear_up.v
-$BASEJUMP_STL_DIR/bsg_misc/bsg_counter_set_down.v
-$BASEJUMP_STL_DIR/bsg_misc/bsg_counter_up_down.v
-$BASEJUMP_STL_DIR/bsg_misc/bsg_counter_up_down_variable.v
-$BASEJUMP_STL_DIR/bsg_misc/bsg_crossbar_o_by_i.v
-$BASEJUMP_STL_DIR/bsg_misc/bsg_cycle_counter.v
-$BASEJUMP_STL_DIR/bsg_misc/bsg_decode.v
-$BASEJUMP_STL_DIR/bsg_misc/bsg_decode_with_v.v
-$BASEJUMP_STL_DIR/bsg_misc/bsg_dff.v
-$BASEJUMP_STL_DIR/bsg_misc/bsg_dff_en_bypass.v
-$BASEJUMP_STL_DIR/bsg_misc/bsg_dff_chain.v
-$BASEJUMP_STL_DIR/bsg_misc/bsg_dff_en.v
-$BASEJUMP_STL_DIR/bsg_misc/bsg_dff_reset.v
-$BASEJUMP_STL_DIR/bsg_misc/bsg_dff_reset_en.v
-$BASEJUMP_STL_DIR/bsg_misc/bsg_encode_one_hot.v
-$BASEJUMP_STL_DIR/bsg_misc/bsg_lfsr.v
-$BASEJUMP_STL_DIR/bsg_misc/bsg_lru_pseudo_tree_decode.v
-$BASEJUMP_STL_DIR/bsg_misc/bsg_lru_pseudo_tree_encode.v
-$BASEJUMP_STL_DIR/bsg_misc/bsg_mux.v
-$BASEJUMP_STL_DIR/bsg_misc/bsg_mux_butterfly.v
-$BASEJUMP_STL_DIR/bsg_misc/bsg_mux_one_hot.v
-$BASEJUMP_STL_DIR/bsg_misc/bsg_mux_segmented.v
-$BASEJUMP_STL_DIR/bsg_misc/bsg_priority_encode.v
-$BASEJUMP_STL_DIR/bsg_misc/bsg_priority_encode_one_hot_out.v
-$BASEJUMP_STL_DIR/bsg_misc/bsg_round_robin_arb.v
-$BASEJUMP_STL_DIR/bsg_misc/bsg_scan.v
-$BASEJUMP_STL_DIR/bsg_misc/bsg_swap.v
-$BASEJUMP_STL_DIR/bsg_misc/bsg_thermometer_count.v
-$BASEJUMP_STL_DIR/bsg_misc/bsg_transpose.v
-$BASEJUMP_STL_DIR/bsg_misc/bsg_unconcentrate_static.v
-$BASEJUMP_STL_DIR/bsg_noc/bsg_mesh_router.v
-$BASEJUMP_STL_DIR/bsg_noc/bsg_mesh_router_buffered.v
-$BASEJUMP_STL_DIR/bsg_noc/bsg_noc_repeater_node.v
-$BASEJUMP_STL_DIR/bsg_noc/bsg_wormhole_concentrator.v
-$BASEJUMP_STL_DIR/bsg_noc/bsg_wormhole_concentrator_in.v
-$BASEJUMP_STL_DIR/bsg_noc/bsg_wormhole_concentrator_out.v
-$BASEJUMP_STL_DIR/bsg_noc/bsg_wormhole_router.v
-$BASEJUMP_STL_DIR/bsg_noc/bsg_wormhole_router_adapter.v
-$BASEJUMP_STL_DIR/bsg_noc/bsg_wormhole_router_adapter_in.v
-$BASEJUMP_STL_DIR/bsg_noc/bsg_wormhole_router_adapter_out.v
-$BASEJUMP_STL_DIR/bsg_noc/bsg_wormhole_router_decoder_dor.v
-$BASEJUMP_STL_DIR/bsg_noc/bsg_wormhole_router_input_control.v  
-$BASEJUMP_STL_DIR/bsg_noc/bsg_wormhole_router_output_control.v 
-// Common files
-$BP_COMMON_DIR/src/v/bsg_fifo_1r1w_fence.v
-$BP_COMMON_DIR/src/v/bsg_fifo_1r1w_rolly.v
-$BP_COMMON_DIR/src/v/bp_tlb.v
-$BP_COMMON_DIR/src/v/bp_tlb_replacement.v
-// BE files
-$BP_BE_DIR/src/v/bp_be_top.v
-// Calculator
-$BP_BE_DIR/src/v/bp_be_calculator/bp_be_bypass.v
-$BP_BE_DIR/src/v/bp_be_calculator/bp_be_calculator_top.v
-$BP_BE_DIR/src/v/bp_be_calculator/bp_be_instr_decoder.v
-$BP_BE_DIR/src/v/bp_be_calculator/bp_be_int_alu.v
-$BP_BE_DIR/src/v/bp_be_calculator/bp_be_pipe_fp.v
-$BP_BE_DIR/src/v/bp_be_calculator/bp_be_pipe_int.v
-$BP_BE_DIR/src/v/bp_be_calculator/bp_be_pipe_mem.v
-$BP_BE_DIR/src/v/bp_be_calculator/bp_be_pipe_mul.v
-$BP_BE_DIR/src/v/bp_be_calculator/bp_be_regfile.v
-// Checker
-$BP_BE_DIR/src/v/bp_be_checker/bp_be_checker_top.v
-$BP_BE_DIR/src/v/bp_be_checker/bp_be_detector.v
-$BP_BE_DIR/src/v/bp_be_checker/bp_be_director.v
-$BP_BE_DIR/src/v/bp_be_checker/bp_be_scheduler.v
-// MMU
-$BP_BE_DIR/src/v/bp_be_mem/bp_be_ptw.v
-$BP_BE_DIR/src/v/bp_be_mem/bp_be_csr.v
-$BP_BE_DIR/src/v/bp_be_mem/bp_be_dcache/bp_be_dcache.v
-$BP_BE_DIR/src/v/bp_be_mem/bp_be_dcache/bp_be_dcache_lce_cmd.v
-$BP_BE_DIR/src/v/bp_be_mem/bp_be_dcache/bp_be_dcache_lce.v
-$BP_BE_DIR/src/v/bp_be_mem/bp_be_dcache/bp_be_dcache_lce_req.v
-$BP_BE_DIR/src/v/bp_be_mem/bp_be_dcache/bp_be_dcache_wbuf.v
-$BP_BE_DIR/src/v/bp_be_mem/bp_be_dcache/bp_be_dcache_wbuf_queue.v
-$BP_BE_DIR/src/v/bp_be_mem/bp_be_mem_top.v
-//// FE files
-$BP_FE_DIR/src/v/bp_fe_bht.v
-$BP_FE_DIR/src/v/bp_fe_btb.v
-$BP_FE_DIR/src/v/bp_fe_lce_cmd.v
-$BP_FE_DIR/src/v/bp_fe_icache.v
-$BP_FE_DIR/src/v/bp_fe_instr_scan.v
-$BP_FE_DIR/src/v/bp_fe_lce.v
-$BP_FE_DIR/src/v/bp_fe_lce_req.v
-$BP_FE_DIR/src/v/bp_fe_mem.v
-$BP_FE_DIR/src/v/bp_fe_pc_gen.v
-$BP_FE_DIR/src/v/bp_fe_top.v
-//// ME files
-// CCE
-$BP_ME_DIR/src/v/cce/bp_cce.v
-$BP_ME_DIR/src/v/cce/bp_cce_alu.v
-$BP_ME_DIR/src/v/cce/bp_cce_dir.v
-$BP_ME_DIR/src/v/cce/bp_cce_dir_tag_checker.v
-$BP_ME_DIR/src/v/cce/bp_cce_dir_lru_extract.v
-$BP_ME_DIR/src/v/cce/bp_cce_gad.v
-$BP_ME_DIR/src/v/cce/bp_cce_inst_decode.v
-$BP_ME_DIR/src/v/cce/bp_cce_msg.v
-$BP_ME_DIR/src/v/cce/bp_cce_msg_cached.v
-$BP_ME_DIR/src/v/cce/bp_cce_msg_uncached.v
-$BP_ME_DIR/src/v/cce/bp_cce_pc.v
-$BP_ME_DIR/src/v/cce/bp_cce_pending.v
-$BP_ME_DIR/src/v/cce/bp_cce_reg.v
-$BP_ME_DIR/src/v/cce/bp_cce_top.v
-// Network
-$BP_ME_DIR/src/v/wormhole/bp_me_cce_id_to_cord.v
-$BP_ME_DIR/src/v/wormhole/bp_me_cce_to_wormhole_link_client.v
-$BP_ME_DIR/src/v/wormhole/bp_me_cce_to_wormhole_link_master.v
-$BP_ME_DIR/src/v/wormhole/bp_me_lce_id_to_cord.v
-$BP_ME_DIR/src/v/wormhole/bp_me_wormhole_packet_encode_lce_cmd.v
-$BP_ME_DIR/src/v/wormhole/bp_me_wormhole_packet_encode_lce_req.v
-$BP_ME_DIR/src/v/wormhole/bp_me_wormhole_packet_encode_lce_resp.v
-$BP_ME_DIR/src/v/wormhole/bp_me_wormhole_packet_encode_mem_cmd.v
-$BP_ME_DIR/src/v/wormhole/bp_me_wormhole_packet_encode_mem_resp.v
-//// TOP
-$BP_TOP_DIR/src/v/bp_chip.v
-$BP_TOP_DIR/src/v/bp_core.v
-$BP_TOP_DIR/src/v/bp_core_complex.v
-$BP_TOP_DIR/src/v/bp_mem_complex.v
-$BP_TOP_DIR/src/v/bp_mmio_enclave.v
-$BP_TOP_DIR/src/v/bp_mmio_node.v
-$BP_TOP_DIR/src/v/bp_tile.v
-$BP_TOP_DIR/src/v/bp_tile_node.v
-//// Common
-$BP_COMMON_DIR/src/v/bp_addr_map.v
-
-// bsg_ip_cores files
-$BASEJUMP_STL_DIR/bsg_fsb/bsg_fsb_node_trace_replay.v
-// be files
-//$BP_BE_DIR/test/common/bp_be_nonsynth_tracer.v
-// $BP_BE_DIR/test/common/bp_be_nonsynth_perf.v
-// me files
-// $BP_ME_DIR/test/common/bp_mem.v
-// $BP_ME_DIR/test/common/bp_mem_delay_model.v
-// $BP_ME_DIR/test/common/bp_mem_transducer.v
-// $BP_ME_DIR/test/common/bp_mem_storage_sync.v
-// $BP_ME_DIR/test/common/dramsim2_wrapper.cpp
-$BP_ME_DIR/test/common/bp_cce_mmio_cfg_loader.v
-// $BP_ME_DIR/test/common/bp_mem_nonsynth_tracer.v
-// $BP_ME_DIR/test/common/bp_cce_nonsynth_tracer.v
-// $BP_ME_DIR/test/common/bp_mem_utils.cpp
-// top files
-$BP_TOP_DIR/test/common/bp_nonsynth_host.v
-// $BP_TOP_DIR/test/common/bp_nonsynth_if_verif.v
-//$BP_TOP_DIR/test/common/bp_nonsynth_commit_tracer.v
-// /home/scanakci/Research_sado/litex/litex/litex/soc/cores/cpu/blackparrot/pre-alpha-release/bp_top/syn/results/verilator/bp_top_trace_demo.e_bp_single_core_cfg.build/wrapper.v
-// /home/scanakci/Research_sado/litex/litex/litex/soc/cores/cpu/blackparrot/pre-alpha-release/bp_top/syn/results/verilator/bp_top_trace_demo.e_bp_single_core_cfg.build/test_bp.cpp
-$BP_TOP_DIR/test/common/bp_monitor.cpp
-$BP_FPGA_DIR/bp2wb_convertor.v
-$BP_FPGA_DIR/ExampleBlackParrotSystem.v
-$BP_FPGA_DIR/bsg_mem_1rw_sync_mask_write_bit.v
-// Recent
-$BASEJUMP_STL_DIR/bsg_noc/bsg_mesh_stitch.v
diff --git a/litex/soc/cores/cpu/blackparrot/setEnvironment.sh b/litex/soc/cores/cpu/blackparrot/setEnvironment.sh
index 1e45ca903..0f6fa1268 100755
--- a/litex/soc/cores/cpu/blackparrot/setEnvironment.sh
+++ b/litex/soc/cores/cpu/blackparrot/setEnvironment.sh
@@ -15,10 +15,10 @@ export BP_EXTERNAL_DIR=$BP/external
 export BASEJUMP_STL_DIR=$BP_EXTERNAL_DIR/basejump_stl
 export LITEX_FPGA_DIR=$BP_LITEX_DIR/fpga
 export LITEX_SIMU_DIR=$BP_LITEX_DIR/simulation
-export LITEX_SOFTWARE=$BP_LITEX_DIR/software
+export BP_LITEX_SOFTWARE=$BP_LITEX_DIR/software
 
 ##SOFTWARE CHANGES##
 
 #for a reason, provided udivmoddi4.c is not functionally correct when used with either BP or Rocket under IA extension. Another version of udivmoddi4.c is a workaround to run BIOS on these architectures.
-cp $LITEX_SOFTWARE/udivmoddi4.c $LITEX_SOFTWARE_COMPILER_RT/pythondata_software_compiler_rt/data/lib/builtins/.
+cp $BP_LITEX_SOFTWARE/udivmoddi4.c $LITEX_SOFTWARE_COMPILER_RT/pythondata_software_compiler_rt/data/lib/builtins/.
 
diff --git a/litex/soc/cores/cpu/blackparrot/update_BP.sh b/litex/soc/cores/cpu/blackparrot/update_BP.sh
deleted file mode 100755
index c6ddde977..000000000
--- a/litex/soc/cores/cpu/blackparrot/update_BP.sh
+++ /dev/null
@@ -1,17 +0,0 @@
-#!/bin/bash
-
-
-##SOFTWARE CHANGES##
-
-#for a reason, provided udivmoddi4.c is not functionally correct when used with either BP or Rocket under IA extension. Another version of udivmoddi4.c is a workaround to run BIOS on these architectures.
-cp bp_software/udivmoddi4.c $LITEX/litex/soc/software/compiler_rt/lib/builtins/.
-cp bp_software/cce_ucode.mem /tmp/.
-
-##HARDWARE CHANGES## 
-#Need to change some files because of memory map differences and proper syntesis
-cp bp_hardware/bp_common_pkg.vh $BP_COMMON_DIR/src/include/.
-cp bp_hardware/bp_cce_mmio_cfg_loader.v $BP_ME_DIR/test/common/.
-cp bp_hardware/bp_nonsynth_host.v $BP_TOP_DIR/test/common/.
-
-# Neccessary files for FPGA Implementations
-cp -r bp_fpga $BP_TOP/DIR
diff --git a/litex/soc/software/bios/Makefile b/litex/soc/software/bios/Makefile
index cc58ddf3a..4d6bc6f76 100755
--- a/litex/soc/software/bios/Makefile
+++ b/litex/soc/software/bios/Makefile
@@ -2,7 +2,7 @@ include ../include/generated/variables.mak
 include $(SOC_DIRECTORY)/software/common.mak
 
 ifeq ($(CPU),blackparrot)
-BP_LIBS =  -L$(LITEX_SOFTWARE)
+BP_LIBS =  -L$(BP_LITEX_SOFTWARE)
 BP_FLAGS = -lgcc
 endif
 # Permit TFTP_SERVER_PORT override from shell environment / command line
diff --git a/litex/soc/software/bios/boot.c b/litex/soc/software/bios/boot.c
index 274cd789f..08b3be4a8 100644
--- a/litex/soc/software/bios/boot.c
+++ b/litex/soc/software/bios/boot.c
@@ -32,8 +32,6 @@
 #include "sfl.h"
 #include "boot.h"
 
-#define MEMTEST_DATA_SIZE2 (589824*4)
-
 extern void boot_helper(unsigned long r1, unsigned long r2, unsigned long r3, unsigned long addr);
 
 static void __attribute__((noreturn)) boot(unsigned long r1, unsigned long r2, unsigned long r3, unsigned long addr)
@@ -61,16 +59,7 @@ static void __attribute__((noreturn)) boot(unsigned long r1, unsigned long r2, u
 	mtspr(SPR_EVBAR, addr);
 	addr += 0x100;
 #endif
-          
 
-/*        volatile unsigned int *array = (unsigned int *)MAIN_RAM_BASE;
-        int i;
-        unsigned int rdata;
-        for(i=0;i<MEMTEST_DATA_SIZE2/4;i++) {
-                rdata = array[i];
-                printf("[data 0x%0x]: 0x%08x\n",i,rdata);
-         }
-*/
 	boot_helper(r1, r2, r3, addr);
 	while(1);
 }
diff --git a/litex/soc/software/bios/isr.c b/litex/soc/software/bios/isr.c
index d6b417219..0044f3d16 100644
--- a/litex/soc/software/bios/isr.c
+++ b/litex/soc/software/bios/isr.c
@@ -78,8 +78,6 @@ void isr(void)
 
 #else
 
-void isr(void){
-printf("ISR blackparrot\n");
-};
+void isr(void){};
 
 #endif
diff --git a/litex/soc/software/include/base/ctype.h b/litex/soc/software/include/base/ctype.h
index 7542e4402..693685933 100644
--- a/litex/soc/software/include/base/ctype.h
+++ b/litex/soc/software/include/base/ctype.h
@@ -26,11 +26,7 @@ extern const unsigned char _ctype[];
 #define isalnum(c)	((__ismask(c)&(_U|_L|_D)) != 0)
 #define isalpha(c)	((__ismask(c)&(_U|_L)) != 0)
 #define iscntrl(c)	((__ismask(c)&(_C)) != 0)
-//#define isdigit(c)	((__ismask(c)&(_D)) != 0)
-static int isdigit(char c){
-  if ((c>='0') && (c<='9')) return 1;
-    return 0;
-}
+#define isdigit(c)	((__ismask(c)&(_D)) != 0)
 #define isgraph(c)	((__ismask(c)&(_P|_U|_L|_D)) != 0)
 #define islower(c)	((__ismask(c)&(_L)) != 0)
 #define isprint(c)	((__ismask(c)&(_P|_U|_L|_D|_SP)) != 0)
diff --git a/litex/soc/software/libbase/libc.c b/litex/soc/software/libbase/libc.c
index 698ec59cc..be48cf651 100644
--- a/litex/soc/software/libbase/libc.c
+++ b/litex/soc/software/libbase/libc.c
@@ -23,7 +23,7 @@
 #include <string.h>
 #include <limits.h>
 #include <inet.h>
-#include <errno.h>
+
 /**
  * strchr - Find the first occurrence of a character in a string
  * @s: The string to be searched
@@ -375,7 +375,7 @@ void *memchr(const void *s, int c, size_t n)
  * @base: The number base to use
  */
 unsigned long strtoul(const char *nptr, char **endptr, int base)
-{       printf("HI\n");
+{
 	unsigned long result = 0,value;
 
 	if (!base) {
@@ -392,14 +392,11 @@ unsigned long strtoul(const char *nptr, char **endptr, int base)
 		if (nptr[0] == '0' && toupper(nptr[1]) == 'X')
 			nptr += 2;
 	}
-        printf("HI2\n");
 	while (isxdigit(*nptr) &&
 	       (value = isdigit(*nptr) ? *nptr-'0' : toupper(*nptr)-'A'+10) < base) {
 		result = result*base + value;
 		nptr++;
-                printf("HI4\n");
 	}
-        printf("HI3\n");
 	if (endptr)
 		*endptr = (char *)nptr;
 	return result;
diff --git a/litex/soc/software/libnet/tftp.c b/litex/soc/software/libnet/tftp.c
index d51107388..439b3e075 100644
--- a/litex/soc/software/libnet/tftp.c
+++ b/litex/soc/software/libnet/tftp.c
@@ -117,11 +117,10 @@ int tftp_get(uint32_t ip, uint16_t server_port, const char *filename,
 	int i;
 	int length_before;
 	int spin = 0;
-        printf("DEBUGWTH?\n");
 
 	if(!microudp_arp_resolve(ip))
 		return -1;
-        printf("DEBUG0\n");
+
 	microudp_set_callback(rx_callback);
 
 	dst_buffer = buffer;
@@ -130,8 +129,6 @@ int tftp_get(uint32_t ip, uint16_t server_port, const char *filename,
 	transfer_finished = 0;
 	tries = 5;
 	while(1) {
-                
-                printf("DEBUG1\n");
 		packet_data = microudp_get_tx_buffer();
 		len = format_request(packet_data, TFTP_RRQ, filename);
 		microudp_send(PORT_IN, server_port, len);
@@ -139,8 +136,6 @@ int tftp_get(uint32_t ip, uint16_t server_port, const char *filename,
 			microudp_service();
 			if((total_length > 0) || transfer_finished) break;
 		}
-
-                printf("DEBUG2\n");
 		if((total_length > 0) || transfer_finished) break;
 		tries--;
 		if(tries == 0) {
@@ -149,7 +144,6 @@ int tftp_get(uint32_t ip, uint16_t server_port, const char *filename,
 		}
 	}
 
-        printf("DEBUG3\n");
 	i = 12000000;
 	length_before = total_length;
 	while(!transfer_finished) {
@@ -168,10 +162,8 @@ int tftp_get(uint32_t ip, uint16_t server_port, const char *filename,
 		microudp_service();
 	}
 
-        printf("DEBUG4\n");
 	microudp_set_callback(NULL);
 
-        printf("DEBUG5\n");
 	return total_length;
 }
 
diff --git a/litex/tools/litex_sim.py b/litex/tools/litex_sim.py
index 86c6d9692..987681d33 100755
--- a/litex/tools/litex_sim.py
+++ b/litex/tools/litex_sim.py
@@ -177,7 +177,6 @@ class SimSoC(SoCSDRAM):
             ident               = "LiteX Simulation", ident_version=True,
             l2_reverse          = False,
             **kwargs)
-#        self.add_constant("UART_POLLING",None)
         # CRG --------------------------------------------------------------------------------------
         self.submodules.crg = CRG(platform.request("sys_clk"))
 
@@ -353,8 +352,8 @@ def main():
         with_analyzer  = args.with_analyzer,
         sdram_init     = [] if args.sdram_init is None else get_mem_data(args.sdram_init, cpu_endianness),
         **soc_kwargs)
-    if args.ram_init is not None: #sdram_init
-        soc.add_constant("ROM_BOOT_ADDRESS", 0x80000000)
+    if args.ram_init is not None:
+        soc.add_constant("ROM_BOOT_ADDRESS", 0x40000000)
     if args.with_ethernet:
         for i in range(4):
             soc.add_constant("LOCALIP{}".format(i+1), int(args.local_ip.split(".")[i]))

From d81f171c8ac594cc6792887b645b58a961ff4ead Mon Sep 17 00:00:00 2001
From: Florent Kermarrec <florent@enjoy-digital.fr>
Date: Sat, 2 May 2020 11:02:51 +0200
Subject: [PATCH 69/95] software/libbase/system.c: remove unused includes.

---
 litex/soc/software/libbase/system.c | 7 -------
 1 file changed, 7 deletions(-)

diff --git a/litex/soc/software/libbase/system.c b/litex/soc/software/libbase/system.c
index f9e37eb28..ed4110dde 100644
--- a/litex/soc/software/libbase/system.c
+++ b/litex/soc/software/libbase/system.c
@@ -1,12 +1,5 @@
 #include <irq.h>
 #include <uart.h>
-#ifdef __or1k__
-#include <spr-defs.h>
-#endif
-
-#if defined (__vexriscv__)
-#include <csr-defs.h>
-#endif
 
 #include <system.h>
 #include <generated/mem.h>

From 4efc783534320d6a7f7561e76c9a6560456f4fa9 Mon Sep 17 00:00:00 2001
From: Florent Kermarrec <florent@enjoy-digital.fr>
Date: Sat, 2 May 2020 11:52:58 +0200
Subject: [PATCH 70/95] cpus: add human_name attribute and use it to simplify
 the BIOS.

---
 litex/soc/cores/cpu/blackparrot/core.py | 11 ++++++-----
 litex/soc/cores/cpu/lm32/core.py        |  1 +
 litex/soc/cores/cpu/microwatt/core.py   |  1 +
 litex/soc/cores/cpu/minerva/core.py     |  1 +
 litex/soc/cores/cpu/mor1kx/core.py      |  1 +
 litex/soc/cores/cpu/picorv32/core.py    |  1 +
 litex/soc/cores/cpu/rocket/core.py      |  1 +
 litex/soc/cores/cpu/serv/core.py        |  1 +
 litex/soc/cores/cpu/vexriscv/core.py    |  1 +
 litex/soc/integration/soc.py            |  5 +++--
 litex/soc/software/bios/main.c          | 25 ++++---------------------
 11 files changed, 21 insertions(+), 28 deletions(-)

diff --git a/litex/soc/cores/cpu/blackparrot/core.py b/litex/soc/cores/cpu/blackparrot/core.py
index 6b15a964a..03690eb81 100644
--- a/litex/soc/cores/cpu/blackparrot/core.py
+++ b/litex/soc/cores/cpu/blackparrot/core.py
@@ -47,13 +47,14 @@ GCC_FLAGS = {
 
 class BlackParrotRV64(CPU):
     name                 = "blackparrot"
+    human_name           = "BlackParrotRV64[ia]"
     data_width           = 64
     endianness           = "little"
     gcc_triple           = ("riscv64-unknown-elf", "riscv64-linux", "riscv-sifive-elf",
                             "riscv64-none-elf")
     linker_output_format = "elf64-littleriscv"
     io_regions           = {0x50000000: 0x10000000} # origin, length
-   
+
     @property
     def mem_map(self):
         return {
@@ -87,10 +88,10 @@ class BlackParrotRV64(CPU):
             # clock, reset
             i_clk_i = ClockSignal(),
             i_reset_i = ResetSignal() | self.reset,
-            
-            # irq           
+
+            # irq
             #i_interrupts = self.interrupt,
-            
+
             #wishbone
             i_wbm_dat_i = idbus.dat_r,
             o_wbm_dat_o = idbus.dat_w,
@@ -105,7 +106,7 @@ class BlackParrotRV64(CPU):
             o_wbm_cti_o = idbus.cti,
             o_wbm_bte_o = idbus.bte,
             )
-     
+
            # add verilog sources
         self.add_sources(platform, variant)
 
diff --git a/litex/soc/cores/cpu/lm32/core.py b/litex/soc/cores/cpu/lm32/core.py
index 42d5a9754..f05329fa7 100644
--- a/litex/soc/cores/cpu/lm32/core.py
+++ b/litex/soc/cores/cpu/lm32/core.py
@@ -18,6 +18,7 @@ CPU_VARIANTS = ["minimal", "lite", "standard"]
 
 class LM32(CPU):
     name                 = "lm32"
+    human_name           = "LM32"
     data_width           = 32
     endianness           = "big"
     gcc_triple           = "lm32-elf"
diff --git a/litex/soc/cores/cpu/microwatt/core.py b/litex/soc/cores/cpu/microwatt/core.py
index ba3867d79..808ac0a74 100644
--- a/litex/soc/cores/cpu/microwatt/core.py
+++ b/litex/soc/cores/cpu/microwatt/core.py
@@ -16,6 +16,7 @@ CPU_VARIANTS = ["standard"]
 
 class Microwatt(CPU):
     name                 = "microwatt"
+    human_name           = "Microwatt"
     data_width           = 64
     endianness           = "little"
     gcc_triple           = ("powerpc64le-linux")
diff --git a/litex/soc/cores/cpu/minerva/core.py b/litex/soc/cores/cpu/minerva/core.py
index b703f2f13..524cd7f0e 100644
--- a/litex/soc/cores/cpu/minerva/core.py
+++ b/litex/soc/cores/cpu/minerva/core.py
@@ -16,6 +16,7 @@ CPU_VARIANTS = ["standard"]
 
 class Minerva(CPU):
     name                 = "minerva"
+    human_name           = "Minerva"
     data_width           = 32
     endianness           = "little"
     gcc_triple           = ("riscv64-unknown-elf", "riscv32-unknown-elf", "riscv-none-embed",
diff --git a/litex/soc/cores/cpu/mor1kx/core.py b/litex/soc/cores/cpu/mor1kx/core.py
index 5dea660fb..8e91dd94c 100644
--- a/litex/soc/cores/cpu/mor1kx/core.py
+++ b/litex/soc/cores/cpu/mor1kx/core.py
@@ -17,6 +17,7 @@ CPU_VARIANTS = ["standard", "linux"]
 
 class MOR1KX(CPU):
     name                 = "mor1kx"
+    human_name           = "MOR1KX"
     data_width           = 32
     endianness           = "big"
     gcc_triple           = "or1k-elf"
diff --git a/litex/soc/cores/cpu/picorv32/core.py b/litex/soc/cores/cpu/picorv32/core.py
index ebb96b810..761a926e1 100644
--- a/litex/soc/cores/cpu/picorv32/core.py
+++ b/litex/soc/cores/cpu/picorv32/core.py
@@ -33,6 +33,7 @@ GCC_FLAGS = {
 
 class PicoRV32(CPU):
     name                 = "picorv32"
+    human_name           = "PicoRV32"
     data_width           = 32
     endianness           = "little"
     gcc_triple           = ("riscv64-unknown-elf", "riscv32-unknown-elf", "riscv-none-embed",
diff --git a/litex/soc/cores/cpu/rocket/core.py b/litex/soc/cores/cpu/rocket/core.py
index 80d300fea..cac2b05bb 100644
--- a/litex/soc/cores/cpu/rocket/core.py
+++ b/litex/soc/cores/cpu/rocket/core.py
@@ -66,6 +66,7 @@ AXI_DATA_WIDTHS = {
 
 class RocketRV64(CPU):
     name                 = "rocket"
+    human_name           = "RocketRV64[imac]"
     data_width           = 64
     endianness           = "little"
     gcc_triple           = ("riscv64-unknown-elf", "riscv64-linux", "riscv-sifive-elf",
diff --git a/litex/soc/cores/cpu/serv/core.py b/litex/soc/cores/cpu/serv/core.py
index d99661d66..ee31b3487 100644
--- a/litex/soc/cores/cpu/serv/core.py
+++ b/litex/soc/cores/cpu/serv/core.py
@@ -16,6 +16,7 @@ CPU_VARIANTS = ["standard"]
 
 class SERV(CPU):
     name                 = "serv"
+    human_name           = "SERV"
     data_width           = 32
     endianness           = "little"
     gcc_triple           = ("riscv64-unknown-elf", "riscv32-unknown-elf", "riscv-none-embed",
diff --git a/litex/soc/cores/cpu/vexriscv/core.py b/litex/soc/cores/cpu/vexriscv/core.py
index 8e27e5d3f..990333bd9 100644
--- a/litex/soc/cores/cpu/vexriscv/core.py
+++ b/litex/soc/cores/cpu/vexriscv/core.py
@@ -76,6 +76,7 @@ class VexRiscvTimer(Module, AutoCSR):
 
 class VexRiscv(CPU, AutoCSR):
     name                 = "vexriscv"
+    human_name           = "VexRiscv"
     data_width           = 32
     endianness           = "little"
     gcc_triple           = ("riscv64-unknown-elf", "riscv32-unknown-elf", "riscv-none-embed",
diff --git a/litex/soc/integration/soc.py b/litex/soc/integration/soc.py
index 55557ecf1..0256fc77b 100644
--- a/litex/soc/integration/soc.py
+++ b/litex/soc/integration/soc.py
@@ -793,8 +793,9 @@ class SoC(Module):
                 self.comb += self.cpu.reset.eq(self.ctrl.reset)
             self.add_config("CPU_RESET_ADDR", reset_address)
         # Add constants
-        self.add_config("CPU_TYPE",    str(name))
-        self.add_config("CPU_VARIANT", str(variant.split('+')[0]))
+        self.add_config("CPU_TYPE",       str(name))
+        self.add_config("CPU_VARIANT",    str(variant.split('+')[0]))
+        self.add_constant("CONFIG_CPU_HUMAN_NAME", getattr(self.cpu, "human_name", "Unknown"))
 
     def add_timer(self, name="timer0"):
         self.check_if_exists(name)
diff --git a/litex/soc/software/bios/main.c b/litex/soc/software/bios/main.c
index e985dd5a3..7864260aa 100644
--- a/litex/soc/software/bios/main.c
+++ b/litex/soc/software/bios/main.c
@@ -25,6 +25,7 @@
 #include <crc.h>
 
 #include <generated/csr.h>
+#include <generated/soc.h>
 #include <generated/mem.h>
 #include <generated/git.h>
 
@@ -101,27 +102,9 @@ int main(int i, char **c)
 	printf(" LiteX git sha1: "LITEX_GIT_SHA1"\n");
 	printf("\n");
 	printf("--=============== \e[1mSoC\e[0m ==================--\n");
-	printf("\e[1mCPU\e[0m:       ");
-#ifdef __lm32__
-	printf("LM32");
-#elif __or1k__
-	printf("MOR1KX");
-#elif __picorv32__
-	printf("PicoRV32");
-#elif __vexriscv__
-	printf("VexRiscv");
-#elif __minerva__
-	printf("Minerva");
-#elif __rocket__
-	printf("RocketRV64[imac]");
-#elif __blackparrot__
-        printf("BlackParrotRV64[ia]");
-#elif __serv__
-	printf("SERV");
-#else
-	printf("Unknown");
-#endif
-	printf(" @ %dMHz\n", CONFIG_CLOCK_FREQUENCY/1000000);
+	printf("\e[1mCPU\e[0m:       %s @ %dMHz\n",
+		CONFIG_CPU_HUMAN_NAME,
+		CONFIG_CLOCK_FREQUENCY/1000000);
 	printf("\e[1mROM\e[0m:       %dKB\n", ROM_SIZE/1024);
 	printf("\e[1mSRAM\e[0m:      %dKB\n", SRAM_SIZE/1024);
 #ifdef CONFIG_L2_SIZE

From 97e534d0b6d42d79b9a3d088490f1c159b1107df Mon Sep 17 00:00:00 2001
From: Florent Kermarrec <florent@enjoy-digital.fr>
Date: Sat, 2 May 2020 12:04:46 +0200
Subject: [PATCH 71/95] cpus: add nop instruction and use it to simplify the
 BIOS.

---
 litex/soc/cores/cpu/blackparrot/core.py |  1 +
 litex/soc/cores/cpu/lm32/core.py        |  1 +
 litex/soc/cores/cpu/microwatt/core.py   |  1 +
 litex/soc/cores/cpu/minerva/core.py     |  1 +
 litex/soc/cores/cpu/mor1kx/core.py      |  1 +
 litex/soc/cores/cpu/picorv32/core.py    |  1 +
 litex/soc/cores/cpu/rocket/core.py      |  1 +
 litex/soc/cores/cpu/serv/core.py        |  1 +
 litex/soc/cores/cpu/vexriscv/core.py    |  1 +
 litex/soc/integration/soc.py            |  6 ++++--
 litex/soc/software/bios/sdram.c         | 25 +------------------------
 11 files changed, 14 insertions(+), 26 deletions(-)

diff --git a/litex/soc/cores/cpu/blackparrot/core.py b/litex/soc/cores/cpu/blackparrot/core.py
index 03690eb81..302aa70dc 100644
--- a/litex/soc/cores/cpu/blackparrot/core.py
+++ b/litex/soc/cores/cpu/blackparrot/core.py
@@ -53,6 +53,7 @@ class BlackParrotRV64(CPU):
     gcc_triple           = ("riscv64-unknown-elf", "riscv64-linux", "riscv-sifive-elf",
                             "riscv64-none-elf")
     linker_output_format = "elf64-littleriscv"
+    nop                  = "nop"
     io_regions           = {0x50000000: 0x10000000} # origin, length
 
     @property
diff --git a/litex/soc/cores/cpu/lm32/core.py b/litex/soc/cores/cpu/lm32/core.py
index f05329fa7..2b6273f3d 100644
--- a/litex/soc/cores/cpu/lm32/core.py
+++ b/litex/soc/cores/cpu/lm32/core.py
@@ -23,6 +23,7 @@ class LM32(CPU):
     endianness           = "big"
     gcc_triple           = "lm32-elf"
     linker_output_format = "elf32-lm32"
+    nop                  = "nop"
     io_regions           = {0x80000000: 0x80000000} # origin, length
 
     @property
diff --git a/litex/soc/cores/cpu/microwatt/core.py b/litex/soc/cores/cpu/microwatt/core.py
index 808ac0a74..76eb59dc7 100644
--- a/litex/soc/cores/cpu/microwatt/core.py
+++ b/litex/soc/cores/cpu/microwatt/core.py
@@ -21,6 +21,7 @@ class Microwatt(CPU):
     endianness           = "little"
     gcc_triple           = ("powerpc64le-linux")
     linker_output_format = "elf64-powerpcle"
+    nop                  = "nop"
     io_regions           = {0xc0000000: 0x10000000} # origin, length
 
     @property
diff --git a/litex/soc/cores/cpu/minerva/core.py b/litex/soc/cores/cpu/minerva/core.py
index 524cd7f0e..2a6f21f9e 100644
--- a/litex/soc/cores/cpu/minerva/core.py
+++ b/litex/soc/cores/cpu/minerva/core.py
@@ -22,6 +22,7 @@ class Minerva(CPU):
     gcc_triple           = ("riscv64-unknown-elf", "riscv32-unknown-elf", "riscv-none-embed",
                             "riscv64-linux", "riscv-sifive-elf", "riscv64-none-elf")
     linker_output_format = "elf32-littleriscv"
+    nop                  = "nop"
     io_regions           = {0x80000000: 0x80000000} # origin, length
 
     @property
diff --git a/litex/soc/cores/cpu/mor1kx/core.py b/litex/soc/cores/cpu/mor1kx/core.py
index 8e91dd94c..5f05ef340 100644
--- a/litex/soc/cores/cpu/mor1kx/core.py
+++ b/litex/soc/cores/cpu/mor1kx/core.py
@@ -23,6 +23,7 @@ class MOR1KX(CPU):
     gcc_triple           = "or1k-elf"
     clang_triple         = "or1k-linux"
     linker_output_format = "elf32-or1k"
+    nop                  = "l.nop"
     io_regions           = {0x80000000: 0x80000000} # origin, length
 
     @property
diff --git a/litex/soc/cores/cpu/picorv32/core.py b/litex/soc/cores/cpu/picorv32/core.py
index 761a926e1..b3bfc0747 100644
--- a/litex/soc/cores/cpu/picorv32/core.py
+++ b/litex/soc/cores/cpu/picorv32/core.py
@@ -39,6 +39,7 @@ class PicoRV32(CPU):
     gcc_triple           = ("riscv64-unknown-elf", "riscv32-unknown-elf", "riscv-none-embed",
                             "riscv64-linux", "riscv-sifive-elf", "riscv64-none-elf")
     linker_output_format = "elf32-littleriscv"
+    nop                  = "nop"
     io_regions           = {0x80000000: 0x80000000} # origin, length
 
     @property
diff --git a/litex/soc/cores/cpu/rocket/core.py b/litex/soc/cores/cpu/rocket/core.py
index cac2b05bb..e0100c769 100644
--- a/litex/soc/cores/cpu/rocket/core.py
+++ b/litex/soc/cores/cpu/rocket/core.py
@@ -72,6 +72,7 @@ class RocketRV64(CPU):
     gcc_triple           = ("riscv64-unknown-elf", "riscv64-linux", "riscv-sifive-elf",
                             "riscv64-none-elf")
     linker_output_format = "elf64-littleriscv"
+    nop                  = "nop"
     io_regions           = {0x10000000: 0x70000000} # origin, length
 
     @property
diff --git a/litex/soc/cores/cpu/serv/core.py b/litex/soc/cores/cpu/serv/core.py
index ee31b3487..dbb6a1b40 100644
--- a/litex/soc/cores/cpu/serv/core.py
+++ b/litex/soc/cores/cpu/serv/core.py
@@ -22,6 +22,7 @@ class SERV(CPU):
     gcc_triple           = ("riscv64-unknown-elf", "riscv32-unknown-elf", "riscv-none-embed",
                             "riscv64-linux", "riscv-sifive-elf", "riscv64-none-elf")
     linker_output_format = "elf32-littleriscv"
+    nop                  = "nop"
     io_regions           = {0x80000000: 0x80000000} # origin, length
 
     @property
diff --git a/litex/soc/cores/cpu/vexriscv/core.py b/litex/soc/cores/cpu/vexriscv/core.py
index 990333bd9..45fc0df9d 100644
--- a/litex/soc/cores/cpu/vexriscv/core.py
+++ b/litex/soc/cores/cpu/vexriscv/core.py
@@ -82,6 +82,7 @@ class VexRiscv(CPU, AutoCSR):
     gcc_triple           = ("riscv64-unknown-elf", "riscv32-unknown-elf", "riscv-none-embed",
                             "riscv64-linux", "riscv-sifive-elf", "riscv64-none-elf")
     linker_output_format = "elf32-littleriscv"
+    nop                  = "nop"
     io_regions           = {0x80000000: 0x80000000} # origin, length
 
     @property
diff --git a/litex/soc/integration/soc.py b/litex/soc/integration/soc.py
index 0256fc77b..8d5107625 100644
--- a/litex/soc/integration/soc.py
+++ b/litex/soc/integration/soc.py
@@ -793,9 +793,11 @@ class SoC(Module):
                 self.comb += self.cpu.reset.eq(self.ctrl.reset)
             self.add_config("CPU_RESET_ADDR", reset_address)
         # Add constants
-        self.add_config("CPU_TYPE",       str(name))
-        self.add_config("CPU_VARIANT",    str(variant.split('+')[0]))
+        self.add_config("CPU_TYPE",    str(name))
+        self.add_config("CPU_VARIANT", str(variant.split('+')[0]))
         self.add_constant("CONFIG_CPU_HUMAN_NAME", getattr(self.cpu, "human_name", "Unknown"))
+        if hasattr(self.cpu, "nop"):
+            self.add_constant("CONFIG_CPU_NOP", self.cpu.nop)
 
     def add_timer(self, name="timer0"):
         self.check_if_exists(name)
diff --git a/litex/soc/software/bios/sdram.c b/litex/soc/software/bios/sdram.c
index 1e139d5d2..1923b49b0 100644
--- a/litex/soc/software/bios/sdram.c
+++ b/litex/soc/software/bios/sdram.c
@@ -29,31 +29,8 @@
 
 __attribute__((unused)) static void cdelay(int i)
 {
-	/* FIXME: move nop definitions to CPUs */
 	while(i > 0) {
-#if defined (__lm32__)
-		__asm__ volatile("nop");
-#elif defined (__or1k__)
-		__asm__ volatile("l.nop");
-#elif defined (__picorv32__)
-		__asm__ volatile("nop");
-#elif defined (__vexriscv__)
-		__asm__ volatile("nop");
-#elif defined (__minerva__)
-		__asm__ volatile("nop");
-#elif defined (__rocket__)
-		__asm__ volatile("nop");
-#elif defined (__powerpc__)
-		__asm__ volatile("nop");
-#elif defined (__microwatt__)
-		__asm__ volatile("nop");
-#elif defined (__blackparrot__)
-		__asm__ volatile("nop");
-#elif defined (__serv__)
-		__asm__ volatile("nop");
-#else
-#error Unsupported architecture
-#endif
+		__asm__ volatile(CONFIG_CPU_NOP);
 		i--;
 	}
 }

From b02053357c22cd8e5595a024f2afb2b9363a85b3 Mon Sep 17 00:00:00 2001
From: Florent Kermarrec <florent@enjoy-digital.fr>
Date: Sat, 2 May 2020 20:07:52 +0200
Subject: [PATCH 72/95] cpu/vexriscv: fix flush_cpu_icache, remove workaround
 on boot.c.

---
 litex/soc/cores/cpu/vexriscv/system.h | 2 +-
 litex/soc/software/bios/boot.c        | 3 ---
 2 files changed, 1 insertion(+), 4 deletions(-)

diff --git a/litex/soc/cores/cpu/vexriscv/system.h b/litex/soc/cores/cpu/vexriscv/system.h
index 952b5b326..a8fbe42bb 100644
--- a/litex/soc/cores/cpu/vexriscv/system.h
+++ b/litex/soc/cores/cpu/vexriscv/system.h
@@ -10,7 +10,7 @@ extern "C" {
 __attribute__((unused)) static void flush_cpu_icache(void)
 {
   asm volatile(
-    ".word(0x400F)\n"
+    ".word(0x100F)\n"
     "nop\n"
     "nop\n"
     "nop\n"
diff --git a/litex/soc/software/bios/boot.c b/litex/soc/software/bios/boot.c
index 08b3be4a8..8f53fcca3 100644
--- a/litex/soc/software/bios/boot.c
+++ b/litex/soc/software/bios/boot.c
@@ -43,10 +43,7 @@ static void __attribute__((noreturn)) boot(unsigned long r1, unsigned long r2, u
 	irq_setmask(0);
 	irq_setie(0);
 #endif
-/* FIXME: understand why flushing icache on Vexriscv make boot fail  */
-#ifndef __vexriscv__
 	flush_cpu_icache();
-#endif
 	flush_cpu_dcache();
 #ifdef CONFIG_L2_SIZE
 	flush_l2_cache();

From 7c69a6dbba581a57fa9319a9ca4e60882e6f5f1f Mon Sep 17 00:00:00 2001
From: Florent Kermarrec <florent@enjoy-digital.fr>
Date: Sun, 3 May 2020 10:54:35 +0200
Subject: [PATCH 73/95] bios/cmd_mdio.c:  fix missing <base/mdio.h> import.

---
 litex/soc/software/bios/commands/cmd_mdio.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/litex/soc/software/bios/commands/cmd_mdio.c b/litex/soc/software/bios/commands/cmd_mdio.c
index 9d28c5347..35b020737 100644
--- a/litex/soc/software/bios/commands/cmd_mdio.c
+++ b/litex/soc/software/bios/commands/cmd_mdio.c
@@ -5,6 +5,8 @@
 
 #include <generated/csr.h>
 
+#include <base/mdio.h>
+
 #include "../command.h"
 #include "../helpers.h"
 

From 45377d9faa7722c9fb5c8efd9749ecb229d354d3 Mon Sep 17 00:00:00 2001
From: Florent Kermarrec <florent@enjoy-digital.fr>
Date: Sun, 3 May 2020 21:29:54 +0200
Subject: [PATCH 74/95] cpus: use a common definition of gcc_triple for the
 RISC-V CPUs, reorganize CPU by ISA/Data-Width.

---
 litex/soc/cores/cpu/__init__.py         | 62 ++++++++++++++++++-------
 litex/soc/cores/cpu/blackparrot/core.py |  5 +-
 litex/soc/cores/cpu/minerva/core.py     |  5 +-
 litex/soc/cores/cpu/picorv32/core.py    |  5 +-
 litex/soc/cores/cpu/rocket/core.py      |  5 +-
 litex/soc/cores/cpu/serv/core.py        |  5 +-
 litex/soc/cores/cpu/vexriscv/core.py    |  5 +-
 7 files changed, 56 insertions(+), 36 deletions(-)

diff --git a/litex/soc/cores/cpu/__init__.py b/litex/soc/cores/cpu/__init__.py
index 21f7ce5d5..bc1067123 100644
--- a/litex/soc/cores/cpu/__init__.py
+++ b/litex/soc/cores/cpu/__init__.py
@@ -29,46 +29,72 @@ class CPUNone(CPU):
     periph_buses         = []
     memory_buses         = []
 
+CPU_GCC_TRIPLE_RISCV32 = (
+    "riscv64-unknown-elf",
+    "riscv32-unknown-elf",
+    "riscv-none-embed",
+    "riscv64-linux",
+    "riscv-sifive-elf",
+    "riscv64-none-elf",
+)
+
+CPU_GCC_TRIPLE_RISCV64 = (
+    "riscv64-unknown-elf",
+    "riscv64-linux",
+    "riscv-sifive-elf",
+    "riscv64-none-elf",
+)
+
 # CPUS ---------------------------------------------------------------------------------------------
 
 from litex.soc.cores.cpu.lm32 import LM32
 from litex.soc.cores.cpu.mor1kx import MOR1KX
-from litex.soc.cores.cpu.picorv32 import PicoRV32
-from litex.soc.cores.cpu.vexriscv import VexRiscv
-from litex.soc.cores.cpu.minerva import Minerva
-from litex.soc.cores.cpu.rocket import RocketRV64
 from litex.soc.cores.cpu.microwatt import Microwatt
-from litex.soc.cores.cpu.blackparrot import BlackParrotRV64
 from litex.soc.cores.cpu.serv import SERV
+from litex.soc.cores.cpu.picorv32 import PicoRV32
+from litex.soc.cores.cpu.minerva import Minerva
+from litex.soc.cores.cpu.vexriscv import VexRiscv
+from litex.soc.cores.cpu.rocket import RocketRV64
+from litex.soc.cores.cpu.blackparrot import BlackParrotRV64
 
 CPUS = {
+    # None
     "None"        : CPUNone,
+
+    # LM32
     "lm32"        : LM32,
+
+    # OpenRisc
     "mor1kx"      : MOR1KX,
-    "picorv32"    : PicoRV32,
-    "vexriscv"    : VexRiscv,
-    "minerva"     : Minerva,
-    "rocket"      : RocketRV64,
+
+    # Open Power
     "microwatt"   : Microwatt,
+
+    # RISC-V 32-bit
+    "serv"        : SERV,
+    "picorv32"    : PicoRV32,
+    "minerva"     : Minerva,
+    "vexriscv"    : VexRiscv,
+
+    # RISC-V 64-bit
+    "rocket"      : RocketRV64,
     "blackparrot" : BlackParrotRV64,
-    "serv"        : SERV
 }
 
 # CPU Variants/Extensions Definition ---------------------------------------------------------------
 
 CPU_VARIANTS = {
     # "official name": ["alias 1", "alias 2"],
-    "minimal" : ["min",],
-    "lite" : ["light", "zephyr", "nuttx"],
-    "standard": [None, "std"],
-    "full": [],
-    "linux" : [],
-    "linuxd" : [],
-    "linuxq" : [],
+    "minimal" :   ["min",],
+    "lite" :      ["light", "zephyr", "nuttx"],
+    "standard":   [None, "std"],
+    "full":       [],
+    "linux" :     [],
+    "linuxd" :    [],
+    "linuxq" :    [],
 }
 CPU_VARIANTS_EXTENSIONS = ["debug", "no-dsp"]
 
-
 class InvalidCPUVariantError(ValueError):
     def __init__(self, variant):
         msg = """\
diff --git a/litex/soc/cores/cpu/blackparrot/core.py b/litex/soc/cores/cpu/blackparrot/core.py
index 302aa70dc..9f3d4fb7c 100644
--- a/litex/soc/cores/cpu/blackparrot/core.py
+++ b/litex/soc/cores/cpu/blackparrot/core.py
@@ -35,7 +35,7 @@ from migen import *
 from litex import get_data_mod
 from litex.soc.interconnect import axi
 from litex.soc.interconnect import wishbone
-from litex.soc.cores.cpu import CPU
+from litex.soc.cores.cpu import CPU, CPU_GCC_TRIPLE_RISCV64
 
 CPU_VARIANTS = {
     "standard": "freechips.rocketchip.system.LitexConfig",
@@ -50,8 +50,7 @@ class BlackParrotRV64(CPU):
     human_name           = "BlackParrotRV64[ia]"
     data_width           = 64
     endianness           = "little"
-    gcc_triple           = ("riscv64-unknown-elf", "riscv64-linux", "riscv-sifive-elf",
-                            "riscv64-none-elf")
+    gcc_triple           = CPU_GCC_TRIPLE_RISCV64
     linker_output_format = "elf64-littleriscv"
     nop                  = "nop"
     io_regions           = {0x50000000: 0x10000000} # origin, length
diff --git a/litex/soc/cores/cpu/minerva/core.py b/litex/soc/cores/cpu/minerva/core.py
index 2a6f21f9e..64cf86662 100644
--- a/litex/soc/cores/cpu/minerva/core.py
+++ b/litex/soc/cores/cpu/minerva/core.py
@@ -9,7 +9,7 @@ from migen import *
 
 from litex import get_data_mod
 from litex.soc.interconnect import wishbone
-from litex.soc.cores.cpu import CPU
+from litex.soc.cores.cpu import CPU, CPU_GCC_TRIPLE_RISCV32
 
 CPU_VARIANTS = ["standard"]
 
@@ -19,8 +19,7 @@ class Minerva(CPU):
     human_name           = "Minerva"
     data_width           = 32
     endianness           = "little"
-    gcc_triple           = ("riscv64-unknown-elf", "riscv32-unknown-elf", "riscv-none-embed",
-                            "riscv64-linux", "riscv-sifive-elf", "riscv64-none-elf")
+    gcc_triple           = CPU_GCC_TRIPLE_RISCV32
     linker_output_format = "elf32-littleriscv"
     nop                  = "nop"
     io_regions           = {0x80000000: 0x80000000} # origin, length
diff --git a/litex/soc/cores/cpu/picorv32/core.py b/litex/soc/cores/cpu/picorv32/core.py
index b3bfc0747..3f568db4b 100644
--- a/litex/soc/cores/cpu/picorv32/core.py
+++ b/litex/soc/cores/cpu/picorv32/core.py
@@ -13,7 +13,7 @@ from migen import *
 
 from litex import get_data_mod
 from litex.soc.interconnect import wishbone
-from litex.soc.cores.cpu import CPU
+from litex.soc.cores.cpu import CPU, CPU_GCC_TRIPLE_RISCV64
 
 
 CPU_VARIANTS = ["minimal", "standard"]
@@ -36,8 +36,7 @@ class PicoRV32(CPU):
     human_name           = "PicoRV32"
     data_width           = 32
     endianness           = "little"
-    gcc_triple           = ("riscv64-unknown-elf", "riscv32-unknown-elf", "riscv-none-embed",
-                            "riscv64-linux", "riscv-sifive-elf", "riscv64-none-elf")
+    gcc_triple           = CPU_GCC_TRIPLE_RISCV64
     linker_output_format = "elf32-littleriscv"
     nop                  = "nop"
     io_regions           = {0x80000000: 0x80000000} # origin, length
diff --git a/litex/soc/cores/cpu/rocket/core.py b/litex/soc/cores/cpu/rocket/core.py
index e0100c769..f08019fff 100644
--- a/litex/soc/cores/cpu/rocket/core.py
+++ b/litex/soc/cores/cpu/rocket/core.py
@@ -36,7 +36,7 @@ from migen import *
 from litex import get_data_mod
 from litex.soc.interconnect import axi
 from litex.soc.interconnect import wishbone
-from litex.soc.cores.cpu import CPU
+from litex.soc.cores.cpu import CPU, CPU_GCC_TRIPLE_RISCV64
 
 
 CPU_VARIANTS = {
@@ -69,8 +69,7 @@ class RocketRV64(CPU):
     human_name           = "RocketRV64[imac]"
     data_width           = 64
     endianness           = "little"
-    gcc_triple           = ("riscv64-unknown-elf", "riscv64-linux", "riscv-sifive-elf",
-                            "riscv64-none-elf")
+    gcc_triple           = CPU_GCC_TRIPLE_RISCV64
     linker_output_format = "elf64-littleriscv"
     nop                  = "nop"
     io_regions           = {0x10000000: 0x70000000} # origin, length
diff --git a/litex/soc/cores/cpu/serv/core.py b/litex/soc/cores/cpu/serv/core.py
index dbb6a1b40..739b83b6b 100644
--- a/litex/soc/cores/cpu/serv/core.py
+++ b/litex/soc/cores/cpu/serv/core.py
@@ -8,7 +8,7 @@ from migen import *
 
 from litex import get_data_mod
 from litex.soc.interconnect import wishbone
-from litex.soc.cores.cpu import CPU
+from litex.soc.cores.cpu import CPU, CPU_GCC_TRIPLE_RISCV32
 
 
 CPU_VARIANTS = ["standard"]
@@ -19,8 +19,7 @@ class SERV(CPU):
     human_name           = "SERV"
     data_width           = 32
     endianness           = "little"
-    gcc_triple           = ("riscv64-unknown-elf", "riscv32-unknown-elf", "riscv-none-embed",
-                            "riscv64-linux", "riscv-sifive-elf", "riscv64-none-elf")
+    gcc_triple           = CPU_GCC_TRIPLE_RISCV32
     linker_output_format = "elf32-littleriscv"
     nop                  = "nop"
     io_regions           = {0x80000000: 0x80000000} # origin, length
diff --git a/litex/soc/cores/cpu/vexriscv/core.py b/litex/soc/cores/cpu/vexriscv/core.py
index 45fc0df9d..dc267ce98 100644
--- a/litex/soc/cores/cpu/vexriscv/core.py
+++ b/litex/soc/cores/cpu/vexriscv/core.py
@@ -15,7 +15,7 @@ from migen import *
 from litex import get_data_mod
 from litex.soc.interconnect import wishbone
 from litex.soc.interconnect.csr import *
-from litex.soc.cores.cpu import CPU
+from litex.soc.cores.cpu import CPU, CPU_GCC_TRIPLE_RISCV32
 
 
 CPU_VARIANTS = {
@@ -79,8 +79,7 @@ class VexRiscv(CPU, AutoCSR):
     human_name           = "VexRiscv"
     data_width           = 32
     endianness           = "little"
-    gcc_triple           = ("riscv64-unknown-elf", "riscv32-unknown-elf", "riscv-none-embed",
-                            "riscv64-linux", "riscv-sifive-elf", "riscv64-none-elf")
+    gcc_triple           = CPU_GCC_TRIPLE_RISCV32
     linker_output_format = "elf32-littleriscv"
     nop                  = "nop"
     io_regions           = {0x80000000: 0x80000000} # origin, length

From c06a1279090c504b04f3293fce20e29305f67f6f Mon Sep 17 00:00:00 2001
From: Florent Kermarrec <florent@enjoy-digital.fr>
Date: Mon, 4 May 2020 08:46:25 +0200
Subject: [PATCH 75/95] cpu/microwatt: add pythondata and fix build with it.

---
 litex/soc/cores/cpu/microwatt/core.py | 6 ++----
 litex_setup.py                        | 1 +
 2 files changed, 3 insertions(+), 4 deletions(-)

diff --git a/litex/soc/cores/cpu/microwatt/core.py b/litex/soc/cores/cpu/microwatt/core.py
index 76eb59dc7..603a950d2 100644
--- a/litex/soc/cores/cpu/microwatt/core.py
+++ b/litex/soc/cores/cpu/microwatt/core.py
@@ -102,9 +102,7 @@ class Microwatt(CPU):
 
     @staticmethod
     def add_sources(platform):
-        sdir = os.path.join(
-            get_data_mod("cpu", "microwatt").data_location,
-            "sources")
+        sdir = get_data_mod("cpu", "microwatt").data_location
         platform.add_sources(sdir,
             # Common / Types / Helpers
             "decode_types.vhdl",
@@ -157,7 +155,7 @@ class Microwatt(CPU):
             "core_debug.vhdl",
             "core.vhdl",
         )
-        platform.add_source(os.path.join(sdir, "..", "microwatt_wrapper.vhdl"))
+        platform.add_source(os.path.join(os.path.dirname(__file__), "microwatt_wrapper.vhdl"))
 
     def do_finalize(self):
         self.specials += Instance("microwatt_wrapper", **self.cpu_params)
diff --git a/litex_setup.py b/litex_setup.py
index f6d6b3937..287cc076a 100755
--- a/litex_setup.py
+++ b/litex_setup.py
@@ -47,6 +47,7 @@ repos = [
     ("pythondata-cpu-vexriscv",    ("https://github.com/litex-hub/", False, True)),
     ("pythondata-cpu-rocket",      ("https://github.com/litex-hub/", False, True)),
     ("pythondata-cpu-minerva",     ("https://github.com/litex-hub/", False, True)),
+    ("pythondata-cpu-microwatt",   ("https://github.com/litex-hub/", False, True)),
 ]
 
 repos = OrderedDict(repos)

From 2112703181fd512c1776766de17383ab0bdcbee8 Mon Sep 17 00:00:00 2001
From: Florent Kermarrec <florent@enjoy-digital.fr>
Date: Mon, 4 May 2020 08:51:38 +0200
Subject: [PATCH 76/95] cpu/microwatt: add powerpc64le-linux-gnu to gcc_triple.

It seems to be what most distros cross-comiplers are using.
---
 litex/soc/cores/cpu/microwatt/core.py | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/litex/soc/cores/cpu/microwatt/core.py b/litex/soc/cores/cpu/microwatt/core.py
index 603a950d2..ca4aae2bc 100644
--- a/litex/soc/cores/cpu/microwatt/core.py
+++ b/litex/soc/cores/cpu/microwatt/core.py
@@ -19,7 +19,7 @@ class Microwatt(CPU):
     human_name           = "Microwatt"
     data_width           = 64
     endianness           = "little"
-    gcc_triple           = ("powerpc64le-linux")
+    gcc_triple           = ("powerpc64le-linux", "powerpc64le-linux-gnu")
     linker_output_format = "elf64-powerpcle"
     nop                  = "nop"
     io_regions           = {0xc0000000: 0x10000000} # origin, length

From 07e0153bb19c62cbdee6a193e02fc619bc88bc23 Mon Sep 17 00:00:00 2001
From: Florent Kermarrec <florent@enjoy-digital.fr>
Date: Mon, 4 May 2020 09:59:01 +0200
Subject: [PATCH 77/95] CHANGES: update.

---
 CHANGES | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/CHANGES b/CHANGES
index 64bd257e0..f4b28cd8a 100644
--- a/CHANGES
+++ b/CHANGES
@@ -3,10 +3,11 @@
 
 	[> Issues resolved
 	------------------
-	- NA
+	- Fix flush_cpu_icache on VexRiscv.
 
 	[> Added Features
 	------------------
+	- BIOS history, autocomplete.
 	- Pluggable CPUs.
 	- Add nMigen dependency.
 	- Properly integrate Minerva CPU.

From ee413527ac080a53837664fd54dc31987933d10e Mon Sep 17 00:00:00 2001
From: shuffle2 <godisgovernment@gmail.com>
Date: Mon, 4 May 2020 01:10:09 -0700
Subject: [PATCH 78/95] diamond: quiet warning about missing clkin freq for
 EHXPLLL

FREQUENCY_PIN_CLKI should be given in mhz
---
 litex/soc/cores/clock.py | 1 +
 1 file changed, 1 insertion(+)

diff --git a/litex/soc/cores/clock.py b/litex/soc/cores/clock.py
index 97f83c7ba..321768e6c 100644
--- a/litex/soc/cores/clock.py
+++ b/litex/soc/cores/clock.py
@@ -676,6 +676,7 @@ class ECP5PLL(Module):
         clkfb  = Signal()
         self.params.update(
             attr=[
+                ("FREQUENCY_PIN_CLKI",     str(self.clkin_freq/1e6)),
                 ("ICP_CURRENT",            "6"),
                 ("LPF_RESISTOR",          "16"),
                 ("MFG_ENABLE_FILTEROPAMP", "1"),

From edfed4f068fdf87407e5addf53f900bb95ff94be Mon Sep 17 00:00:00 2001
From: Gabriel Somlo <gsomlo@gmail.com>
Date: Mon, 4 May 2020 09:13:32 -0400
Subject: [PATCH 79/95] software/*/Makefile: no need to copy .S files from CPU
 directory

Signed-off-by: Gabriel Somlo <gsomlo@gmail.com>
---
 litex/soc/software/bios/Makefile    | 1 -
 litex/soc/software/libbase/Makefile | 2 --
 2 files changed, 3 deletions(-)

diff --git a/litex/soc/software/bios/Makefile b/litex/soc/software/bios/Makefile
index e792ff633..0369522e6 100755
--- a/litex/soc/software/bios/Makefile
+++ b/litex/soc/software/bios/Makefile
@@ -88,7 +88,6 @@ endif
 	$(assemble)
 
 boot-helper.o: $(CPU_DIRECTORY)/boot-helper.S
-	cp $(CPU_DIRECTORY)/boot-helper.S $(BIOS_DIRECTORY)/boot-helper.S
 	$(assemble)
 
 clean:
diff --git a/litex/soc/software/libbase/Makefile b/litex/soc/software/libbase/Makefile
index e81a5316e..13680ad0e 100755
--- a/litex/soc/software/libbase/Makefile
+++ b/litex/soc/software/libbase/Makefile
@@ -25,11 +25,9 @@ vsnprintf-nofloat.o: $(LIBBASE_DIRECTORY)/vsnprintf.c
 	$(assemble)
 
 crt0-ctr.o: $(CPU_DIRECTORY)/crt0.S
-	cp $(CPU_DIRECTORY)/crt0.S $(LIBBASE_DIRECTORY)/crt0-crt.S
 	$(assemble)
 
 crt0-xip.o: $(CPU_DIRECTORY)/crt0.S
-	cp $(CPU_DIRECTORY)/crt0.S $(LIBBASE_DIRECTORY)/crt0-xip.S
 	$(CC) -c -DEXECUTE_IN_PLACE $(CFLAGS) -o $@ $<
 
 .PHONY: all clean

From 9bef218ad6616d4d8b958e34de1f6e87b7cbdd99 Mon Sep 17 00:00:00 2001
From: Florent Kermarrec <florent@enjoy-digital.fr>
Date: Mon, 4 May 2020 17:30:12 +0200
Subject: [PATCH 80/95] cpu/microwatt: fix integration/crt0.S (thanks Benjamin
 Herrenschmidt).

Tested on Arty A7:

        __   _ __      _  __
       / /  (_) /____ | |/_/
      / /__/ / __/ -_)>  <
     /____/_/\__/\__/_/|_|
   Build your hardware, easily!

 (c) Copyright 2012-2020 Enjoy-Digital
 (c) Copyright 2007-2015 M-Labs

 BIOS built on May  4 2020 17:15:13
 BIOS CRC passed (0adc4193)

 Migen git sha1: 5b5e4fd
 LiteX git sha1: 6f24d46d

--=============== SoC ==================--
CPU:       Microwatt @ 100MHz
ROM:       32KB
SRAM:      4KB
L2:        8KB
MAIN-RAM:  262144KB

--========== Initialization ============--
Initializing SDRAM...
SDRAM now under software control
Read leveling:
m0, b0: |00000000000000000000000000000000| delays: -
m0, b1: |00000000000000000000000000000000| delays: -
m0, b2: |00000000000000000000000000000000| delays: -
m0, b3: |00000000000000000000000000000000| delays: -
m0, b4: |00000000000000000000000000000000| delays: -
m0, b5: |00000000000000000000000000000000| delays: -
m0, b6: |00000111111111111100000000000000| delays: 11+-06
m0, b7: |00000000000000000000000000000000| delays: -
best: m0, b6 delays: 11+-06
m1, b0: |00000000000000000000000000000000| delays: -
m1, b1: |00000000000000000000000000000000| delays: -
m1, b2: |00000000000000000000000000000000| delays: -
m1, b3: |00000000000000000000000000000000| delays: -
m1, b4: |00000000000000000000000000000000| delays: -
m1, b5: |10000000000000000000000000000000| delays: 00+-00
m1, b6: |00000011111111111100000000000000| delays: 12+-06
m1, b7: |00000000000000000000000000000000| delays: -
best: m1, b6 delays: 12+-06
SDRAM now under hardware control
Memtest OK
Memspeed Writes: 129Mbps Reads: 215Mbps

--============== Boot ==================--
Booting from serial...
Press Q or ESC to abort boot completely.
sL5DdSMmkekro
Timeout
No boot medium found

--============= Console ================--

litex>
---
 litex/soc/cores/cpu/microwatt/core.py |  8 ++++----
 litex/soc/cores/cpu/microwatt/crt0.S  | 13 ++-----------
 2 files changed, 6 insertions(+), 15 deletions(-)

diff --git a/litex/soc/cores/cpu/microwatt/core.py b/litex/soc/cores/cpu/microwatt/core.py
index ca4aae2bc..81802f345 100644
--- a/litex/soc/cores/cpu/microwatt/core.py
+++ b/litex/soc/cores/cpu/microwatt/core.py
@@ -47,8 +47,8 @@ class Microwatt(CPU):
         self.platform     = platform
         self.variant      = variant
         self.reset        = Signal()
-        self.wb_insn      = wb_insn = wishbone.Interface(data_width=64, adr_width=28)
-        self.wb_data      = wb_data = wishbone.Interface(data_width=64, adr_width=28)
+        self.wb_insn      = wb_insn = wishbone.Interface(data_width=64, adr_width=29)
+        self.wb_data      = wb_data = wishbone.Interface(data_width=64, adr_width=29)
         self.periph_buses = [wb_insn, wb_data]
         self.memory_buses = []
 
@@ -64,7 +64,7 @@ class Microwatt(CPU):
             i_wishbone_insn_ack   = wb_insn.ack,
             i_wishbone_insn_stall = wb_insn.cyc & ~wb_insn.ack, # No burst support
 
-            o_wishbone_insn_adr   = Cat(Signal(4), wb_insn.adr),
+            o_wishbone_insn_adr   = Cat(Signal(3), wb_insn.adr),
             o_wishbone_insn_dat_w = wb_insn.dat_w,
             o_wishbone_insn_cyc   = wb_insn.cyc,
             o_wishbone_insn_stb   = wb_insn.stb,
@@ -76,7 +76,7 @@ class Microwatt(CPU):
             i_wishbone_data_ack   = wb_data.ack,
             i_wishbone_data_stall = wb_data.cyc & ~wb_data.ack, # No burst support
 
-            o_wishbone_data_adr   = Cat(Signal(4), wb_data.adr),
+            o_wishbone_data_adr   = Cat(Signal(3), wb_data.adr),
             o_wishbone_data_dat_w = wb_data.dat_w,
             o_wishbone_data_cyc   = wb_data.cyc,
             o_wishbone_data_stb   = wb_data.stb,
diff --git a/litex/soc/cores/cpu/microwatt/crt0.S b/litex/soc/cores/cpu/microwatt/crt0.S
index 0dd6f343b..e03ac0bb4 100644
--- a/litex/soc/cores/cpu/microwatt/crt0.S
+++ b/litex/soc/cores/cpu/microwatt/crt0.S
@@ -14,8 +14,6 @@
  * limitations under the License.
  */
 
-#define STACK_TOP	0xffff4000
-
 #define FIXUP_ENDIAN						   \
 	tdi   0,0,0x48;	  /* Reverse endian of b . + 8		*/ \
 	b     191f;	  /* Skip trampoline if endian is good	*/ \
@@ -38,24 +36,17 @@
 	oris    r,r, (e)@h;			\
 	ori     r,r, (e)@l;
 
-	.section ".head","ax"
-
 	. = 0
 .global _start
 _start:
 	FIXUP_ENDIAN
 
 	/* setup stack */
-	LOAD_IMM64(%r1, STACK_TOP - 0x100)
+	LOAD_IMM64(%r1, _fstack - 0x100)
 	LOAD_IMM64(%r12, main)
 	mtctr	%r12,
 	bctrl
-	ba	0
-
-	/* XXX: litedram init should not take exceptions, maybe we could get
-	 *      rid of these to save space, along with a core tweak to suppress
-	 *      exceptions in case they happen (just terminate ?)
-	 */
+	b .
 
 #define EXCEPTION(nr)		\
 	.=  nr;      \

From b8f9f83a8fb0a9280dadde45ea9ac8d2ae53bb43 Mon Sep 17 00:00:00 2001
From: Florent Kermarrec <florent@enjoy-digital.fr>
Date: Tue, 5 May 2020 09:56:13 +0200
Subject: [PATCH 81/95] build/openocd: add find_config method to allow using
 local config file or download it if not available locally.

---
 litex/build/generic_programmer.py | 34 +++++++++++++++++++++++++++----
 litex/build/openocd.py            |  6 ++++--
 2 files changed, 34 insertions(+), 6 deletions(-)

diff --git a/litex/build/generic_programmer.py b/litex/build/generic_programmer.py
index 394440300..2927d8298 100644
--- a/litex/build/generic_programmer.py
+++ b/litex/build/generic_programmer.py
@@ -20,7 +20,10 @@ class GenericProgrammer:
         self.flash_proxy_repos = [
             "https://github.com/quartiq/bscan_spi_bitstreams/raw/master/",
         ]
-        self.flash_proxy_local = "flash_proxies"
+        self.config_repos = [
+            "https://raw.githubusercontent.com/litex-hub/litex-boards/master/litex_boards/prog/",
+        ]
+        self.prog_local = "prog"
 
     def set_flash_proxy_dir(self, flash_proxy_dir):
         if flash_proxy_dir is not None:
@@ -34,14 +37,14 @@ class GenericProgrammer:
             if os.path.exists(fullname):
                 return fullname
         # Search in local flash_proxy directory
-        fullname = tools.cygpath(os.path.join(self.flash_proxy_local, self.flash_proxy_basename))
+        fullname = tools.cygpath(os.path.join(self.prog_local, self.flash_proxy_basename))
         if os.path.exists(fullname):
             return fullname
         # Search in repositories and download it
         import requests
-        os.makedirs(self.flash_proxy_local, exist_ok=True)
+        os.makedirs(self.prog_local, exist_ok=True)
         for d in self.flash_proxy_repos:
-            fullname = tools.cygpath(os.path.join(self.flash_proxy_local, self.flash_proxy_basename))
+            fullname = tools.cygpath(os.path.join(self.prog_local, self.flash_proxy_basename))
             try:
                 r = requests.get(d + self.flash_proxy_basename)
                 with open(fullname, "wb") as f:
@@ -51,6 +54,29 @@ class GenericProgrammer:
                 pass
         raise OSError("Failed to find flash proxy bitstream")
 
+    def find_config(self):
+        # Search in local directory
+        fullname = tools.cygpath(self.config)
+        if os.path.exists(fullname):
+            return self.config
+        # Search in local config directory
+        fullname = tools.cygpath(os.path.join(self.prog_local, self.config))
+        if os.path.exists(fullname):
+            return fullname
+        # Search in repositories and download it
+        import requests
+        os.makedirs(self.prog_local, exist_ok=True)
+        for d in self.config_repos:
+            fullname = tools.cygpath(os.path.join(self.prog_local, self.config))
+            try:
+                r = requests.get(d + self.config)
+                with open(fullname, "wb") as f:
+                    f.write(r.content)
+                return fullname
+            except:
+                pass
+        raise OSError("Failed to find config file")
+
     # Must be overloaded by specific programmer
     def load_bitstream(self, bitstream_file):
         raise NotImplementedError
diff --git a/litex/build/openocd.py b/litex/build/openocd.py
index c149ca2cc..d3680d609 100644
--- a/litex/build/openocd.py
+++ b/litex/build/openocd.py
@@ -17,14 +17,16 @@ class OpenOCD(GenericProgrammer):
         self.config = config
 
     def load_bitstream(self, bitstream):
+        config = self.find_config()
         script = "; ".join([
             "init",
             "pld load 0 {{{}}}".format(bitstream),
             "exit",
         ])
-        subprocess.call(["openocd", "-f", self.config, "-c", script])
+        subprocess.call(["openocd", "-f", config, "-c", script])
 
     def flash(self, address, data, set_qe=False):
+        config      = self.find_config()
         flash_proxy = self.find_flash_proxy()
         script = "; ".join([
             "init",
@@ -34,7 +36,7 @@ class OpenOCD(GenericProgrammer):
             "fpga_program",
             "exit"
         ])
-        subprocess.call(["openocd", "-f", self.config, "-c", script])
+        subprocess.call(["openocd", "-f", config, "-c", script])
 
 
     def stream(self, port=20000):

From d0b8daa005c332b97e3014576b4e6aabfaeccef1 Mon Sep 17 00:00:00 2001
From: Florent Kermarrec <florent@enjoy-digital.fr>
Date: Tue, 5 May 2020 11:23:46 +0200
Subject: [PATCH 82/95] build/platform: allow doing a loose lookup_request
 (return None instead of ConstraintError) and allow subname in lookup_request.

In the platforms, insead of doing:
self.lookup_request("eth_clocks").rx
we can now do:
self.lookup_request("eth_clocks:rx")

This allows some try/except simplifications on constraints.
---
 litex/build/altera/platform.py    |  1 +
 litex/build/generic_platform.py   | 14 +++++++++++---
 litex/build/lattice/platform.py   |  1 +
 litex/build/microsemi/platform.py |  1 +
 litex/build/xilinx/platform.py    |  1 +
 5 files changed, 15 insertions(+), 3 deletions(-)

diff --git a/litex/build/altera/platform.py b/litex/build/altera/platform.py
index a95dcf4b9..2f03fc720 100644
--- a/litex/build/altera/platform.py
+++ b/litex/build/altera/platform.py
@@ -33,6 +33,7 @@ class AlteraPlatform(GenericPlatform):
         return self.toolchain.build(self, *args, **kwargs)
 
     def add_period_constraint(self, clk, period):
+        if clk is None: return
         if hasattr(clk, "p"):
             clk = clk.p
         self.toolchain.add_period_constraint(self, clk, period)
diff --git a/litex/build/generic_platform.py b/litex/build/generic_platform.py
index d540cc38a..7c489efea 100644
--- a/litex/build/generic_platform.py
+++ b/litex/build/generic_platform.py
@@ -205,13 +205,21 @@ class ConstraintManager:
         self.matched.append((resource, obj))
         return obj
 
-    def lookup_request(self, name, number=None):
+    def lookup_request(self, name, number=None, loose=False):
+        subname = None
+        if ":" in name: name, subname = name.split(":")
         for resource, obj in self.matched:
             if resource[0] == name and (number is None or
                                         resource[1] == number):
-                return obj
+                if subname is not None:
+                    return getattr(obj, subname)
+                else:
+                    return obj
 
-        raise ConstraintError("Resource not found: {}:{}".format(name, number))
+        if loose:
+            return None
+        else:
+            raise ConstraintError("Resource not found: {}:{}".format(name, number))
 
     def add_platform_command(self, command, **signals):
         self.platform_commands.append((command, signals))
diff --git a/litex/build/lattice/platform.py b/litex/build/lattice/platform.py
index 71ff2a653..7380b45e0 100644
--- a/litex/build/lattice/platform.py
+++ b/litex/build/lattice/platform.py
@@ -34,6 +34,7 @@ class LatticePlatform(GenericPlatform):
         return self.toolchain.build(self, *args, **kwargs)
 
     def add_period_constraint(self, clk, period):
+        if clk is None: return
         if hasattr(clk, "p"):
             clk = clk.p
         self.toolchain.add_period_constraint(self, clk, period)
diff --git a/litex/build/microsemi/platform.py b/litex/build/microsemi/platform.py
index 65d2c996d..c8f13bd89 100644
--- a/litex/build/microsemi/platform.py
+++ b/litex/build/microsemi/platform.py
@@ -28,6 +28,7 @@ class MicrosemiPlatform(GenericPlatform):
         return self.toolchain.build(self, *args, **kwargs)
 
     def add_period_constraint(self, clk, period):
+        if clk is None: return
         clk.attr.add("keep")
         if hasattr(clk, "p"):
             clk = clk.p
diff --git a/litex/build/xilinx/platform.py b/litex/build/xilinx/platform.py
index cf7bbeb50..d5e3d8f85 100644
--- a/litex/build/xilinx/platform.py
+++ b/litex/build/xilinx/platform.py
@@ -48,6 +48,7 @@ class XilinxPlatform(GenericPlatform):
         return self.toolchain.build(self, *args, **kwargs)
 
     def add_period_constraint(self, clk, period):
+        if clk is None: return
         if hasattr(clk, "p"):
             clk = clk.p
         self.toolchain.add_period_constraint(self, clk, period)

From 9a7f9cb87beb310b1cc2202184bb4af2de4888df Mon Sep 17 00:00:00 2001
From: Florent Kermarrec <florent@enjoy-digital.fr>
Date: Tue, 5 May 2020 12:16:29 +0200
Subject: [PATCH 83/95] build/generic_programmer: catch 404 not found when
 downloading config/proxy.

---
 litex/build/generic_programmer.py | 14 ++++++++------
 1 file changed, 8 insertions(+), 6 deletions(-)

diff --git a/litex/build/generic_programmer.py b/litex/build/generic_programmer.py
index 2927d8298..cb0597d1d 100644
--- a/litex/build/generic_programmer.py
+++ b/litex/build/generic_programmer.py
@@ -47,9 +47,10 @@ class GenericProgrammer:
             fullname = tools.cygpath(os.path.join(self.prog_local, self.flash_proxy_basename))
             try:
                 r = requests.get(d + self.flash_proxy_basename)
-                with open(fullname, "wb") as f:
-                    f.write(r.content)
-                return fullname
+                if r.status_code != 404:
+                    with open(fullname, "wb") as f:
+                        f.write(r.content)
+                    return fullname
             except:
                 pass
         raise OSError("Failed to find flash proxy bitstream")
@@ -70,9 +71,10 @@ class GenericProgrammer:
             fullname = tools.cygpath(os.path.join(self.prog_local, self.config))
             try:
                 r = requests.get(d + self.config)
-                with open(fullname, "wb") as f:
-                    f.write(r.content)
-                return fullname
+                if r.status_code != 404:
+                    with open(fullname, "wb") as f:
+                        f.write(r.content)
+                    return fullname
             except:
                 pass
         raise OSError("Failed to find config file")

From 85ac5ef1333d93049c0b1c98197738c34b66d5f3 Mon Sep 17 00:00:00 2001
From: Florent Kermarrec <florent@enjoy-digital.fr>
Date: Tue, 5 May 2020 12:17:12 +0200
Subject: [PATCH 84/95] build/lattice/programmer: make OpenOCDJTAGProgrammer
 closer to OpenOCD programmer.

---
 litex/build/lattice/programmer.py | 21 +++++++++------------
 1 file changed, 9 insertions(+), 12 deletions(-)

diff --git a/litex/build/lattice/programmer.py b/litex/build/lattice/programmer.py
index 0095c147f..e3d7a963d 100644
--- a/litex/build/lattice/programmer.py
+++ b/litex/build/lattice/programmer.py
@@ -25,34 +25,31 @@ class LatticeProgrammer(GenericProgrammer):
 # OpenOCDJTAGProgrammer --------------------------------------------------------------------------------
 
 class OpenOCDJTAGProgrammer(GenericProgrammer):
-    def __init__(self, openocd_config, flash_proxy_basename=None):
-        GenericProgrammer.__init__(self, flash_proxy_basename=flash_proxy_basename)
-        self.openocd_config = openocd_config
+    def __init__(self, config, flash_proxy_basename=None):
+        GenericProgrammer.__init__(self, flash_proxy_basename)
+        self.config = config
 
     def load_bitstream(self, bitstream_file):
+        config   = self.find_config()
         svf_file = bitstream_file.replace(".bit", ".svf")
-
-        subprocess.call(["openocd", "-f", self.openocd_config , "-c", "transport select jtag; init; svf quiet progress \"{}\"; exit".format(svf_file)])
+        subprocess.call(["openocd", "-f", config, "-c", "transport select jtag; init; svf quiet progress \"{}\"; exit".format(svf_file)])
 
     def flash(self, address, data, verify=True):
-        if self.flash_proxy_basename is None:
-            flash_proxy = None
-        else:
-            flash_proxy = self.find_flash_proxy()
-
+        config      = self.find_config()
+        flash_proxy = self.find_flash_proxy()
         script = "; ".join([
             "transport select jtag",
             "target create ecp5.spi0.proxy testee -chain-position ecp5.tap",
             "flash bank spi0 jtagspi 0 0 0 0 ecp5.spi0.proxy 0x32",
             "init",
-            "svf quiet progress \"{}\"".format(flash_proxy) if flash_proxy is not None else "",
+            "svf quiet progress \"{}\"".format(flash_proxy),
             "reset halt",
             "flash probe spi0",
             "flash write_image erase \"{0}\" 0x{1:x}".format(data, address),
             "flash verify_bank spi0 \"{0}\" 0x{1:x}" if verify else "".format(data, address),
             "exit"
         ])
-        subprocess.call(["openocd", "-f", self.openocd_config, "-c", script])
+        subprocess.call(["openocd", "-f", config, "-c", script])
 
 # IceStormProgrammer -------------------------------------------------------------------------------
 

From 28f85c74038cdb8d78e5e0e0ed91a4655382f7da Mon Sep 17 00:00:00 2001
From: Florent Kermarrec <florent@enjoy-digital.fr>
Date: Tue, 5 May 2020 13:31:58 +0200
Subject: [PATCH 85/95] build/lattice/programmer: add UJProg (for ULX3S).

---
 litex/build/lattice/programmer.py | 8 ++++++++
 1 file changed, 8 insertions(+)

diff --git a/litex/build/lattice/programmer.py b/litex/build/lattice/programmer.py
index e3d7a963d..96204e189 100644
--- a/litex/build/lattice/programmer.py
+++ b/litex/build/lattice/programmer.py
@@ -130,3 +130,11 @@ class MyStormProgrammer(GenericProgrammer):
         with serial.Serial(self.serial_port) as port:
             with open(bitstream_file, "rb") as f:
                 port.write(f.read())
+
+# UJProg -------------------------------------------------------------------------------------------
+
+class UJProg(GenericProgrammer):
+    needs_bitreverse = False
+
+    def load_bitstream(self, bitstream_file):
+        subprocess.call(["ujprog", bitstream_file])

From 22bcbec03aa82bce6ca1059443f500649dd74c82 Mon Sep 17 00:00:00 2001
From: Florent Kermarrec <florent@enjoy-digital.fr>
Date: Tue, 5 May 2020 15:27:56 +0200
Subject: [PATCH 86/95] boards: keep in sync with LiteX-Boards, integrate
 improvements.

- create_programmer on all platforms.
- input clocks automatically constrainted.
- build/load parameters.
---
 litex/boards/platforms/arty.py         | 10 +++++--
 litex/boards/platforms/avalanche.py    |  5 ++++
 litex/boards/platforms/de0nano.py      |  4 +++
 litex/boards/platforms/genesys2.py     |  9 +++----
 litex/boards/platforms/icebreaker.py   |  4 +++
 litex/boards/platforms/kc705.py        | 20 +++++---------
 litex/boards/platforms/kcu105.py       |  2 ++
 litex/boards/platforms/machxo3.py      |  4 +++
 litex/boards/platforms/minispartan6.py |  9 +++++--
 litex/boards/platforms/netv2.py        | 12 ++++++++-
 litex/boards/platforms/nexys4ddr.py    |  8 +++++-
 litex/boards/platforms/nexys_video.py  |  9 +++++--
 litex/boards/platforms/tinyfpga_bx.py  |  4 +++
 litex/boards/platforms/ulx3s.py        | 15 +++++++++++
 litex/boards/platforms/versa_ecp5.py   | 16 +++++-------
 litex/boards/targets/arty.py           | 14 +++++++---
 litex/boards/targets/de0nano.py        |  9 +++++--
 litex/boards/targets/genesys2.py       |  8 +++++-
 litex/boards/targets/icebreaker.py     | 19 +++++++++-----
 litex/boards/targets/kc705.py          | 11 +++++---
 litex/boards/targets/kcu105.py         | 11 +++++---
 litex/boards/targets/minispartan6.py   |  8 +++++-
 litex/boards/targets/netv2.py          | 14 ++++++----
 litex/boards/targets/nexys4ddr.py      | 20 +++++++-------
 litex/boards/targets/nexys_video.py    | 11 +++++---
 litex/boards/targets/simple.py         | 13 +++++-----
 litex/boards/targets/ulx3s.py          | 36 +++++++++++++++++---------
 litex/boards/targets/versa_ecp5.py     | 19 ++++++++------
 28 files changed, 224 insertions(+), 100 deletions(-)

diff --git a/litex/boards/platforms/arty.py b/litex/boards/platforms/arty.py
index 1e2d8743e..712cd9aba 100644
--- a/litex/boards/platforms/arty.py
+++ b/litex/boards/platforms/arty.py
@@ -3,7 +3,8 @@
 # License: BSD
 
 from litex.build.generic_platform import *
-from litex.build.xilinx import XilinxPlatform, VivadoProgrammer
+from litex.build.xilinx import XilinxPlatform
+from litex.build.openocd import OpenOCD
 
 # IOs ----------------------------------------------------------------------------------------------
 
@@ -257,4 +258,9 @@ class Platform(XilinxPlatform):
         self.add_platform_command("set_property INTERNAL_VREF 0.675 [get_iobanks 34]")
 
     def create_programmer(self):
-        return VivadoProgrammer(flash_part="n25q128-3.3v-spi-x1_x2_x4")
+        bscan_spi = "bscan_spi_xc7a100t.bit" if "xc7a100t" in self.device else "bscan_spi_xc7a35t.bit"
+        return OpenOCD("openocd_xilinx_xc7.cfg", bscan_spi)
+
+    def do_finalize(self, fragment):
+        XilinxPlatform.do_finalize(self, fragment)
+        self.add_period_constraint(self.lookup_request("clk100", loose=True), 1e9/100e6)
diff --git a/litex/boards/platforms/avalanche.py b/litex/boards/platforms/avalanche.py
index 5de18cde7..ac5f568b3 100644
--- a/litex/boards/platforms/avalanche.py
+++ b/litex/boards/platforms/avalanche.py
@@ -92,3 +92,8 @@ class Platform(MicrosemiPlatform):
 
     def __init__(self):
         MicrosemiPlatform.__init__(self, "MPF300TS_ES-FCG484-1", _io)
+
+    def do_finalize(self, fragment):
+        MicrosemiPlatform.do_finalize(self, fragment)
+        self.add_period_constraint(self.lookup_request("clk50", 0, loose=True), 1e9/50e6)
+        self.add_period_constraint(self.lookup_request("clk50", 1, loose=True), 1e9/50e6)
diff --git a/litex/boards/platforms/de0nano.py b/litex/boards/platforms/de0nano.py
index 042a543e5..819a47eb3 100644
--- a/litex/boards/platforms/de0nano.py
+++ b/litex/boards/platforms/de0nano.py
@@ -114,3 +114,7 @@ class Platform(AlteraPlatform):
 
     def create_programmer(self):
         return USBBlaster()
+
+    def do_finalize(self, fragment):
+        AlteraPlatform.do_finalize(self, fragment)
+        self.add_period_constraint(self.lookup_request("clk50", loose=True), 1e9/50e6)
diff --git a/litex/boards/platforms/genesys2.py b/litex/boards/platforms/genesys2.py
index 523aa92b9..7e5ebc43c 100644
--- a/litex/boards/platforms/genesys2.py
+++ b/litex/boards/platforms/genesys2.py
@@ -3,6 +3,7 @@
 
 from litex.build.generic_platform import *
 from litex.build.xilinx import XilinxPlatform, VivadoProgrammer
+from litex.build.openocd import OpenOCD
 
 # IOs ----------------------------------------------------------------------------------------------
 
@@ -116,11 +117,9 @@ class Platform(XilinxPlatform):
         XilinxPlatform.__init__(self, "xc7k325t-ffg900-2", _io, _connectors, toolchain="vivado")
 
     def create_programmer(self):
-        return VivadoProgrammer()
+        return OpenOCD("openocd_xilinx_xc7.cfg", "bscan_spi_xc7a325t.bit")
 
     def do_finalize(self, fragment):
         XilinxPlatform.do_finalize(self, fragment)
-        try:
-            self.add_period_constraint(self.lookup_request("eth_clocks").rx, 1e9/125e6)
-        except ConstraintError:
-            pass
+        self.add_period_constraint(self.lookup_request("clk200",        loose=True), 1e9/200e6)
+        self.add_period_constraint(self.lookup_request("eth_clocks:rx", loose=True), 1e9/125e6)
diff --git a/litex/boards/platforms/icebreaker.py b/litex/boards/platforms/icebreaker.py
index a46651ef3..1525ba6be 100644
--- a/litex/boards/platforms/icebreaker.py
+++ b/litex/boards/platforms/icebreaker.py
@@ -86,3 +86,7 @@ class Platform(LatticePlatform):
 
     def create_programmer(self):
         return IceStormProgrammer()
+
+    def do_finalize(self, fragment):
+        LatticePlatform.do_finalize(self, fragment)
+        self.add_period_constraint(self.lookup_request("clk12", loose=True), 1e9/12e6)
diff --git a/litex/boards/platforms/kc705.py b/litex/boards/platforms/kc705.py
index d1f02a505..394e58675 100644
--- a/litex/boards/platforms/kc705.py
+++ b/litex/boards/platforms/kc705.py
@@ -3,7 +3,8 @@
 # This file is Copyright (c) 2015 Yann Sionneau <ys@m-labs.hk>
 
 from litex.build.generic_platform import *
-from litex.build.xilinx import XilinxPlatform, VivadoProgrammer
+from litex.build.xilinx import XilinxPlatform
+from litex.build.openocd import OpenOCD
 
 # IOs ----------------------------------------------------------------------------------------------
 
@@ -548,20 +549,11 @@ set_property CONFIG_VOLTAGE 2.5 [current_design]
         self.toolchain.additional_commands = ["write_cfgmem -force -format bin -interface spix4 -size 16 -loadbit \"up 0x0 {build_name}.bit\" -file {build_name}.bin"]
 
     def create_programmer(self):
-        return VivadoProgrammer()
+        return OpenOCD("openocd_xilinx_xc7.cfg", "bscan_spi_xc7a325t.bit")
 
     def do_finalize(self, fragment):
         XilinxPlatform.do_finalize(self, fragment)
-        try:
-            self.add_period_constraint(self.lookup_request("clk200").p, 1e9/200e6)
-        except ConstraintError:
-            pass
-        try:
-            self.add_period_constraint(self.lookup_request("eth_clocks").rx, 1e9/125e6)
-        except ConstraintError:
-            pass
-        try:
-            self.add_period_constraint(self.lookup_request("eth_clocks").tx, 1e9/125e6)
-        except ConstraintError:
-            pass
+        self.add_period_constraint(self.lookup_request("clk200",        loose=True), 1e9/200e6)
+        self.add_period_constraint(self.lookup_request("eth_clocks:rx", loose=True), 1e9/125e6)
+        self.add_period_constraint(self.lookup_request("eth_clocks:tx", loose=True), 1e9/125e6)
         self.add_platform_command("set_property DCI_CASCADE {{32 34}} [get_iobanks 33]")
diff --git a/litex/boards/platforms/kcu105.py b/litex/boards/platforms/kcu105.py
index 038df0fbc..1230011de 100644
--- a/litex/boards/platforms/kcu105.py
+++ b/litex/boards/platforms/kcu105.py
@@ -498,6 +498,8 @@ class Platform(XilinxPlatform):
 
     def do_finalize(self, fragment):
         XilinxPlatform.do_finalize(self, fragment)
+        self.add_period_constraint(self.lookup_request("clk125", loose=True), 1e9/125e6)
+        self.add_period_constraint(self.lookup_request("clk300", loose=True), 1e9/300e6)
         self.add_platform_command("set_property INTERNAL_VREF 0.84 [get_iobanks 44]")
         self.add_platform_command("set_property INTERNAL_VREF 0.84 [get_iobanks 45]")
         self.add_platform_command("set_property INTERNAL_VREF 0.84 [get_iobanks 46]")
diff --git a/litex/boards/platforms/machxo3.py b/litex/boards/platforms/machxo3.py
index ebf72d6a1..d47242f41 100644
--- a/litex/boards/platforms/machxo3.py
+++ b/litex/boards/platforms/machxo3.py
@@ -92,3 +92,7 @@ class Platform(LatticePlatform):
 </ispXCF>
 """
         return LatticeProgrammer(_xcf_template)
+
+    def do_finalize(self, fragment):
+        LatticePlatform.do_finalize(self, fragment)
+        self.add_period_constraint(self.lookup_request("clk12", loose=True), 1e9/12e6)
diff --git a/litex/boards/platforms/minispartan6.py b/litex/boards/platforms/minispartan6.py
index 046ee16b3..0ad7e0799 100644
--- a/litex/boards/platforms/minispartan6.py
+++ b/litex/boards/platforms/minispartan6.py
@@ -3,7 +3,7 @@
 
 from litex.build.generic_platform import *
 from litex.build.xilinx import XilinxPlatform
-from litex.build.xilinx.programmer import FpgaProg
+from litex.build.xilinx.programmer import XC3SProg
 
 # IOs ----------------------------------------------------------------------------------------------
 
@@ -136,4 +136,9 @@ class Platform(XilinxPlatform):
         XilinxPlatform.__init__(self, device+"-3-ftg256", _io, _connectors)
 
     def create_programmer(self):
-        return FpgaProg()
+        return XC3SProg(cable="ftdi")
+
+    def do_finalize(self, fragment):
+        XilinxPlatform.do_finalize(self, fragment)
+        self.add_period_constraint(self.lookup_request("clk32", loose=True), 1e9/32e6)
+        self.add_period_constraint(self.lookup_request("clk50", loose=True), 1e9/50e6)
diff --git a/litex/boards/platforms/netv2.py b/litex/boards/platforms/netv2.py
index f3e8abc8e..c201b07f4 100644
--- a/litex/boards/platforms/netv2.py
+++ b/litex/boards/platforms/netv2.py
@@ -2,7 +2,8 @@
 # License: BSD
 
 from litex.build.generic_platform import *
-from litex.build.xilinx import XilinxPlatform, VivadoProgrammer
+from litex.build.xilinx import XilinxPlatform
+from litex.build.openocd import OpenOCD
 
 # IOs ----------------------------------------------------------------------------------------------
 
@@ -191,3 +192,12 @@ class Platform(XilinxPlatform):
     def __init__(self, device="xc7a35t"):
         assert device in ["xc7a35t", "xc7a100t"]
         XilinxPlatform.__init__(self, device + "-fgg484-2", _io, toolchain="vivado")
+
+    def create_programmer(self):
+        bscan_spi = "bscan_spi_xc7a100t.bit" if "xc7a100t" in self.device else "bscan_spi_xc7a35t.bit"
+        return OpenOCD("openocd_netv2_rpi.cfg", bscan_spi)
+
+    def do_finalize(self, fragment):
+        XilinxPlatform.do_finalize(self, fragment)
+        self.add_period_constraint(self.lookup_request("clk50",      loose=True), 1e9/50e6)
+        self.add_period_constraint(self.lookup_request("eth_clocks", loose=True), 1e9/50e6)
diff --git a/litex/boards/platforms/nexys4ddr.py b/litex/boards/platforms/nexys4ddr.py
index b52ca6491..e112ca621 100644
--- a/litex/boards/platforms/nexys4ddr.py
+++ b/litex/boards/platforms/nexys4ddr.py
@@ -3,6 +3,7 @@
 
 from litex.build.generic_platform import *
 from litex.build.xilinx import XilinxPlatform, VivadoProgrammer
+from litex.build.openocd import OpenOCD
 
 # IOs ----------------------------------------------------------------------------------------------
 
@@ -131,4 +132,9 @@ class Platform(XilinxPlatform):
         self.add_platform_command("set_property INTERNAL_VREF 0.750 [get_iobanks 34]")
 
     def create_programmer(self):
-        return VivadoProgrammer()
+        return OpenOCD("openocd_xilinx_xc7.cfg", "bscan_spi_xc7a100t.bit")
+
+    def do_finalize(self, fragment):
+        XilinxPlatform.do_finalize(self, fragment)
+        self.add_period_constraint(self.lookup_request("clk100",             loose=True), 1e9/100e6)
+        self.add_period_constraint(self.lookup_request("eth_clocks:ref_clk", loose=True), 1e9/50e6)
diff --git a/litex/boards/platforms/nexys_video.py b/litex/boards/platforms/nexys_video.py
index dad949b8f..e4a58ac82 100644
--- a/litex/boards/platforms/nexys_video.py
+++ b/litex/boards/platforms/nexys_video.py
@@ -3,6 +3,7 @@
 
 from litex.build.generic_platform import *
 from litex.build.xilinx import XilinxPlatform, VivadoProgrammer
+from litex.build.openocd import OpenOCD
 
 # IOs ----------------------------------------------------------------------------------------------
 
@@ -230,9 +231,8 @@ class Platform(XilinxPlatform):
              "-loadbit \"up 0x0 {build_name}.bit\" -file {build_name}.bin"]
         self.add_platform_command("set_property INTERNAL_VREF 0.750 [get_iobanks 35]")
 
-
     def create_programmer(self):
-        return VivadoProgrammer(flash_part="n25q128-3.3v-spi-x1_x2_x4")
+        return OpenOCD("openocd_xilinx_xc7.cfg", "bscan_spi_xc7a200t.bit")
 
     def do_finalize(self, fragment):
         XilinxPlatform.do_finalize(self, fragment)
@@ -240,3 +240,8 @@ class Platform(XilinxPlatform):
             self.add_period_constraint(self.lookup_request("eth_clocks").rx, 1e9/125e6)
         except ConstraintError:
             pass
+
+    def do_finalize(self, fragment):
+        XilinxPlatform.do_finalize(self, fragment)
+        self.add_period_constraint(self.lookup_request("clk100",     loose=True), 1e9/100e6)
+        self.add_period_constraint(self.lookup_request("eth_clocks", loose=True), 1e9/125e6)
diff --git a/litex/boards/platforms/tinyfpga_bx.py b/litex/boards/platforms/tinyfpga_bx.py
index 4cfe96382..a1bfd5e52 100644
--- a/litex/boards/platforms/tinyfpga_bx.py
+++ b/litex/boards/platforms/tinyfpga_bx.py
@@ -67,3 +67,7 @@ class Platform(LatticePlatform):
 
     def create_programmer(self):
         return TinyProgProgrammer()
+
+    def do_finalize(self, fragment):
+        LatticePlatform.do_finalize(self, fragment)
+        self.add_period_constraint(self.lookup_request("clk16", loose=True), 1e9/16e6)
diff --git a/litex/boards/platforms/ulx3s.py b/litex/boards/platforms/ulx3s.py
index 20640fc38..f2859cba0 100644
--- a/litex/boards/platforms/ulx3s.py
+++ b/litex/boards/platforms/ulx3s.py
@@ -3,6 +3,7 @@
 
 from litex.build.generic_platform import *
 from litex.build.lattice import LatticePlatform
+from litex.build.lattice.programmer import UJProg
 
 # IOs ----------------------------------------------------------------------------------------------
 
@@ -84,6 +85,13 @@ _io = [
         Subsignal("n", Pins("C10")),
         IOStandard("LVCMOS33")
     ),
+
+    ("usb", 0,
+        Subsignal("d_p", Pins("D15")),
+        Subsignal("d_n", Pins("E15")),
+        Subsignal("pullup", Pins("B12 C12")),
+        IOStandard("LVCMOS33")
+    ),
 ]
 
 # Platform -----------------------------------------------------------------------------------------
@@ -94,3 +102,10 @@ class Platform(LatticePlatform):
 
     def __init__(self, device="LFE5U-45F", **kwargs):
         LatticePlatform.__init__(self, device + "-6BG381C", _io, **kwargs)
+
+    def create_programmer(self):
+        return UJProg()
+
+    def do_finalize(self, fragment):
+        LatticePlatform.do_finalize(self, fragment)
+        self.add_period_constraint(self.lookup_request("clk25", loose=True), 1e9/25e6)
diff --git a/litex/boards/platforms/versa_ecp5.py b/litex/boards/platforms/versa_ecp5.py
index e3b40b418..4ea3df466 100644
--- a/litex/boards/platforms/versa_ecp5.py
+++ b/litex/boards/platforms/versa_ecp5.py
@@ -4,7 +4,7 @@
 
 from litex.build.generic_platform import *
 from litex.build.lattice import LatticePlatform
-from litex.build.lattice.programmer import LatticeProgrammer
+from litex.build.lattice.programmer import OpenOCDJTAGProgrammer
 
 # IOs ----------------------------------------------------------------------------------------------
 
@@ -224,12 +224,10 @@ class Platform(LatticePlatform):
     def __init__(self, **kwargs):
         LatticePlatform.__init__(self, "LFE5UM5G-45F-8BG381C", _io, _connectors, **kwargs)
 
+    def create_programmer(self):
+        return OpenOCDJTAGProgrammer("openocd_versa_ecp5.cfg")
+
     def do_finalize(self, fragment):
-        try:
-            self.add_period_constraint(self.lookup_request("eth_clocks", 0).rx, 1e9/125e6)
-        except ConstraintError:
-            pass
-        try:
-            self.add_period_constraint(self.lookup_request("eth_clocks", 1).rx, 1e9/125e6)
-        except ConstraintError:
-            pass
+        self.add_period_constraint(self.lookup_request("clk100", loose=True), 1e9/100e6)
+        self.add_period_constraint(self.lookup_request("eth_clocks:rx", 0, loose=True), 1e9/125e6)
+        self.add_period_constraint(self.lookup_request("eth_clocks:rx", 1, loose=True), 1e9/125e6)
diff --git a/litex/boards/targets/arty.py b/litex/boards/targets/arty.py
index 8f3368389..29e33bc3e 100755
--- a/litex/boards/targets/arty.py
+++ b/litex/boards/targets/arty.py
@@ -3,6 +3,7 @@
 # This file is Copyright (c) 2015-2019 Florent Kermarrec <florent@enjoy-digital.fr>
 # License: BSD
 
+import os
 import argparse
 
 from migen import *
@@ -96,20 +97,25 @@ class BaseSoC(SoCCore):
 # Build --------------------------------------------------------------------------------------------
 
 def main():
-    parser = argparse.ArgumentParser(description="LiteX SoC on Arty")
+    parser = argparse.ArgumentParser(description="LiteX SoC on Arty A7")
+    parser.add_argument("--build", action="store_true", help="Build bitstream")
+    parser.add_argument("--load",  action="store_true", help="Load bitstream")
     builder_args(parser)
     soc_sdram_args(parser)
     vivado_build_args(parser)
-    parser.add_argument("--with-ethernet", action="store_true", help="enable Ethernet support")
-    parser.add_argument("--with-etherbone", action="store_true", help="enable Etherbone support")
+    parser.add_argument("--with-ethernet",  action="store_true", help="Enable Ethernet support")
+    parser.add_argument("--with-etherbone", action="store_true", help="Enable Etherbone support")
     args = parser.parse_args()
 
     assert not (args.with_ethernet and args.with_etherbone)
     soc = BaseSoC(with_ethernet=args.with_ethernet, with_etherbone=args.with_etherbone,
         **soc_sdram_argdict(args))
     builder = Builder(soc, **builder_argdict(args))
-    builder.build(**vivado_build_argdict(args))
+    builder.build(**vivado_build_argdict(args), run=args.build)
 
+    if args.load:
+        prog = soc.platform.create_programmer()
+        prog.load_bitstream(os.path.join(builder.gateware_dir, "top.bit"))
 
 if __name__ == "__main__":
     main()
diff --git a/litex/boards/targets/de0nano.py b/litex/boards/targets/de0nano.py
index 5830f35e8..960dc48ec 100755
--- a/litex/boards/targets/de0nano.py
+++ b/litex/boards/targets/de0nano.py
@@ -3,6 +3,7 @@
 # This file is Copyright (c) 2015-2020 Florent Kermarrec <florent@enjoy-digital.fr>
 # License: BSD
 
+import os
 import argparse
 
 from migen import *
@@ -31,7 +32,6 @@ class _CRG(Module):
 
         # Clk / Rst
         clk50 = platform.request("clk50")
-        platform.add_period_constraint(clk50, 1e9/50e6)
 
         # PLL
         self.submodules.pll = pll = CycloneIVPLL(speedgrade="-6")
@@ -71,14 +71,19 @@ class BaseSoC(SoCCore):
 
 def main():
     parser = argparse.ArgumentParser(description="LiteX SoC on DE0 Nano")
+    parser.add_argument("--build", action="store_true", help="Build bitstream")
+    parser.add_argument("--load",  action="store_true", help="Load bitstream")
     builder_args(parser)
     soc_sdram_args(parser)
     args = parser.parse_args()
 
     soc = BaseSoC(**soc_sdram_argdict(args))
     builder = Builder(soc, **builder_argdict(args))
-    builder.build()
+    builder.build(run=args.build)
 
+    if args.load:
+        prog = soc.platform.create_programmer()
+        prog.load_bitstream(os.path.join(builder.gateware_dir, "top.sof"))
 
 if __name__ == "__main__":
     main()
diff --git a/litex/boards/targets/genesys2.py b/litex/boards/targets/genesys2.py
index d97b68a36..8557c0c52 100755
--- a/litex/boards/targets/genesys2.py
+++ b/litex/boards/targets/genesys2.py
@@ -3,6 +3,7 @@
 # This file is Copyright (c) 2019 Florent Kermarrec <florent@enjoy-digital.fr>
 # License: BSD
 
+import os
 import argparse
 
 from migen import *
@@ -87,6 +88,8 @@ class BaseSoC(SoCCore):
 
 def main():
     parser = argparse.ArgumentParser(description="LiteX SoC on Genesys2")
+    parser.add_argument("--build", action="store_true", help="Build bitstream")
+    parser.add_argument("--load",  action="store_true", help="Load bitstream")
     builder_args(parser)
     soc_sdram_args(parser)
     parser.add_argument("--with-ethernet",  action="store_true", help="enable Ethernet support")
@@ -97,8 +100,11 @@ def main():
     soc = BaseSoC(with_ethernet=args.with_ethernet, with_etherbone=args.with_etherbone,
         **soc_sdram_argdict(args))
     builder = Builder(soc, **builder_argdict(args))
-    builder.build()
+    builder.build(run=args.build)
 
+    if args.load:
+        prog = soc.platform.create_programmer()
+        prog.load_bitstream(os.path.join(builder.gateware_dir, "top.bit"))
 
 if __name__ == "__main__":
     main()
diff --git a/litex/boards/targets/icebreaker.py b/litex/boards/targets/icebreaker.py
index 938281798..ae1363b92 100755
--- a/litex/boards/targets/icebreaker.py
+++ b/litex/boards/targets/icebreaker.py
@@ -14,6 +14,7 @@
 # with more features, examples to run C/Rust code on the RISC-V CPU and documentation can be found
 # at: https://github.com/icebreaker-fpga/icebreaker-litex-examples
 
+import os
 import argparse
 
 from migen import *
@@ -115,18 +116,24 @@ def flash(bios_flash_offset):
 
 def main():
     parser = argparse.ArgumentParser(description="LiteX SoC on iCEBreaker")
-    parser.add_argument("--bios-flash-offset", default=0x40000, help="BIOS offset in SPI Flash")
-    parser.add_argument("--flash", action="store_true", help="Load Bitstream")
+    parser.add_argument("--build",             action="store_true", help="Build bitstream")
+    parser.add_argument("--load",              action="store_true", help="Load bitstream")
+    parser.add_argument("--bios-flash-offset", default=0x40000,     help="BIOS offset in SPI Flash")
+    parser.add_argument("--flash",             action="store_true", help="Flash Bitstream")
     builder_args(parser)
     soc_core_args(parser)
     args = parser.parse_args()
 
+    soc     = BaseSoC(args.bios_flash_offset, **soc_core_argdict(args))
+    builder = Builder(soc, **builder_argdict(args))
+    builder.build(run=args.build)
+
+    if args.load:
+        prog = soc.platform.create_programmer()
+        prog.load_bitstream(os.path.join(builder.gateware_dir, "top.bin"))
+
     if args.flash:
         flash(args.bios_flash_offset)
 
-    soc     = BaseSoC(args.bios_flash_offset, **soc_core_argdict(args))
-    builder = Builder(soc, **builder_argdict(args))
-    builder.build()
-
 if __name__ == "__main__":
     main()
diff --git a/litex/boards/targets/kc705.py b/litex/boards/targets/kc705.py
index 87290e477..9bca15823 100755
--- a/litex/boards/targets/kc705.py
+++ b/litex/boards/targets/kc705.py
@@ -5,6 +5,7 @@
 # This file is Copyright (c) 2014-2015 Yann Sionneau <ys@m-labs.hk>
 # License: BSD
 
+import os
 import argparse
 
 from migen import *
@@ -83,16 +84,20 @@ class BaseSoC(SoCCore):
 
 def main():
     parser = argparse.ArgumentParser(description="LiteX SoC on KC705")
+    parser.add_argument("--build", action="store_true", help="Build bitstream")
+    parser.add_argument("--load",  action="store_true", help="Load bitstream")
     builder_args(parser)
     soc_sdram_args(parser)
-    parser.add_argument("--with-ethernet", action="store_true",
-                        help="enable Ethernet support")
+    parser.add_argument("--with-ethernet", action="store_true", help="Enable Ethernet support")
     args = parser.parse_args()
 
     soc = BaseSoC(with_ethernet=args.with_ethernet, **soc_sdram_argdict(args))
     builder = Builder(soc, **builder_argdict(args))
-    builder.build()
+    builder.build(run=args.build)
 
+    if args.load:
+        prog = soc.platform.create_programmer()
+        prog.load_bitstream(os.path.join(builder.gateware_dir, "top.bit"))
 
 if __name__ == "__main__":
     main()
diff --git a/litex/boards/targets/kcu105.py b/litex/boards/targets/kcu105.py
index b632b16cc..a0c98f862 100755
--- a/litex/boards/targets/kcu105.py
+++ b/litex/boards/targets/kcu105.py
@@ -3,6 +3,7 @@
 # This file is Copyright (c) 2018-2019 Florent Kermarrec <florent@enjoy-digital.fr>
 # License: BSD
 
+import os
 import argparse
 
 from migen import *
@@ -92,16 +93,20 @@ class BaseSoC(SoCCore):
 
 def main():
     parser = argparse.ArgumentParser(description="LiteX SoC on KCU105")
+    parser.add_argument("--build", action="store_true", help="Build bitstream")
+    parser.add_argument("--load",  action="store_true", help="Load bitstream")
     builder_args(parser)
     soc_sdram_args(parser)
-    parser.add_argument("--with-ethernet", action="store_true",
-                        help="enable Ethernet support")
+    parser.add_argument("--with-ethernet", action="store_true", help="Enable Ethernet support")
     args = parser.parse_args()
 
     soc = BaseSoC(with_ethernet=args.with_ethernet, **soc_sdram_argdict(args))
     builder = Builder(soc, **builder_argdict(args))
-    builder.build()
+    builder.build(run=args.build)
 
+    if args.load:
+        prog = soc.platform.create_programmer()
+        prog.load_bitstream(os.path.join(builder.gateware_dir, "top.bit"))
 
 if __name__ == "__main__":
     main()
diff --git a/litex/boards/targets/minispartan6.py b/litex/boards/targets/minispartan6.py
index 638d28d18..641e11192 100755
--- a/litex/boards/targets/minispartan6.py
+++ b/litex/boards/targets/minispartan6.py
@@ -5,6 +5,7 @@
 # This file is Copyright (c) 2014 Yann Sionneau <ys@m-labs.hk>
 # License: BSD
 
+import os
 import argparse
 from fractions import Fraction
 
@@ -69,14 +70,19 @@ class BaseSoC(SoCCore):
 
 def main():
     parser = argparse.ArgumentParser(description="LiteX SoC on MiniSpartan6")
+    parser.add_argument("--build", action="store_true", help="Build bitstream")
+    parser.add_argument("--load",  action="store_true", help="Load bitstream")
     builder_args(parser)
     soc_sdram_args(parser)
     args = parser.parse_args()
 
     soc = BaseSoC(**soc_sdram_argdict(args))
     builder = Builder(soc, **builder_argdict(args))
-    builder.build()
+    builder.build(run=args.build)
 
+    if args.load:
+        prog = soc.platform.create_programmer()
+        prog.load_bitstream(os.path.join(builder.gateware_dir, "top.bit"))
 
 if __name__ == "__main__":
     main()
diff --git a/litex/boards/targets/netv2.py b/litex/boards/targets/netv2.py
index cb4270489..7535bc3c6 100755
--- a/litex/boards/targets/netv2.py
+++ b/litex/boards/targets/netv2.py
@@ -3,6 +3,7 @@
 # This file is Copyright (c) 2018-2019 Florent Kermarrec <florent@enjoy-digital.fr>
 # License: BSD
 
+import os
 import argparse
 
 from migen import *
@@ -95,18 +96,21 @@ class BaseSoC(SoCCore):
 
 def main():
     parser = argparse.ArgumentParser(description="LiteX SoC on NeTV2")
+    parser.add_argument("--build", action="store_true", help="Build bitstream")
+    parser.add_argument("--load",  action="store_true", help="Load bitstream")
     builder_args(parser)
     soc_sdram_args(parser)
-    parser.add_argument("--with-ethernet", action="store_true",
-                        help="enable Ethernet support")
-    parser.add_argument("--with-spi-xip", action="store_true",
-                        help="enable SPI XIP support")
+    parser.add_argument("--with-ethernet", action="store_true", help="Enable Ethernet support")
+    parser.add_argument("--with-spi-xip",  action="store_true", help="Enable SPI XIP support")
     args = parser.parse_args()
 
     soc = BaseSoC(with_ethernet=args.with_ethernet, with_spi_xip=args.with_spi_xip, **soc_sdram_argdict(args))
     builder = Builder(soc, **builder_argdict(args))
-    builder.build()
+    builder.build(run=args.build)
 
+    if args.load:
+        prog = soc.platform.create_programmer()
+        prog.load_bitstream(os.path.join(builder.gateware_dir, "top.bit"))
 
 if __name__ == "__main__":
     main()
diff --git a/litex/boards/targets/nexys4ddr.py b/litex/boards/targets/nexys4ddr.py
index a4b617df8..e608963fb 100755
--- a/litex/boards/targets/nexys4ddr.py
+++ b/litex/boards/targets/nexys4ddr.py
@@ -3,6 +3,7 @@
 # This file is Copyright (c) 2018-2019 Florent Kermarrec <florent@enjoy-digital.fr>
 # License: BSD
 
+import os
 import argparse
 
 from migen import *
@@ -117,16 +118,14 @@ class BaseSoC(SoCCore):
 
 def main():
     parser = argparse.ArgumentParser(description="LiteX SoC on Nexys4DDR")
+    parser.add_argument("--build", action="store_true", help="Build bitstream")
+    parser.add_argument("--load",  action="store_true", help="Load bitstream")
     builder_args(parser)
     soc_sdram_args(parser)
-    parser.add_argument("--sys-clk-freq", default=75e6,
-                        help="system clock frequency (default=75MHz)")
-    parser.add_argument("--with-ethernet", action="store_true",
-                        help="enable Ethernet support")
-    parser.add_argument("--with-spi-sdcard", action="store_true",
-                        help="enable SPI-mode SDCard support")
-    parser.add_argument("--with-sdcard", action="store_true",
-                        help="enable SDCard support")
+    parser.add_argument("--sys-clk-freq",  default=75e6,          help="System clock frequency (default=75MHz)")
+    parser.add_argument("--with-ethernet", action="store_true",   help="Enable Ethernet support")
+    parser.add_argument("--with-spi-sdcard", action="store_true", help="enable SPI-mode SDCard support")
+    parser.add_argument("--with-sdcard", action="store_true",     help="enable SDCard support")
     args = parser.parse_args()
 
     soc = BaseSoC(sys_clk_freq=int(float(args.sys_clk_freq)),
@@ -139,8 +138,11 @@ def main():
             raise ValueError("'--with-spi-sdcard' and '--with-sdcard' are mutually exclusive!")
         soc.add_sdcard()
     builder = Builder(soc, **builder_argdict(args))
-    builder.build()
+    builder.build(run=args.build)
 
+    if args.load:
+        prog = soc.platform.create_programmer()
+        prog.load_bitstream(os.path.join(builder.gateware_dir, "top.bit"))
 
 if __name__ == "__main__":
     main()
diff --git a/litex/boards/targets/nexys_video.py b/litex/boards/targets/nexys_video.py
index 677a20f05..f53a0bfa0 100755
--- a/litex/boards/targets/nexys_video.py
+++ b/litex/boards/targets/nexys_video.py
@@ -3,6 +3,7 @@
 # This file is Copyright (c) 2015-2019 Florent Kermarrec <florent@enjoy-digital.fr>
 # License: BSD
 
+import os
 import argparse
 
 from migen import *
@@ -83,16 +84,20 @@ class BaseSoC(SoCCore):
 
 def main():
     parser = argparse.ArgumentParser(description="LiteX SoC on Nexys Video")
+    parser.add_argument("--build", action="store_true", help="Build bitstream")
+    parser.add_argument("--load",  action="store_true", help="Load bitstream")
     builder_args(parser)
     soc_sdram_args(parser)
-    parser.add_argument("--with-ethernet", action="store_true",
-                        help="enable Ethernet support")
+    parser.add_argument("--with-ethernet", action="store_true", help="Enable Ethernet support")
     args = parser.parse_args()
 
     soc = BaseSoC(with_ethernet=args.with_ethernet, **soc_sdram_argdict(args))
     builder = Builder(soc, **builder_argdict(args))
-    builder.build()
+    builder.build(run=args.build)
 
+    if args.load:
+        prog = soc.platform.create_programmer()
+        prog.load_bitstream(os.path.join(builder.gateware_dir, "top.bit"))
 
 if __name__ == "__main__":
     main()
diff --git a/litex/boards/targets/simple.py b/litex/boards/targets/simple.py
index b208544fb..70872bb0c 100755
--- a/litex/boards/targets/simple.py
+++ b/litex/boards/targets/simple.py
@@ -4,6 +4,7 @@
 # This file is Copyright (c) 2013-2014 Sebastien Bourdeauducq <sb@m-labs.hk>
 # License: BSD
 
+import os
 import argparse
 import importlib
 
@@ -41,14 +42,12 @@ class BaseSoC(SoCCore):
 
 def main():
     parser = argparse.ArgumentParser(description="Generic LiteX SoC")
+    parser.add_argument("--build", action="store_true", help="Build bitstream")
     builder_args(parser)
     soc_core_args(parser)
-    parser.add_argument("--with-ethernet", action="store_true",
-                        help="enable Ethernet support")
-    parser.add_argument("platform",
-                        help="module name of the platform to build for")
-    parser.add_argument("--gateware-toolchain", default=None,
-                        help="FPGA gateware toolchain used for build")
+    parser.add_argument("--with-ethernet", action="store_true", help="Enable Ethernet support")
+    parser.add_argument("platform",                             help="Module name of the platform to build for")
+    parser.add_argument("--gateware-toolchain", default=None,   help="FPGA gateware toolchain used for build")
     args = parser.parse_args()
 
     platform_module = importlib.import_module(args.platform)
@@ -58,7 +57,7 @@ def main():
         platform = platform_module.Platform()
     soc = BaseSoC(platform, with_ethernet=args.with_ethernet, **soc_core_argdict(args))
     builder = Builder(soc, **builder_argdict(args))
-    builder.build()
+    builder.build(run=args.build)
 
 
 if __name__ == "__main__":
diff --git a/litex/boards/targets/ulx3s.py b/litex/boards/targets/ulx3s.py
index a7668e3a9..9802266ca 100755
--- a/litex/boards/targets/ulx3s.py
+++ b/litex/boards/targets/ulx3s.py
@@ -4,6 +4,7 @@
 # This file is Copyright (c) 2018 David Shah <dave@ds0.me>
 # License: BSD
 
+import os
 import argparse
 import sys
 
@@ -27,7 +28,7 @@ from litedram.phy import GENSDRPHY
 # CRG ----------------------------------------------------------------------------------------------
 
 class _CRG(Module):
-    def __init__(self, platform, sys_clk_freq):
+    def __init__(self, platform, sys_clk_freq, with_usb_pll=False):
         self.clock_domains.cd_sys    = ClockDomain()
         self.clock_domains.cd_sys_ps = ClockDomain(reset_less=True)
 
@@ -36,7 +37,6 @@ class _CRG(Module):
         # Clk / Rst
         clk25 = platform.request("clk25")
         rst   = platform.request("rst")
-        platform.add_period_constraint(clk25, 1e9/25e6)
 
         # PLL
         self.submodules.pll = pll = ECP5PLL()
@@ -46,6 +46,15 @@ class _CRG(Module):
         pll.create_clkout(self.cd_sys_ps, sys_clk_freq, phase=90)
         self.specials += AsyncResetSynchronizer(self.cd_sys, ~pll.locked | rst)
 
+        # USB PLL
+        if with_usb_pll:
+            self.submodules.usb_pll = usb_pll = ECP5PLL()
+            usb_pll.register_clkin(clk25, 25e6)
+            self.clock_domains.cd_usb_12 = ClockDomain()
+            self.clock_domains.cd_usb_48 = ClockDomain()
+            usb_pll.create_clkout(self.cd_usb_12, 12e6, margin=0)
+            usb_pll.create_clkout(self.cd_usb_48, 48e6, margin=0)
+
         # SDRAM clock
         self.specials += DDROutput(1, 0, platform.request("sdram_clock"), ClockSignal("sys_ps"))
 
@@ -64,7 +73,8 @@ class BaseSoC(SoCCore):
         SoCCore.__init__(self, platform, clk_freq=sys_clk_freq, **kwargs)
 
         # CRG --------------------------------------------------------------------------------------
-        self.submodules.crg = _CRG(platform, sys_clk_freq)
+        with_usb_pll = kwargs.get("uart_name", None) == "usb_acm"
+        self.submodules.crg = _CRG(platform, sys_clk_freq, with_usb_pll)
 
         # SDR SDRAM --------------------------------------------------------------------------------
         if not self.integrated_main_ram_size:
@@ -83,14 +93,12 @@ class BaseSoC(SoCCore):
 
 def main():
     parser = argparse.ArgumentParser(description="LiteX SoC on ULX3S")
-    parser.add_argument("--gateware-toolchain", dest="toolchain", default="trellis",
-        help="gateware toolchain to use, trellis (default) or diamond")
-    parser.add_argument("--device", dest="device", default="LFE5U-45F",
-        help="FPGA device, ULX3S can be populated with LFE5U-12F, LFE5U-25F, LFE5U-45F (default) or LFE5U-85F")
-    parser.add_argument("--sys-clk-freq", default=50e6,
-                        help="system clock frequency (default=50MHz)")
-    parser.add_argument("--sdram-module", default="MT48LC16M16",
-                        help="SDRAM module: MT48LC16M16, AS4C32M16 or AS4C16M16 (default=MT48LC16M16)")
+    parser.add_argument("--build", action="store_true", help="Build bitstream")
+    parser.add_argument("--load",  action="store_true", help="Load bitstream")
+    parser.add_argument("--gateware-toolchain", dest="toolchain", default="trellis",   help="Gateware toolchain to use, trellis (default) or diamond")
+    parser.add_argument("--device",             dest="device",    default="LFE5U-45F", help="FPGA device, ULX3S can be populated with LFE5U-45F (default) or LFE5U-85F")
+    parser.add_argument("--sys-clk-freq", default=50e6,          help="System clock frequency (default=50MHz)")
+    parser.add_argument("--sdram-module", default="MT48LC16M16", help="SDRAM module: MT48LC16M16, AS4C32M16 or AS4C16M16 (default=MT48LC16M16)")
     builder_args(parser)
     soc_sdram_args(parser)
     trellis_args(parser)
@@ -102,7 +110,11 @@ def main():
         **soc_sdram_argdict(args))
     builder = Builder(soc, **builder_argdict(args))
     builder_kargs = trellis_argdict(args) if args.toolchain == "trellis" else {}
-    builder.build(**builder_kargs)
+    builder.build(**builder_kargs, run=args.build)
+
+    if args.load:
+        prog = soc.platform.create_programmer()
+        prog.load_bitstream(os.path.join(builder.gateware_dir, "top.svf"))
 
 if __name__ == "__main__":
     main()
diff --git a/litex/boards/targets/versa_ecp5.py b/litex/boards/targets/versa_ecp5.py
index 49d8a6517..e390575f5 100755
--- a/litex/boards/targets/versa_ecp5.py
+++ b/litex/boards/targets/versa_ecp5.py
@@ -4,6 +4,7 @@
 # This file is Copyright (c) 2018-2019 David Shah <dave@ds0.me>
 # License: BSD
 
+import os
 import argparse
 
 from migen import *
@@ -40,7 +41,6 @@ class _CRG(Module):
         # Clk / Rst
         clk100 = platform.request("clk100")
         rst_n  = platform.request("rst_n")
-        platform.add_period_constraint(clk100, 1e9/100e6)
 
         # Power on reset
         por_count = Signal(16, reset=2**16-1)
@@ -110,21 +110,24 @@ class BaseSoC(SoCCore):
 
 def main():
     parser = argparse.ArgumentParser(description="LiteX SoC on Versa ECP5")
-    parser.add_argument("--gateware-toolchain", dest="toolchain", default="trellis",
-        help="gateware toolchain to use, trellis (default) or diamond")
+    parser.add_argument("--build", action="store_true", help="Build bitstream")
+    parser.add_argument("--load",  action="store_true", help="Load bitstream")
+    parser.add_argument("--gateware-toolchain", dest="toolchain", default="trellis", help="Gateware toolchain to use, trellis (default) or diamond")
     builder_args(parser)
     soc_sdram_args(parser)
     trellis_args(parser)
-    parser.add_argument("--sys-clk-freq", default=75e6,
-                        help="system clock frequency (default=75MHz)")
-    parser.add_argument("--with-ethernet", action="store_true",
-                        help="enable Ethernet support")
+    parser.add_argument("--sys-clk-freq",  default=75e6,        help="System clock frequency (default=75MHz)")
+    parser.add_argument("--with-ethernet", action="store_true", help="Enable Ethernet support")
     args = parser.parse_args()
 
     soc = BaseSoC(sys_clk_freq=int(float(args.sys_clk_freq)), with_ethernet=args.with_ethernet, toolchain=args.toolchain, **soc_sdram_argdict(args))
     builder = Builder(soc, **builder_argdict(args))
     builder_kargs = trellis_argdict(args) if args.toolchain == "trellis" else {}
-    builder.build(**builder_kargs)
+    builder.build(**builder_kargs, run=args.build)
+
+    if args.load:
+        prog = soc.platform.create_programmer()
+        prog.load_bitstream(os.path.join(builder.gateware_dir, "top.svf"))
 
 if __name__ == "__main__":
     main()

From 98d1b45157c90ddf0d07ebf3bcdafef51dc6324d Mon Sep 17 00:00:00 2001
From: Florent Kermarrec <florent@enjoy-digital.fr>
Date: Tue, 5 May 2020 15:55:09 +0200
Subject: [PATCH 87/95] platforms/targets: fix CI.

---
 litex/boards/platforms/netv2.py       | 4 ++--
 litex/boards/platforms/nexys_video.py | 4 ++--
 test/test_targets.py                  | 2 --
 3 files changed, 4 insertions(+), 6 deletions(-)

diff --git a/litex/boards/platforms/netv2.py b/litex/boards/platforms/netv2.py
index c201b07f4..b598172c7 100644
--- a/litex/boards/platforms/netv2.py
+++ b/litex/boards/platforms/netv2.py
@@ -199,5 +199,5 @@ class Platform(XilinxPlatform):
 
     def do_finalize(self, fragment):
         XilinxPlatform.do_finalize(self, fragment)
-        self.add_period_constraint(self.lookup_request("clk50",      loose=True), 1e9/50e6)
-        self.add_period_constraint(self.lookup_request("eth_clocks", loose=True), 1e9/50e6)
+        self.add_period_constraint(self.lookup_request("clk50",              loose=True), 1e9/50e6)
+        self.add_period_constraint(self.lookup_request("eth_clocks:ref_clk", loose=True), 1e9/50e6)
diff --git a/litex/boards/platforms/nexys_video.py b/litex/boards/platforms/nexys_video.py
index e4a58ac82..c8604e9f4 100644
--- a/litex/boards/platforms/nexys_video.py
+++ b/litex/boards/platforms/nexys_video.py
@@ -243,5 +243,5 @@ class Platform(XilinxPlatform):
 
     def do_finalize(self, fragment):
         XilinxPlatform.do_finalize(self, fragment)
-        self.add_period_constraint(self.lookup_request("clk100",     loose=True), 1e9/100e6)
-        self.add_period_constraint(self.lookup_request("eth_clocks", loose=True), 1e9/125e6)
+        self.add_period_constraint(self.lookup_request("clk100",        loose=True), 1e9/100e6)
+        self.add_period_constraint(self.lookup_request("eth_clocks:rx", loose=True), 1e9/125e6)
diff --git a/test/test_targets.py b/test/test_targets.py
index f8100fe49..2e71719f3 100644
--- a/test/test_targets.py
+++ b/test/test_targets.py
@@ -134,7 +134,6 @@ class TestTargets(unittest.TestCase):
 litex/boards/targets/simple.py litex.boards.platforms.{p} \
     --cpu-type=vexriscv     \
     --no-compile-software   \
-    --no-compile-gateware   \
     --uart-name=stub        \
 """.format(p=p)
                 subprocess.check_call(cmd, shell=True)
@@ -155,7 +154,6 @@ litex/boards/targets/simple.py litex.boards.platforms.arty \
     --cpu-type={c}          \
     --cpu-variant={v}       \
     --no-compile-software   \
-    --no-compile-gateware   \
     --uart-name=stub        \
 """.format(c=cpu, v=variant)
         subprocess.check_output(cmd, shell=True)

From 95b57899cd8dde8be6a95eb8abab35a5e15605bd Mon Sep 17 00:00:00 2001
From: Florent Kermarrec <florent@enjoy-digital.fr>
Date: Tue, 5 May 2020 16:27:21 +0200
Subject: [PATCH 88/95] bios: remove usddrphy debug (we'll use a specific debug
 firmware to fix the usddrphy corner cases).

---
 litex/boards/targets/kcu105.py                |   1 -
 litex/soc/software/bios/Makefile              |  13 +-
 .../soc/software/bios/commands/cmd_usddrphy.c | 128 ------------------
 litex/soc/software/bios/sdram.c               |  91 +------------
 litex/soc/software/bios/sdram.h               |   7 -
 5 files changed, 7 insertions(+), 233 deletions(-)
 delete mode 100644 litex/soc/software/bios/commands/cmd_usddrphy.c

diff --git a/litex/boards/targets/kcu105.py b/litex/boards/targets/kcu105.py
index a0c98f862..138f3ffa7 100755
--- a/litex/boards/targets/kcu105.py
+++ b/litex/boards/targets/kcu105.py
@@ -68,7 +68,6 @@ class BaseSoC(SoCCore):
                 iodelay_clk_freq = 200e6,
                 cmd_latency      = 1)
             self.add_csr("ddrphy")
-            self.add_constant("USDDRPHY_DEBUG")
             self.add_sdram("sdram",
                 phy                     = self.ddrphy,
                 module                  = EDY4016A(sys_clk_freq, "1:4"),
diff --git a/litex/soc/software/bios/Makefile b/litex/soc/software/bios/Makefile
index 0369522e6..9fba33a62 100755
--- a/litex/soc/software/bios/Makefile
+++ b/litex/soc/software/bios/Makefile
@@ -11,12 +11,12 @@ CFLAGS += -DTFTP_SERVER_PORT=$(TFTP_SERVER_PORT)
 endif
 
 OBJECTS = isr.o			\
-	  sdram.o		\
-	  sdcard.o		\
-	  main.o		\
+	  sdram.o			\
+	  sdcard.o			\
+	  main.o			\
 	  boot-helper.o		\
-	  boot.o		\
-	  helpers.o		\
+	  boot.o			\
+	  helpers.o			\
 	  cmd_bios.o		\
 	  cmd_boot.o		\
 	  cmd_dram.o		\
@@ -24,7 +24,6 @@ OBJECTS = isr.o			\
 	  cmd_mem_access.o	\
 	  cmd_sdcard.o		\
 	  cmd_spi_flash.o	\
-	  cmd_usddrphy.o
 
 ifneq "$(or $(TERM_NO_COMPLETE),$(TERM_MINI))" ""
 CFLAGS += -DTERM_NO_COMPLETE
@@ -70,7 +69,7 @@ bios.elf: $(BIOS_DIRECTORY)/linker.ld $(OBJECTS)
 		$(BP_LIBS) \
 		-lnet -lbase-nofloat -lcompiler_rt \
 		$(BP_FLAGS)
-	
+
 ifneq ($(OS),Windows_NT)
 	chmod -x $@
 endif
diff --git a/litex/soc/software/bios/commands/cmd_usddrphy.c b/litex/soc/software/bios/commands/cmd_usddrphy.c
deleted file mode 100644
index 69c62fad0..000000000
--- a/litex/soc/software/bios/commands/cmd_usddrphy.c
+++ /dev/null
@@ -1,128 +0,0 @@
-// SPDX-License-Identifier: BSD-Source-Code
-
-#include <stdio.h>
-#include <stdlib.h>
-
-#include <generated/csr.h>
-
-#include "../command.h"
-#include "../helpers.h"
-#include "../sdram.h"
-
-/**
- * Command "sdram_cdly"
- *
- * Set SDRAM clk/cmd delay
- *
- */
-#ifdef USDDRPHY_DEBUG
-static void sdram_cdly(int nb_params, char **params)
-{
-	unsigned int delay;
-	char *c;
-
-	if (nb_params < 1) {
-		printf("sdram_cdly <delay>");
-		return;
-	}
-
-	delay = strtoul(params[0], &c, 0);
-	if (*c != 0) {
-		printf("Incorrect delay");
-		return;
-	}
-
-	ddrphy_cdly(delay);
-}
-
-define_command(sdram_cdly, sdram_cdly, "Set SDRAM clk/cmd delay", DDR_CMDS);
-#endif
-
-/**
- * Command "sdram_cdly"
- *
- * Run SDRAM calibration
- *
- */
-#ifdef USDDRPHY_DEBUG
-define_command(sdram_cal, sdram_cal, "Run SDRAM calibration", DDR_CMDS);
-#endif
-
-/**
- * Command "sdram_mpr"
- *
- * Read SDRAM MPR
- *
- */
-#ifdef USDDRPHY_DEBUG
-define_command(sdram_mpr, sdram_mpr, "Read SDRAM MPR", DDR_CMDS);
-#endif
-
-
-/**
- * Command "sdram_mrwr"
- *
- * Write SDRAM mode registers
- *
- */
-#ifdef USDDRPHY_DEBUG
-static void sdram_mrwr(int nb_params, char **params)
-{
-	unsigned int reg;
-	unsigned int value;
-	char *c;
-
-	if (nb_params < 2) {
-		printf("sdram_mrwr <reg> <value>");
-		return;
-	}
-
-	reg = strtoul(params[0], &c, 0);
-	if (*c != 0) {
-		printf("Incorrect register value");
-		return;
-	}
-
-	value = strtoul(params[1], &c, 0);
-	if (*c != 0) {
-		printf("Incorrect value");
-		return;
-	}
-
-	sdrsw();
-	printf("Writing 0x%04x to SDRAM mode register %d\n", value, reg);
-	sdrmrwr(reg, value);
-	sdrhw();
-}
-
-define_command(sdram_mrwr, sdram_mrwr, "Write SDRAM mode registers", DDR_CMDS);
-#endif
-
-/**
- * Command "sdram_cdly_scan"
- *
- * Enable/disable cdly scan
- *
- */
-#ifdef USDDRPHY_DEBUG
-static void sdram_cdly_scan(int nb_params, char **params)
-{
-	unsigned int value;
-	char *c;
-
-	if (nb_params < 1) {
-		printf("sdram_cdly_scan <value>");
-		return;
-	}
-
-	value = strtoul(params[0], &c, 0);
-	if (*c != 0) {
-		printf("Incorrect value");
-		return;
-	}
-
-	sdr_cdly_scan(value);
-}
-
-define_command(sdram_cdly_scan, sdram_cdly_scan, "Enable/disable cdly scan", DDR_CMDS);
-#endif
diff --git a/litex/soc/software/bios/sdram.c b/litex/soc/software/bios/sdram.c
index 1923b49b0..9056a2ff1 100644
--- a/litex/soc/software/bios/sdram.c
+++ b/litex/soc/software/bios/sdram.c
@@ -166,7 +166,7 @@ void sdrwr(unsigned int addr)
 
 #ifdef CSR_DDRPHY_BASE
 
-#if defined(DDRPHY_CMD_DELAY) || defined(USDDRPHY_DEBUG)
+#if defined(DDRPHY_CMD_DELAY)
 void ddrphy_cdly(unsigned int delay) {
 	printf("Setting clk/cmd delay to %d taps\n", delay);
 #if CSR_DDRPHY_EN_VTC_ADDR
@@ -1048,93 +1048,4 @@ int sdrinit(void)
 	return 1;
 }
 
-#ifdef USDDRPHY_DEBUG
-
-#define MPR0_SEL (0 << 0)
-#define MPR1_SEL (1 << 0)
-#define MPR2_SEL (2 << 0)
-#define MPR3_SEL (3 << 0)
-
-#define MPR_ENABLE (1 << 2)
-
-#define MPR_READ_SERIAL    (0 << 11)
-#define MPR_READ_PARALLEL  (1 << 11)
-#define MPR_READ_STAGGERED (2 << 11)
-
-void sdrcal(void)
-{
-#ifdef CSR_DDRPHY_BASE
-#if CSR_DDRPHY_EN_VTC_ADDR
-	ddrphy_en_vtc_write(0);
-#endif
-	sdrlevel();
-#if CSR_DDRPHY_EN_VTC_ADDR
-	ddrphy_en_vtc_write(1);
-#endif
-#endif
-	sdrhw();
-}
-
-void sdrmrwr(char reg, int value) {
-	sdram_dfii_pi0_address_write(value);
-	sdram_dfii_pi0_baddress_write(reg);
-	command_p0(DFII_COMMAND_RAS|DFII_COMMAND_CAS|DFII_COMMAND_WE|DFII_COMMAND_CS);
-}
-
-static void sdrmpron(char mpr)
-{
-	sdrmrwr(3, MPR_READ_SERIAL | MPR_ENABLE | mpr);
-}
-
-static void sdrmproff(void)
-{
-	sdrmrwr(3, 0);
-}
-
-void sdrmpr(void)
-{
-	int module, phase;
-	unsigned char buf[DFII_PIX_DATA_BYTES];
-	printf("Read SDRAM MPR...\n");
-
-	/* rst phy */
-	for(module=0; module<SDRAM_PHY_MODULES; module++) {
-#ifdef SDRAM_PHY_WRITE_LEVELING_CAPABLE
-		write_delay_rst(module);
-#endif
-		read_delay_rst(module);
-		read_bitslip_rst(module);
-	}
-
-	/* software control */
-	sdrsw();
-
-	printf("Reads with MPR0 (0b01010101) enabled...\n");
-	sdrmpron(MPR0_SEL);
-	command_prd(DFII_COMMAND_CAS|DFII_COMMAND_CS|DFII_COMMAND_RDDATA);
-	cdelay(15);
-	for (module=0; module < SDRAM_PHY_MODULES; module++) {
-		printf("m%d: ", module);
-		for(phase=0; phase<SDRAM_PHY_PHASES; phase++) {
-			csr_rd_buf_uint8(sdram_dfii_pix_rddata_addr[phase],
-					 buf, DFII_PIX_DATA_BYTES);
-			printf("%d", buf[  SDRAM_PHY_MODULES-module-1] & 0x1);
-			printf("%d", buf[2*SDRAM_PHY_MODULES-module-1] & 0x1);
-		}
-		printf("\n");
-	}
-	sdrmproff();
-
-	/* hardware control */
-	sdrhw();
-}
-
-void sdr_cdly_scan(int enabled)
-{
-	printf("Turning cdly scan %s\n", enabled ? "ON" : "OFF");
-	_write_level_cdly_scan = enabled;
-}
-
-#endif
-
 #endif
diff --git a/litex/soc/software/bios/sdram.h b/litex/soc/software/bios/sdram.h
index d777c22cf..21433c03c 100644
--- a/litex/soc/software/bios/sdram.h
+++ b/litex/soc/software/bios/sdram.h
@@ -25,11 +25,4 @@ int sdrinit(void);
 void ddrphy_cdly(unsigned int delay);
 #endif
 
-#ifdef USDDRPHY_DEBUG
-void sdrcal(void);
-void sdrmrwr(char reg, int value);
-void sdrmpr(void);
-void sdr_cdly_scan(int enabled);
-#endif
-
 #endif /* __SDRAM_H */

From 0aa3c339ccfddad71657060448c72a3144879311 Mon Sep 17 00:00:00 2001
From: Florent Kermarrec <florent@enjoy-digital.fr>
Date: Tue, 5 May 2020 16:33:14 +0200
Subject: [PATCH 89/95] targets/genesys2: set cmd_latency to 1.

---
 litex/boards/targets/genesys2.py | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/litex/boards/targets/genesys2.py b/litex/boards/targets/genesys2.py
index 8557c0c52..d0b33def0 100755
--- a/litex/boards/targets/genesys2.py
+++ b/litex/boards/targets/genesys2.py
@@ -56,7 +56,8 @@ class BaseSoC(SoCCore):
             self.submodules.ddrphy = s7ddrphy.K7DDRPHY(platform.request("ddram"),
                 memtype      = "DDR3",
                 nphases      = 4,
-                sys_clk_freq = sys_clk_freq)
+                sys_clk_freq = sys_clk_freq,
+                cmd_latency  = 1)
             self.add_csr("ddrphy")
             self.add_sdram("sdram",
                 phy                     = self.ddrphy,

From b0578580714ad7d298e244fc3835c06ba082f2c1 Mon Sep 17 00:00:00 2001
From: Florent Kermarrec <florent@enjoy-digital.fr>
Date: Tue, 5 May 2020 16:58:33 +0200
Subject: [PATCH 90/95] gen/fhdl/verilog: explicitly define input/output/inout
 wires.

When integrating designs which set `default_nettype none, the top also needs
to explicitly define the type of the signals.
---
 litex/gen/fhdl/verilog.py | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/litex/gen/fhdl/verilog.py b/litex/gen/fhdl/verilog.py
index f515dbfb2..98a732707 100644
--- a/litex/gen/fhdl/verilog.py
+++ b/litex/gen/fhdl/verilog.py
@@ -236,17 +236,17 @@ def _printheader(f, ios, name, ns, attr_translate,
         sig.type = "wire"
         if sig in inouts:
             sig.direction = "inout"
-            r += "\tinout " + _printsig(ns, sig)
+            r += "\tinout wire " + _printsig(ns, sig)
         elif sig in targets:
             sig.direction = "output"
             if sig in wires:
-                r += "\toutput " + _printsig(ns, sig)
+                r += "\toutput wire " + _printsig(ns, sig)
             else:
                 sig.type = "reg"
                 r += "\toutput reg " + _printsig(ns, sig)
         else:
             sig.direction = "input"
-            r += "\tinput " + _printsig(ns, sig)
+            r += "\tinput wire " + _printsig(ns, sig)
     r += "\n);\n\n"
     for sig in sorted(sigs - ios, key=lambda x: x.duid):
         attr = _printattr(sig.attr, attr_translate)

From 5e049d8966b4e97b52d01d81150c9bcfcdd860bb Mon Sep 17 00:00:00 2001
From: Arnaud Durand <arnaud.durand@unifr.ch>
Date: Tue, 5 May 2020 22:15:24 +0200
Subject: [PATCH 91/95] Add data dirs to manifest

---
 MANIFEST.in | 10 ++++++++++
 1 file changed, 10 insertions(+)

diff --git a/MANIFEST.in b/MANIFEST.in
index d64974bd3..683cad06c 100644
--- a/MANIFEST.in
+++ b/MANIFEST.in
@@ -1 +1,11 @@
 graft litex/build/sim
+graft litex/soc/software
+graft litex/soc/cores/cpu/blackparrot
+graft litex/soc/cores/cpu/lm32
+graft litex/soc/cores/cpu/microwatt
+graft litex/soc/cores/cpu/minerva
+graft litex/soc/cores/cpu/mor1kx
+graft litex/soc/cores/cpu/picorv32
+graft litex/soc/cores/cpu/rocket
+graft litex/soc/cores/cpu/serv
+graft litex/soc/cores/cpu/vexriscv

From 3c34039b731b42e27e2ee6c8e399e5eb8f3a058f Mon Sep 17 00:00:00 2001
From: Florent Kermarrec <florent@enjoy-digital.fr>
Date: Wed, 6 May 2020 13:13:01 +0200
Subject: [PATCH 92/95] build/xilinx/vivado: ensure Vivado process our .xdc
 early.

When generating the LitePCIe PHY wrappers from the .xci, Vivado is locking the
PCIe lanes to default locations that do not necessarily match the ones used in
the design.

Processing our constraints earlier makes Vivado use our constraints and not the
ones from the generated wrapper.
---
 litex/build/xilinx/vivado.py | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/litex/build/xilinx/vivado.py b/litex/build/xilinx/vivado.py
index 2a8b91d29..70cf5c808 100644
--- a/litex/build/xilinx/vivado.py
+++ b/litex/build/xilinx/vivado.py
@@ -167,6 +167,7 @@ class XilinxVivadoToolchain:
         # Add constraints
         tcl.append("\n# Add constraints\n")
         tcl.append("read_xdc {}.xdc".format(build_name))
+        tcl.append("set_property PROCESSING_ORDER EARLY [get_files {}.xdc]".format(build_name))
 
         # Add pre-synthesis commands
         tcl.append("\n# Add pre-synthesis commands\n")
@@ -276,7 +277,7 @@ class XilinxVivadoToolchain:
             "-to [get_pins -filter {{REF_PIN_NAME == PRE}} "
                 "-of_objects [get_cells -hierarchical -filter {{ars_ff1 == TRUE || ars_ff2 == TRUE}}]]"
         )
-        # clock_period-2ns to resolve metastability on the wire between the AsyncResetSynchronizer FFs 
+        # clock_period-2ns to resolve metastability on the wire between the AsyncResetSynchronizer FFs
         platform.add_platform_command(
             "set_max_delay 2 -quiet "
             "-from [get_pins -filter {{REF_PIN_NAME == C}} "

From 8b9aa16d2e7d00d49304fed13a0d4c4d80d5d1e2 Mon Sep 17 00:00:00 2001
From: Florent Kermarrec <florent@enjoy-digital.fr>
Date: Wed, 6 May 2020 16:16:41 +0200
Subject: [PATCH 93/95] boards/platforms: update xilinx programmers.

---
 litex/boards/platforms/arty.py        | 2 +-
 litex/boards/platforms/genesys2.py    | 2 +-
 litex/boards/platforms/kc705.py       | 2 +-
 litex/boards/platforms/nexys4ddr.py   | 2 +-
 litex/boards/platforms/nexys_video.py | 2 +-
 5 files changed, 5 insertions(+), 5 deletions(-)

diff --git a/litex/boards/platforms/arty.py b/litex/boards/platforms/arty.py
index 712cd9aba..1f8101d47 100644
--- a/litex/boards/platforms/arty.py
+++ b/litex/boards/platforms/arty.py
@@ -259,7 +259,7 @@ class Platform(XilinxPlatform):
 
     def create_programmer(self):
         bscan_spi = "bscan_spi_xc7a100t.bit" if "xc7a100t" in self.device else "bscan_spi_xc7a35t.bit"
-        return OpenOCD("openocd_xilinx_xc7.cfg", bscan_spi)
+        return OpenOCD("openocd_xc7_ft2232.cfg", bscan_spi)
 
     def do_finalize(self, fragment):
         XilinxPlatform.do_finalize(self, fragment)
diff --git a/litex/boards/platforms/genesys2.py b/litex/boards/platforms/genesys2.py
index 7e5ebc43c..7da31c872 100644
--- a/litex/boards/platforms/genesys2.py
+++ b/litex/boards/platforms/genesys2.py
@@ -117,7 +117,7 @@ class Platform(XilinxPlatform):
         XilinxPlatform.__init__(self, "xc7k325t-ffg900-2", _io, _connectors, toolchain="vivado")
 
     def create_programmer(self):
-        return OpenOCD("openocd_xilinx_xc7.cfg", "bscan_spi_xc7a325t.bit")
+        return OpenOCD("openocd_xc7_ft2232.cfg", "bscan_spi_xc7a325t.bit")
 
     def do_finalize(self, fragment):
         XilinxPlatform.do_finalize(self, fragment)
diff --git a/litex/boards/platforms/kc705.py b/litex/boards/platforms/kc705.py
index 394e58675..dcb0001e1 100644
--- a/litex/boards/platforms/kc705.py
+++ b/litex/boards/platforms/kc705.py
@@ -549,7 +549,7 @@ set_property CONFIG_VOLTAGE 2.5 [current_design]
         self.toolchain.additional_commands = ["write_cfgmem -force -format bin -interface spix4 -size 16 -loadbit \"up 0x0 {build_name}.bit\" -file {build_name}.bin"]
 
     def create_programmer(self):
-        return OpenOCD("openocd_xilinx_xc7.cfg", "bscan_spi_xc7a325t.bit")
+        return OpenOCD("openocd_xc7_ft2232.cfg", "bscan_spi_xc7a325t.bit")
 
     def do_finalize(self, fragment):
         XilinxPlatform.do_finalize(self, fragment)
diff --git a/litex/boards/platforms/nexys4ddr.py b/litex/boards/platforms/nexys4ddr.py
index e112ca621..060caeb03 100644
--- a/litex/boards/platforms/nexys4ddr.py
+++ b/litex/boards/platforms/nexys4ddr.py
@@ -132,7 +132,7 @@ class Platform(XilinxPlatform):
         self.add_platform_command("set_property INTERNAL_VREF 0.750 [get_iobanks 34]")
 
     def create_programmer(self):
-        return OpenOCD("openocd_xilinx_xc7.cfg", "bscan_spi_xc7a100t.bit")
+        return OpenOCD("openocd_xc7_ft2232.cfg", "bscan_spi_xc7a100t.bit")
 
     def do_finalize(self, fragment):
         XilinxPlatform.do_finalize(self, fragment)
diff --git a/litex/boards/platforms/nexys_video.py b/litex/boards/platforms/nexys_video.py
index c8604e9f4..6dbb9456f 100644
--- a/litex/boards/platforms/nexys_video.py
+++ b/litex/boards/platforms/nexys_video.py
@@ -232,7 +232,7 @@ class Platform(XilinxPlatform):
         self.add_platform_command("set_property INTERNAL_VREF 0.750 [get_iobanks 35]")
 
     def create_programmer(self):
-        return OpenOCD("openocd_xilinx_xc7.cfg", "bscan_spi_xc7a200t.bit")
+        return OpenOCD("openocd_xc7_ft2232.cfg", "bscan_spi_xc7a200t.bit")
 
     def do_finalize(self, fragment):
         XilinxPlatform.do_finalize(self, fragment)

From 99c5b0fca1d1db5317d53407f7f238d25d10e8a2 Mon Sep 17 00:00:00 2001
From: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Date: Wed, 6 May 2020 21:54:27 +0200
Subject: [PATCH 94/95] bios/sdram: Use an LFSR to speed up pseudo-random
 number generation

This speeds up the memory test by an order of magnitude, esp. on
cores without a hardware multiplier by getting rid of the
multiplication in the loop.

The LFSR implementation comes from microwatt's simple_random test
project.

Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
---
 litex/soc/software/bios/lfsr.h  | 109 ++++++++++++++++++++++++++++++++
 litex/soc/software/bios/sdram.c |  17 ++---
 2 files changed, 118 insertions(+), 8 deletions(-)
 create mode 100644 litex/soc/software/bios/lfsr.h

diff --git a/litex/soc/software/bios/lfsr.h b/litex/soc/software/bios/lfsr.h
new file mode 100644
index 000000000..50dfccfc7
--- /dev/null
+++ b/litex/soc/software/bios/lfsr.h
@@ -0,0 +1,109 @@
+#include <limits.h>
+
+/*
+ * Copyright (C) 2020, Anton Blanchard <anton@linux.ibm.com>, IBM
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice, this
+ *    list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/*
+ * Galois LFSR
+ *
+ * Polynomials verified with https://bitbucket.org/gallen/mlpolygen/
+ */
+static inline unsigned long lfsr(unsigned long bits, unsigned long prev)
+{
+       static const unsigned long lfsr_taps[] = {
+               0x0,
+               0x0,
+               0x3,
+               0x6,
+               0xc,
+               0x14,
+               0x30,
+               0x60,
+               0xb8,
+               0x110,
+               0x240,
+               0x500,
+               0x829,
+               0x100d,
+               0x2015,
+               0x6000,
+               0xd008,
+               0x12000,
+               0x20400,
+               0x40023,
+               0x90000,
+               0x140000,
+               0x300000,
+               0x420000,
+               0xe10000,
+               0x1200000,
+               0x2000023,
+               0x4000013,
+               0x9000000,
+               0x14000000,
+               0x20000029,
+               0x48000000,
+               0x80200003,
+#if __WORDSIZE == 64
+               0x100080000,
+               0x204000003,
+               0x500000000,
+               0x801000000,
+               0x100000001f,
+               0x2000000031,
+               0x4400000000,
+               0xa000140000,
+               0x12000000000,
+               0x300000c0000,
+               0x63000000000,
+               0xc0000030000,
+               0x1b0000000000,
+               0x300003000000,
+               0x420000000000,
+               0xc00000180000,
+               0x1008000000000,
+               0x3000000c00000,
+               0x6000c00000000,
+               0x9000000000000,
+               0x18003000000000,
+               0x30000000030000,
+               0x40000040000000,
+               0xc0000600000000,
+               0x102000000000000,
+               0x200004000000000,
+               0x600003000000000,
+               0xc00000000000000,
+               0x1800300000000000,
+               0x3000000000000030,
+               0x6000000000000000,
+               0x800000000000000d
+#endif
+       };
+       unsigned long lsb = prev & 1;
+
+       prev >>= 1;
+       prev ^= (-lsb) & lfsr_taps[bits];
+
+       return prev;
+}
diff --git a/litex/soc/software/bios/sdram.c b/litex/soc/software/bios/sdram.c
index 9056a2ff1..517a223a1 100644
--- a/litex/soc/software/bios/sdram.c
+++ b/litex/soc/software/bios/sdram.c
@@ -21,6 +21,7 @@
 #include <system.h>
 
 #include "sdram.h"
+#include "lfsr.h"
 
 // FIXME(hack): If we don't have main ram, just target the sram instead.
 #ifndef MAIN_RAM_BASE
@@ -514,7 +515,7 @@ static int read_level_scan(int module, int bitslip)
 	prv = 42;
 	for(p=0;p<SDRAM_PHY_PHASES;p++)
 		for(i=0;i<DFII_PIX_DATA_BYTES;i++) {
-			prv = 1664525*prv + 1013904223;
+			return lfsr(32, seed);
 			prs[p][i] = prv;
 		}
 
@@ -594,7 +595,7 @@ static void read_level(int module)
 	prv = 42;
 	for(p=0;p<SDRAM_PHY_PHASES;p++)
 		for(i=0;i<DFII_PIX_DATA_BYTES;i++) {
-			prv = 1664525*prv + 1013904223;
+			return lfsr(32, seed);
 			prs[p][i] = prv;
 		}
 
@@ -712,7 +713,7 @@ static void read_level(int module)
 static unsigned int seed_to_data_32(unsigned int seed, int random)
 {
 	if (random)
-		return 1664525*seed + 1013904223;
+		return lfsr(32, seed);
 	else
 		return seed + 1;
 }
@@ -720,7 +721,7 @@ static unsigned int seed_to_data_32(unsigned int seed, int random)
 static unsigned short seed_to_data_16(unsigned short seed, int random)
 {
 	if (random)
-		return 25173*seed + 13849;
+		return lfsr(16, seed);
 	else
 		return seed + 1;
 }
@@ -794,14 +795,14 @@ static int memtest_data(void)
 	unsigned int rdata;
 
 	errors = 0;
-	seed_32 = 0;
+	seed_32 = 1;
 
 	for(i=0;i<MEMTEST_DATA_SIZE/4;i++) {
 		seed_32 = seed_to_data_32(seed_32, MEMTEST_DATA_RANDOM);
 		array[i] = seed_32;
 	}
 
-	seed_32 = 0;
+	seed_32 = 1;
 	flush_cpu_dcache();
 #ifdef CONFIG_L2_SIZE
 	flush_l2_cache();
@@ -834,14 +835,14 @@ static int memtest_addr(void)
 	unsigned short rdata;
 
 	errors = 0;
-	seed_16 = 0;
+	seed_16 = 1;
 
 	for(i=0;i<MEMTEST_ADDR_SIZE/4;i++) {
 		seed_16 = seed_to_data_16(seed_16, MEMTEST_ADDR_RANDOM);
 		array[(unsigned int) seed_16] = i;
 	}
 
-	seed_16 = 0;
+	seed_16 = 1;
 	flush_cpu_dcache();
 #ifdef CONFIG_L2_SIZE
 	flush_l2_cache();

From 84841e1d58cbe0dbd97756832770d5acbec45f38 Mon Sep 17 00:00:00 2001
From: Florent Kermarrec <florent@enjoy-digital.fr>
Date: Thu, 7 May 2020 08:21:57 +0200
Subject: [PATCH 95/95] bios/sdram: fix merge typo in lfsr (thanks Benjamin
 Herrenschmidt).

---
 litex/soc/software/bios/sdram.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/litex/soc/software/bios/sdram.c b/litex/soc/software/bios/sdram.c
index 517a223a1..6121fb0b1 100644
--- a/litex/soc/software/bios/sdram.c
+++ b/litex/soc/software/bios/sdram.c
@@ -515,7 +515,7 @@ static int read_level_scan(int module, int bitslip)
 	prv = 42;
 	for(p=0;p<SDRAM_PHY_PHASES;p++)
 		for(i=0;i<DFII_PIX_DATA_BYTES;i++) {
-			return lfsr(32, seed);
+			return lfsr(32, prv);
 			prs[p][i] = prv;
 		}
 
@@ -595,7 +595,7 @@ static void read_level(int module)
 	prv = 42;
 	for(p=0;p<SDRAM_PHY_PHASES;p++)
 		for(i=0;i<DFII_PIX_DATA_BYTES;i++) {
-			return lfsr(32, seed);
+			return lfsr(32, prv);
 			prs[p][i] = prv;
 		}