From 2a7d2908d1d48abe0516eb136097ecbc907c5f78 Mon Sep 17 00:00:00 2001
From: Sebastien Bourdeauducq <sebastien@milkymist.org>
Date: Sun, 9 Sep 2012 19:34:46 +0200
Subject: [PATCH] examples: new namer

---
 examples/basic/namer.py | 40 ++++++++++++++++++++++++++++++++++++++++
 1 file changed, 40 insertions(+)
 create mode 100644 examples/basic/namer.py

diff --git a/examples/basic/namer.py b/examples/basic/namer.py
new file mode 100644
index 000000000..f3e31c6eb
--- /dev/null
+++ b/examples/basic/namer.py
@@ -0,0 +1,40 @@
+from migen.fhdl.structure import *
+from migen.fhdl import verilog
+from migen.corelogic.misc import optree
+
+def gen_list(n):
+	s = [Signal() for i in range(n)]
+	return s
+
+def gen_2list(n):
+	s = [Signal(BV(2)) for i in range(n)]
+	return s
+
+class Foo:
+	def __init__(self):
+		la = gen_list(3)
+		lb = gen_2list(2)
+		self.sigs = la + lb
+
+class Bar:
+	def __init__(self):
+		self.sigs = gen_list(2)
+		
+class Toto:
+	def __init__(self):
+		self.sigs = gen_list(2)
+
+a = [Bar() for x in range(3)]
+b = [Foo() for x in range(3)]
+c = b
+b = [Bar() for x in range(2)]
+
+output = Signal()
+allsigs = []
+for lst in [a, b, c]:
+	for obj in lst:
+		allsigs.extend(obj.sigs)
+comb = [output.eq(optree("|", allsigs))]
+
+f = Fragment(comb)
+print(verilog.convert(f))