From 2b786065b1bd0c97303ba13bc1591bfbe2949465 Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Fri, 7 Sep 2018 10:37:15 +0200 Subject: [PATCH] targets: pass endianness to LiteEThMAC, tftp working with RISC-V, still need to fix txlen --- litex/boards/targets/arty.py | 3 ++- litex/boards/targets/genesys2.py | 3 ++- litex/boards/targets/kc705.py | 3 ++- litex/boards/targets/nexys_video.py | 3 ++- litex/boards/targets/sim.py | 3 ++- litex/boards/targets/simple.py | 3 +-- litex/soc/software/libnet/microudp.c | 7 ++++--- 7 files changed, 15 insertions(+), 10 deletions(-) diff --git a/litex/boards/targets/arty.py b/litex/boards/targets/arty.py index 501a8d7ec..fcb2a4f6e 100755 --- a/litex/boards/targets/arty.py +++ b/litex/boards/targets/arty.py @@ -136,7 +136,8 @@ class MiniSoC(BaseSoC): self.submodules.ethphy = LiteEthPHYMII(self.platform.request("eth_clocks"), self.platform.request("eth")) - self.submodules.ethmac = LiteEthMAC(phy=self.ethphy, dw=32, interface="wishbone", endianness="little") + self.submodules.ethmac = LiteEthMAC(phy=self.ethphy, dw=32, + interface="wishbone", endianness=self.cpu_endianness) self.add_wb_slave(mem_decoder(self.mem_map["ethmac"]), self.ethmac.bus) self.add_memory_region("ethmac", self.mem_map["ethmac"] | self.shadow_base, 0x2000) diff --git a/litex/boards/targets/genesys2.py b/litex/boards/targets/genesys2.py index b42743e50..460f0e47f 100755 --- a/litex/boards/targets/genesys2.py +++ b/litex/boards/targets/genesys2.py @@ -118,7 +118,8 @@ class MiniSoC(BaseSoC): self.submodules.ethphy = LiteEthPHYRGMII(self.platform.request("eth_clocks"), self.platform.request("eth")) - self.submodules.ethmac = LiteEthMAC(phy=self.ethphy, dw=32, interface="wishbone") + self.submodules.ethmac = LiteEthMAC(phy=self.ethphy, dw=32, + interface="wishbone", endianness=self.cpu_endianness) self.add_wb_slave(mem_decoder(self.mem_map["ethmac"]), self.ethmac.bus) self.add_memory_region("ethmac", self.mem_map["ethmac"] | self.shadow_base, 0x2000) diff --git a/litex/boards/targets/kc705.py b/litex/boards/targets/kc705.py index 89498d675..514c33e84 100755 --- a/litex/boards/targets/kc705.py +++ b/litex/boards/targets/kc705.py @@ -118,7 +118,8 @@ class MiniSoC(BaseSoC): self.submodules.ethphy = LiteEthPHY(self.platform.request("eth_clocks"), self.platform.request("eth"), clk_freq=self.clk_freq) - self.submodules.ethmac = LiteEthMAC(phy=self.ethphy, dw=32, interface="wishbone") + self.submodules.ethmac = LiteEthMAC(phy=self.ethphy, dw=32, + interface="wishbone", endianness=self.cpu_endianness) self.add_wb_slave(mem_decoder(self.mem_map["ethmac"]), self.ethmac.bus) self.add_memory_region("ethmac", self.mem_map["ethmac"] | self.shadow_base, 0x2000) diff --git a/litex/boards/targets/nexys_video.py b/litex/boards/targets/nexys_video.py index e0146fbb4..3a97e2aac 100755 --- a/litex/boards/targets/nexys_video.py +++ b/litex/boards/targets/nexys_video.py @@ -125,7 +125,8 @@ class MiniSoC(BaseSoC): self.submodules.ethphy = LiteEthPHYRGMII(self.platform.request("eth_clocks"), self.platform.request("eth")) - self.submodules.ethmac = LiteEthMAC(phy=self.ethphy, dw=32, interface="wishbone") + self.submodules.ethmac = LiteEthMAC(phy=self.ethphy, dw=32, + interface="wishbone", endianness=self.cpu_endianness) self.add_wb_slave(mem_decoder(self.mem_map["ethmac"]), self.ethmac.bus) self.add_memory_region("ethmac", self.mem_map["ethmac"] | self.shadow_base, 0x2000) diff --git a/litex/boards/targets/sim.py b/litex/boards/targets/sim.py index 1cd08bd67..d62ecdf95 100755 --- a/litex/boards/targets/sim.py +++ b/litex/boards/targets/sim.py @@ -87,7 +87,8 @@ class MiniSoC(BaseSoC): BaseSoC.__init__(self, *args, **kwargs) self.submodules.ethphy = LiteEthPHYModel(self.platform.request("eth")) - self.submodules.ethmac = LiteEthMAC(phy=self.ethphy, dw=32, interface="wishbone") + self.submodules.ethmac = LiteEthMAC(phy=self.ethphy, dw=32, + interface="wishbone", endianness=self.cpu_endianness) self.add_wb_slave(mem_decoder(self.mem_map["ethmac"]), self.ethmac.bus) self.add_memory_region("ethmac", self.mem_map["ethmac"] | self.shadow_base, 0x2000) diff --git a/litex/boards/targets/simple.py b/litex/boards/targets/simple.py index ccc8cbc3c..8577a04a1 100755 --- a/litex/boards/targets/simple.py +++ b/litex/boards/targets/simple.py @@ -45,8 +45,7 @@ class MiniSoC(BaseSoC): self.submodules.ethphy = LiteEthPHY(platform.request("eth_clocks"), platform.request("eth")) self.submodules.ethmac = LiteEthMAC(phy=self.ethphy, dw=32, - interface="wishbone", - with_preamble_crc=False) + interface="wishbone", endianness=self.cpu_endianness, with_preamble_crc=False) self.add_wb_slave(mem_decoder(self.mem_map["ethmac"]), self.ethmac.bus) self.add_memory_region("ethmac", self.mem_map["ethmac"] | self.shadow_base, 0x2000) diff --git a/litex/soc/software/libnet/microudp.c b/litex/soc/software/libnet/microudp.c index b54107101..38e16588b 100644 --- a/litex/soc/software/libnet/microudp.c +++ b/litex/soc/software/libnet/microudp.c @@ -127,6 +127,7 @@ static ethernet_buffer *txbuffer1; static void send_packet(void) { + #ifndef HW_PREAMBLE_CRC unsigned int crc; crc = crc32(&txbuffer->raw[8], txlen-8); @@ -134,9 +135,9 @@ static void send_packet(void) txbuffer->raw[txlen+1] = (crc & 0xff00) >> 8; txbuffer->raw[txlen+2] = (crc & 0xff0000) >> 16; txbuffer->raw[txlen+3] = (crc & 0xff000000) >> 24; - //txlen += 4; + txlen += 4; #endif - txlen += 4; // FIXME + txlen += 4; //FIXME: padding? #ifdef DEBUG_MICROUDP_TX int j; @@ -169,7 +170,7 @@ static void process_arp(void) const struct arp_frame *rx_arp = &rxbuffer->frame.contents.arp; struct arp_frame *tx_arp = &txbuffer->frame.contents.arp; - //if(rxlen < ARP_PACKET_LENGTH) return; // FIXME + if(rxlen < ARP_PACKET_LENGTH) return; if(ntohs(rx_arp->hwtype) != ARP_HWTYPE_ETHERNET) return; if(ntohs(rx_arp->proto) != ARP_PROTO_IP) return; if(rx_arp->hwsize != 6) return;