From 2bc1c3ac9907c1d8913fec7894334028848456cf Mon Sep 17 00:00:00 2001
From: Ilia Sergachev <ilia@sergachev.ch>
Date: Wed, 19 Jan 2022 02:47:18 +0100
Subject: [PATCH] cpu/zynq7000: enable software compilation

---
 litex/soc/integration/soc.py | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/litex/soc/integration/soc.py b/litex/soc/integration/soc.py
index b5034d0ff..46f2c87ac 100644
--- a/litex/soc/integration/soc.py
+++ b/litex/soc/integration/soc.py
@@ -935,7 +935,7 @@ class SoC(Module):
             self.mem_map.update(self.cpu.mem_map)
 
         # Add Bus Masters/CSR/IRQs.
-        if not isinstance(self.cpu, (cpu.CPUNone, cpu.Zynq7000)):
+        if not isinstance(self.cpu, cpu.CPUNone):
             if hasattr(self.cpu, "set_reset_address"):
                 if reset_address is None:
                     reset_address = self.mem_map["rom"]