From 2be520546318335e5caabf58537c6c928d4e4ac1 Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Thu, 4 Oct 2018 08:17:44 +0200 Subject: [PATCH] build/xilinx/common: update XilinxDDRInputImplS7 and XilinxDDRInputImplKU (from migen) --- litex/build/xilinx/common.py | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) diff --git a/litex/build/xilinx/common.py b/litex/build/xilinx/common.py index 9e90e3426..fffa7a447 100644 --- a/litex/build/xilinx/common.py +++ b/litex/build/xilinx/common.py @@ -169,9 +169,9 @@ class XilinxDDROutputS7: class XilinxDDRInputImplS7(Module): def __init__(self, i, o1, o2, clk): self.specials += Instance("IDDR", - p_DDR_CLK_EDGE="SAME_EDGE_PIPELINED", + p_DDR_CLK_EDGE="SAME_EDGE", i_C=clk, i_CE=1, i_S=0, i_R=0, - o_D=i, i_Q1=o1, i_Q2=o2, + i_D=i, o_Q1=o1, o_Q2=o2, ) @@ -206,9 +206,10 @@ class XilinxDDRInputImplKU(Module): self.specials += Instance("IDDRE1", p_DDR_CLK_EDGE="SAME_EDGE_PIPELINED", p_IS_C_INVERTED=0, + p_IS_CB_INVERTED=1, i_D=i, o_Q1=o1, o_Q2=o2, - i_C=clk, i_CB=~clk, + i_C=clk, i_CB=clk, i_R=0 )