From 2e14569b5c640d11e2b51a9aead9c1dfb134569e Mon Sep 17 00:00:00 2001 From: Sebastien Bourdeauducq Date: Tue, 11 Sep 2012 10:00:03 +0200 Subject: [PATCH] fhdl/verilog: sort clock domains by name --- migen/fhdl/verilog.py | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/migen/fhdl/verilog.py b/migen/fhdl/verilog.py index 8993300e8..d0cbecf8f 100644 --- a/migen/fhdl/verilog.py +++ b/migen/fhdl/verilog.py @@ -1,4 +1,5 @@ from functools import partial +from operator import itemgetter from migen.fhdl.structure import * from migen.fhdl.structure import _Operator, _Slice, _Assign @@ -171,7 +172,7 @@ def _printcomb(f, ns, display_run): def _printsync(f, ns, clock_domains): r = "" - for k, v in f.sync.items(): + for k, v in sorted(f.sync.items(), key=itemgetter(0)): r += "always @(posedge " + ns.get_name(clock_domains[k].clk) + ") begin\n" r += _printnode(ns, _AT_SIGNAL, 1, insert_reset(clock_domains[k].rst, v)) r += "end\n\n"