From 2e46a81bf690593346f9744e7b5e148b525b41cb Mon Sep 17 00:00:00 2001 From: Icenowy Zheng Date: Fri, 4 Nov 2022 22:19:20 +0800 Subject: [PATCH] tools/litex_sim: hack to allow memory base other than 0x40000000 The LiteX OpenC906 core currently uses 0x0 as the base of main memory. Hack to allow this when preloading a binary in litex_sim by adding a command line argument. Signed-off-by: Icenowy Zheng --- litex/tools/litex_sim.py | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/litex/tools/litex_sim.py b/litex/tools/litex_sim.py index f78bafd7c..5adfa3a9e 100755 --- a/litex/tools/litex_sim.py +++ b/litex/tools/litex_sim.py @@ -368,6 +368,7 @@ def sim_args(parser): verilator_build_args(parser) parser.add_argument("--rom-init", default=None, help="ROM init file (.bin or .json).") parser.add_argument("--ram-init", default=None, help="RAM init file (.bin or .json).") + parser.add_argument("--main-ram-init-base", default="0x40000000", help="(SD)RAM base assumed in init file.") parser.add_argument("--with-sdram", action="store_true", help="Enable SDRAM support.") parser.add_argument("--sdram-module", default="MT48LC16M16", help="Select SDRAM chip.") parser.add_argument("--sdram-data-width", default=32, help="Set SDRAM chip data width.") @@ -421,7 +422,7 @@ def main(): ) # RAM / SDRAM. - ram_boot_offset = 0x40000000 # FIXME + ram_boot_offset = int(args.main_ram_init_base, 0) # FIXME: use main_ram in memmap ram_boot_address = None soc_kwargs["integrated_main_ram_size"] = args.integrated_main_ram_size if args.integrated_main_ram_size: