From 2e4813d6ae1a1899689e3a07eff61a5192a239b4 Mon Sep 17 00:00:00 2001
From: Dolu1990 <charles.papon.90@gmail.com>
Date: Wed, 12 Jun 2024 19:33:20 +0200
Subject: [PATCH] Fix vexii axi3

---
 litex/soc/cores/cpu/vexiiriscv/core.py | 5 +++++
 1 file changed, 5 insertions(+)

diff --git a/litex/soc/cores/cpu/vexiiriscv/core.py b/litex/soc/cores/cpu/vexiiriscv/core.py
index 4ebf865ce..1a1b37cc1 100755
--- a/litex/soc/cores/cpu/vexiiriscv/core.py
+++ b/litex/soc/cores/cpu/vexiiriscv/core.py
@@ -534,6 +534,11 @@ class VexiiRiscv(CPU):
             i_mBus_rlast     = mbus.r.last,
         )
 
+        if VexiiRiscv.with_axi3:
+            self.cpu_params.update(
+                o_mBus_wid=mbus.w.id
+            )
+
     def do_finalize(self):
         assert hasattr(self, "reset_address")