From 2e67f6a1a30b83212f8191826af7af1770e6338c Mon Sep 17 00:00:00 2001
From: Richard Tucker <richard.tucker@motec.com.au>
Date: Tue, 24 Oct 2023 09:51:21 +1100
Subject: [PATCH] soc/cores/spi_mmap: add read only slot count register

---
 litex/soc/cores/spi/spi_mmap.py | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/litex/soc/cores/spi/spi_mmap.py b/litex/soc/cores/spi/spi_mmap.py
index 24a054d60..4932248a1 100644
--- a/litex/soc/cores/spi/spi_mmap.py
+++ b/litex/soc/cores/spi/spi_mmap.py
@@ -249,6 +249,9 @@ class SPICtrl(LiteXModule):
         self._version = CSRStatus(size=32, description="""SPI Module Version.""",
             reset=int.from_bytes(str.encode(version), 'little'))
 
+        self.slot_count = CSRStatus(size=32, description="""SPI Module Slot Count.""",
+            reset=nslots)
+
         # Create TX/RX Control/Status registers.
         self.tx_control  = CSRStorage(fields=[
             CSRField("enable", size=1, offset=0, values=[