diff --git a/litex/soc/integration/soc_core.py b/litex/soc/integration/soc_core.py
index 2ce897f70..00277735d 100644
--- a/litex/soc/integration/soc_core.py
+++ b/litex/soc/integration/soc_core.py
@@ -301,10 +301,6 @@ def soc_core_args(parser):
 
     # L2 Cache
     parser.add_argument("--l2-size",           default=8192, type=auto_int, help="L2 cache size (default=8192).")
-    parser.add_argument("--min-l2-data-width", default=128,  type=auto_int, help="Minimum L2 cache datawidth (default=128).")
-
-    # SDRAM
-    parser.add_argument("--max-sdram-size", default=0x40000000, type=auto_int, help="Maximum SDRAM size mapped to the SoC (default=1GB))")
 
 def soc_core_argdict(args):
     r = dict()