From 2efd939d06ba7903892fc5a742838b49ab1728fb Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Sun, 26 Apr 2020 16:26:15 +0200 Subject: [PATCH] serv: fix ibus/dbus byte/word addressing inconsistency, add missing ibus.sel (thanks @GregDavill). --- litex/soc/cores/cpu/serv/core.py | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/litex/soc/cores/cpu/serv/core.py b/litex/soc/cores/cpu/serv/core.py index 8128fda5a..ab73cea22 100644 --- a/litex/soc/cores/cpu/serv/core.py +++ b/litex/soc/cores/cpu/serv/core.py @@ -36,7 +36,7 @@ class SERV(CPU): self.reset = Signal() self.ibus = ibus = wishbone.Interface() self.dbus = dbus = wishbone.Interface() - self.buses = [self.ibus, dbus] + self.buses = [ibus, dbus] self.interrupt = Signal(32) # # # @@ -50,14 +50,13 @@ class SERV(CPU): i_i_timer_irq = 0, # ibus - o_o_ibus_adr = ibus.adr, + o_o_ibus_adr = Cat(Signal(2), ibus.adr), o_o_ibus_cyc = ibus.cyc, i_i_ibus_rdt = ibus.dat_r, i_i_ibus_ack = ibus.ack, - # dbus - o_o_dbus_adr = dbus.adr, + o_o_dbus_adr = Cat(Signal(2), dbus.adr), o_o_dbus_dat = dbus.dat_w, o_o_dbus_sel = dbus.sel, o_o_dbus_we = dbus.we, @@ -67,6 +66,7 @@ class SERV(CPU): ) self.comb += [ ibus.stb.eq(ibus.cyc), + ibus.sel.eq(0xf), dbus.stb.eq(dbus.cyc), ]