From 2f52d364affc6f5483ff8c3e635f0469abe7525a Mon Sep 17 00:00:00 2001
From: Florent Kermarrec <florent@enjoy-digital.fr>
Date: Mon, 16 Nov 2015 16:11:31 +0100
Subject: [PATCH] soc/interconnect/stream/SyncFIFO: expose fifo level

---
 litex/soc/interconnect/stream.py        | 1 +
 litex/soc/interconnect/stream_packet.py | 2 +-
 2 files changed, 2 insertions(+), 1 deletion(-)

diff --git a/litex/soc/interconnect/stream.py b/litex/soc/interconnect/stream.py
index f0a781012..89231d1dd 100644
--- a/litex/soc/interconnect/stream.py
+++ b/litex/soc/interconnect/stream.py
@@ -113,6 +113,7 @@ class SyncFIFO(_FIFOWrapper):
             self,
             fifo.SyncFIFOBuffered if buffered else fifo.SyncFIFO,
             layout, depth)
+        self.level = self.fifo.level
 
 
 class AsyncFIFO(_FIFOWrapper):
diff --git a/litex/soc/interconnect/stream_packet.py b/litex/soc/interconnect/stream_packet.py
index cf2309c7b..6a4e2d4f2 100644
--- a/litex/soc/interconnect/stream_packet.py
+++ b/litex/soc/interconnect/stream_packet.py
@@ -379,6 +379,6 @@ class Buffer(Module):
         # compute almost full
         if almost_full is not None:
             self.almost_full = Signal()
-            self.comb += self.almost_full.eq(data_fifo.fifo.level > almost_full)
+            self.comb += self.almost_full.eq(data_fifo.level > almost_full)
 
 # XXX