From 2fd8c2cd613c59dd64a14978b8c2e22c1d8e148e Mon Sep 17 00:00:00 2001 From: Matthias Breithaupt Date: Thu, 12 Sep 2024 08:22:00 +0200 Subject: [PATCH] sim: add HW_PREAMBLE_CRC for ethernet This fixes the behavior of `ethernet_phy_model` `"sim"`. As the preamble is automatically attached by the tap, there is no need to add it from the BIOS. To let the BIOS know, `HW_PREAMBLE_CRC` needs to be set. Signed-off-by: Matthias Breithaupt --- litex/tools/litex_sim.py | 1 + 1 file changed, 1 insertion(+) diff --git a/litex/tools/litex_sim.py b/litex/tools/litex_sim.py index 3407fc85d..802d5257b 100755 --- a/litex/tools/litex_sim.py +++ b/litex/tools/litex_sim.py @@ -237,6 +237,7 @@ class SimSoC(SoCCore): if with_ethernet or with_etherbone: if ethernet_phy_model == "sim": self.ethphy = LiteEthPHYModel(self.platform.request("eth", 0)) + self.add_constant("HW_PREAMBLE_CRC"); elif ethernet_phy_model == "xgmii": self.ethphy = LiteEthPHYXGMII(None, self.platform.request("xgmii_eth", 0), model=True) elif ethernet_phy_model == "gmii":