From 306bdcaed8e7a548e33db924a9312a9d39909ee7 Mon Sep 17 00:00:00 2001
From: Florent Kermarrec <florent@enjoy-digital.fr>
Date: Fri, 15 Oct 2021 21:46:42 +0200
Subject: [PATCH] fhdl/verilog: Fix regression introduced in to_signed
 function.

---
 litex/gen/fhdl/verilog.py | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/litex/gen/fhdl/verilog.py b/litex/gen/fhdl/verilog.py
index 0de39d8d6..4366fd4a5 100644
--- a/litex/gen/fhdl/verilog.py
+++ b/litex/gen/fhdl/verilog.py
@@ -117,7 +117,7 @@ def _print_operator(ns, node):
     assert arity in [UNARY, BINARY, TERNARY]
 
     def to_signed(r):
-        return f"$signed({{1'd0 {r}}}))"
+        return f"$signed({{1'd0, {r}}})"
 
     # Unary Operator.
     if arity == UNARY: