From 309f012d2c670dffdc285fe49d15c3f8b29dfce4 Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Mon, 24 Apr 2023 10:31:47 +0200 Subject: [PATCH] cores/usb_ohci: Ensure self.usb_clk_freq is an integer (as a workaround to prevent build issue). --- litex/soc/cores/usb_ohci.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/litex/soc/cores/usb_ohci.py b/litex/soc/cores/usb_ohci.py index 3ed08c5ba..5948779ec 100644 --- a/litex/soc/cores/usb_ohci.py +++ b/litex/soc/cores/usb_ohci.py @@ -21,7 +21,7 @@ from litex.build.io import SDRTristate class USBOHCI(Module): def __init__(self, platform, pads, usb_clk_freq=48e6, dma_data_width=32): self.pads = pads - self.usb_clk_freq = usb_clk_freq + self.usb_clk_freq = int(usb_clk_freq) self.dma_data_width = dma_data_width self.wb_ctrl = wb_ctrl = wishbone.Interface(data_width=32)