From 30a18808ad67a189f57afb03d46b3115888840a9 Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Fri, 6 Dec 2019 15:58:06 +0100 Subject: [PATCH] boards/targets: keep attributes are no longer needed since automatically added when applying constraints to signals. --- litex/boards/targets/arty.py | 6 ------ litex/boards/targets/de0nano.py | 4 ---- litex/boards/targets/genesys2.py | 5 ----- litex/boards/targets/kc705.py | 5 ----- litex/boards/targets/kcu105.py | 5 ----- litex/boards/targets/minispartan6.py | 3 --- litex/boards/targets/netv2.py | 6 ------ litex/boards/targets/nexys4ddr.py | 6 ------ litex/boards/targets/nexys_video.py | 6 ------ litex/boards/targets/ulx3s.py | 3 --- litex/boards/targets/versa_ecp5.py | 8 -------- 11 files changed, 57 deletions(-) diff --git a/litex/boards/targets/arty.py b/litex/boards/targets/arty.py index fec790309..63a6ea449 100755 --- a/litex/boards/targets/arty.py +++ b/litex/boards/targets/arty.py @@ -32,10 +32,6 @@ class _CRG(Module): # # # - self.cd_sys.clk.attr.add("keep") - self.cd_sys4x.clk.attr.add("keep") - self.cd_sys4x_dqs.clk.attr.add("keep") - self.submodules.pll = pll = S7PLL(speedgrade=-1) self.comb += pll.reset.eq(~platform.request("cpu_reset")) pll.register_clkin(platform.request("clk100"), 100e6) @@ -97,8 +93,6 @@ class EthernetSoC(BaseSoC): self.add_csr("ethmac") self.add_interrupt("ethmac") - self.ethphy.crg.cd_eth_rx.clk.attr.add("keep") - self.ethphy.crg.cd_eth_tx.clk.attr.add("keep") self.platform.add_period_constraint(self.ethphy.crg.cd_eth_rx.clk, 1e9/12.5e6) self.platform.add_period_constraint(self.ethphy.crg.cd_eth_tx.clk, 1e9/12.5e6) self.platform.add_false_path_constraints( diff --git a/litex/boards/targets/de0nano.py b/litex/boards/targets/de0nano.py index 010331cf3..f05fdf43f 100755 --- a/litex/boards/targets/de0nano.py +++ b/litex/boards/targets/de0nano.py @@ -25,10 +25,6 @@ class _CRG(Module): # # # - self.cd_sys.clk.attr.add("keep") - self.cd_sys_ps.clk.attr.add("keep") - self.cd_por.clk.attr.add("keep") - # Power on reset rst_n = Signal() self.sync.por += rst_n.eq(1) diff --git a/litex/boards/targets/genesys2.py b/litex/boards/targets/genesys2.py index ff1a24a2b..0a7e95a4f 100755 --- a/litex/boards/targets/genesys2.py +++ b/litex/boards/targets/genesys2.py @@ -29,9 +29,6 @@ class _CRG(Module): # # # - self.cd_sys.clk.attr.add("keep") - self.cd_sys4x.clk.attr.add("keep") - self.submodules.pll = pll = S7MMCM(speedgrade=-2) self.comb += pll.reset.eq(~platform.request("cpu_reset_n")) pll.register_clkin(platform.request("clk200"), 200e6) @@ -87,8 +84,6 @@ class EthernetSoC(BaseSoC): self.add_csr("ethmac") self.add_interrupt("ethmac") - self.ethphy.crg.cd_eth_rx.clk.attr.add("keep") - self.ethphy.crg.cd_eth_tx.clk.attr.add("keep") self.platform.add_period_constraint(self.ethphy.crg.cd_eth_rx.clk, 1e9/125e6) self.platform.add_period_constraint(self.ethphy.crg.cd_eth_tx.clk, 1e9/125e6) self.platform.add_false_path_constraints( diff --git a/litex/boards/targets/kc705.py b/litex/boards/targets/kc705.py index 07d6856ff..871607210 100755 --- a/litex/boards/targets/kc705.py +++ b/litex/boards/targets/kc705.py @@ -31,9 +31,6 @@ class _CRG(Module): # # # - self.cd_sys.clk.attr.add("keep") - self.cd_sys4x.clk.attr.add("keep") - self.submodules.pll = pll = S7MMCM(speedgrade=-2) self.comb += pll.reset.eq(platform.request("cpu_reset")) pll.register_clkin(platform.request("clk200"), 200e6) @@ -91,8 +88,6 @@ class EthernetSoC(BaseSoC): self.add_csr("ethmac") self.add_interrupt("ethmac") - self.ethphy.crg.cd_eth_rx.clk.attr.add("keep") - self.ethphy.crg.cd_eth_tx.clk.attr.add("keep") self.platform.add_period_constraint(self.ethphy.crg.cd_eth_rx.clk, 1e9/125e6) self.platform.add_period_constraint(self.ethphy.crg.cd_eth_tx.clk, 1e9/125e6) self.platform.add_false_path_constraints( diff --git a/litex/boards/targets/kcu105.py b/litex/boards/targets/kcu105.py index d7d2fbda0..1243454fa 100755 --- a/litex/boards/targets/kcu105.py +++ b/litex/boards/targets/kcu105.py @@ -30,9 +30,6 @@ class _CRG(Module): # # # - self.cd_sys.clk.attr.add("keep") - self.cd_sys4x.clk.attr.add("keep") - self.submodules.pll = pll = USMMCM(speedgrade=-2) self.comb += pll.reset.eq(platform.request("cpu_reset")) self.clock_domains.cd_pll4x = ClockDomain(reset_less=True) @@ -127,8 +124,6 @@ class EthernetSoC(BaseSoC): self.add_csr("ethmac") self.add_interrupt("ethmac") - self.ethphy.cd_eth_rx.clk.attr.add("keep") - self.ethphy.cd_eth_tx.clk.attr.add("keep") self.platform.add_period_constraint(self.ethphy.cd_eth_rx.clk, 1e9/125e6) self.platform.add_period_constraint(self.ethphy.cd_eth_tx.clk, 1e9/125e6) self.platform.add_false_path_constraints( diff --git a/litex/boards/targets/minispartan6.py b/litex/boards/targets/minispartan6.py index 8c7230ec1..04f71c592 100755 --- a/litex/boards/targets/minispartan6.py +++ b/litex/boards/targets/minispartan6.py @@ -29,9 +29,6 @@ class _CRG(Module): # # # - self.cd_sys.clk.attr.add("keep") - self.cd_sys_ps.clk.attr.add("keep") - self.submodules.pll = pll = S6PLL(speedgrade=-1) pll.register_clkin(platform.request("clk32"), 32e6) pll.create_clkout(self.cd_sys, clk_freq) diff --git a/litex/boards/targets/netv2.py b/litex/boards/targets/netv2.py index bf5428303..7fecb76ab 100755 --- a/litex/boards/targets/netv2.py +++ b/litex/boards/targets/netv2.py @@ -32,10 +32,6 @@ class _CRG(Module): # # # - self.cd_sys.clk.attr.add("keep") - self.cd_sys4x.clk.attr.add("keep") - self.cd_sys4x_dqs.clk.attr.add("keep") - self.submodules.pll = pll = S7PLL(speedgrade=-1) pll.register_clkin(platform.request("clk50"), 50e6) pll.create_clkout(self.cd_sys, sys_clk_freq) @@ -95,8 +91,6 @@ class EthernetSoC(BaseSoC): self.add_csr("ethmac") self.add_interrupt("ethmac") - self.ethphy.crg.cd_eth_rx.clk.attr.add("keep") - self.ethphy.crg.cd_eth_tx.clk.attr.add("keep") self.platform.add_period_constraint(self.ethphy.crg.cd_eth_rx.clk, 1e9/12.5e6) self.platform.add_period_constraint(self.ethphy.crg.cd_eth_tx.clk, 1e9/12.5e6) self.platform.add_false_path_constraints( diff --git a/litex/boards/targets/nexys4ddr.py b/litex/boards/targets/nexys4ddr.py index be2e68931..e19c6f3a4 100755 --- a/litex/boards/targets/nexys4ddr.py +++ b/litex/boards/targets/nexys4ddr.py @@ -31,10 +31,6 @@ class _CRG(Module): # # # - self.cd_sys.clk.attr.add("keep") - self.cd_sys2x.clk.attr.add("keep") - self.cd_sys2x_dqs.clk.attr.add("keep") - self.submodules.pll = pll = S7MMCM(speedgrade=-1) self.comb += pll.reset.eq(~platform.request("cpu_reset")) pll.register_clkin(platform.request("clk100"), 100e6) @@ -94,8 +90,6 @@ class EthernetSoC(BaseSoC): self.add_csr("ethmac") self.add_interrupt("ethmac") - self.ethphy.crg.cd_eth_rx.clk.attr.add("keep") - self.ethphy.crg.cd_eth_tx.clk.attr.add("keep") self.platform.add_period_constraint(self.ethphy.crg.cd_eth_rx.clk, 1e9/12.5e6) self.platform.add_period_constraint(self.ethphy.crg.cd_eth_tx.clk, 1e9/12.5e6) self.platform.add_false_path_constraints( diff --git a/litex/boards/targets/nexys_video.py b/litex/boards/targets/nexys_video.py index 666a4724f..fa423ac62 100755 --- a/litex/boards/targets/nexys_video.py +++ b/litex/boards/targets/nexys_video.py @@ -31,10 +31,6 @@ class _CRG(Module): # # # - self.cd_sys.clk.attr.add("keep") - self.cd_sys4x.clk.attr.add("keep") - self.cd_sys4x_dqs.clk.attr.add("keep") - self.submodules.pll = pll = S7MMCM(speedgrade=-1) self.comb += pll.reset.eq(~platform.request("cpu_reset")) pll.register_clkin(platform.request("clk100"), 100e6) @@ -94,8 +90,6 @@ class EthernetSoC(BaseSoC): self.add_csr("ethmac") self.add_interrupt("ethmac") - self.ethphy.crg.cd_eth_rx.clk.attr.add("keep") - self.ethphy.crg.cd_eth_tx.clk.attr.add("keep") self.platform.add_period_constraint(self.ethphy.crg.cd_eth_rx.clk, 1e9/125e6) self.platform.add_period_constraint(self.ethphy.crg.cd_eth_tx.clk, 1e9/125e6) self.platform.add_false_path_constraints( diff --git a/litex/boards/targets/ulx3s.py b/litex/boards/targets/ulx3s.py index f14a7aae5..94994a77f 100755 --- a/litex/boards/targets/ulx3s.py +++ b/litex/boards/targets/ulx3s.py @@ -27,9 +27,6 @@ class _CRG(Module): # # # - self.cd_sys.clk.attr.add("keep") - self.cd_sys_ps.clk.attr.add("keep") - # clk / rst clk25 = platform.request("clk25") rst = platform.request("rst") diff --git a/litex/boards/targets/versa_ecp5.py b/litex/boards/targets/versa_ecp5.py index 3843b4544..81ad572b0 100755 --- a/litex/boards/targets/versa_ecp5.py +++ b/litex/boards/targets/versa_ecp5.py @@ -35,12 +35,6 @@ class _CRG(Module): # # # - self.cd_init.clk.attr.add("keep") - self.cd_por.clk.attr.add("keep") - self.cd_sys.clk.attr.add("keep") - self.cd_sys2x.clk.attr.add("keep") - self.cd_sys2x_i.clk.attr.add("keep") - self.stop = Signal() # clk / rst @@ -124,8 +118,6 @@ class EthernetSoC(BaseSoC): self.add_csr("ethmac") self.add_interrupt("ethmac") - self.ethphy.crg.cd_eth_rx.clk.attr.add("keep") - self.ethphy.crg.cd_eth_tx.clk.attr.add("keep") self.platform.add_period_constraint(self.ethphy.crg.cd_eth_rx.clk, 1e9/125e6) self.platform.add_period_constraint(self.ethphy.crg.cd_eth_tx.clk, 1e9/125e6)