From 30a7a1cf160f9e003e4511673201117075c8a657 Mon Sep 17 00:00:00 2001 From: Christian Klarhorst Date: Tue, 5 Jul 2022 16:12:41 +0200 Subject: [PATCH] build/xilinx/ise: Fix Yosys flow --- litex/build/xilinx/ise.py | 9 ++++----- 1 file changed, 4 insertions(+), 5 deletions(-) diff --git a/litex/build/xilinx/ise.py b/litex/build/xilinx/ise.py index 101d355db..47b01f824 100755 --- a/litex/build/xilinx/ise.py +++ b/litex/build/xilinx/ise.py @@ -44,13 +44,12 @@ class XilinxISEToolchain(GenericToolchain): self.bitgen_opt = "-g Binary:Yes -w" self.ise_commands = "" self.mode = "xst" - self.isemode = "xst" + self._isemode = "xst" def build(self, platform, fragment, mode = "xst", **kwargs): - - self._mode = mode + self.mode = mode self._isemode = mode if mode in ["xst", "cpld"] else "edif" return GenericToolchain.build(self, platform, fragment, **kwargs) @@ -118,11 +117,11 @@ class XilinxISEToolchain(GenericToolchain): # Yosys Run ---------------------------------------------------------------------------------------- - def _run_yosys(build_name): + def _run_yosys(self): device = self.platform.device ys_contents = "" incflags = "" - for path in platform.verilog_include_paths: + for path in self.platform.verilog_include_paths: incflags += " -I" + path for filename, language, library, *copy in self.platform.sources: ys_contents += "read_{}{} {}\n".format(language, incflags, filename)