diff --git a/misoclib/mem/sdram/core/__init__.py b/misoclib/mem/sdram/core/__init__.py index ca1ec1e66..e8181ad5f 100644 --- a/misoclib/mem/sdram/core/__init__.py +++ b/misoclib/mem/sdram/core/__init__.py @@ -1,5 +1,3 @@ -from collections import namedtuple - from migen.fhdl.std import * from migen.genlib.record import * from migen.bank.description import * @@ -8,8 +6,6 @@ from misoclib.mem.sdram.phy import dfii from misoclib.mem.sdram.core import minicon, lasmicon from misoclib.mem.sdram.core import lasmixbar -ControllerSettings = namedtuple("ControllerSettings", "type req_queue_size read_time write_time") - class SDRAMCore(Module, AutoCSR): def __init__(self, phy, geom_settings, timing_settings, controller_settings, **kwargs): # DFI @@ -18,7 +14,7 @@ class SDRAMCore(Module, AutoCSR): self.comb += Record.connect(self.dfii.master, phy.dfi) # LASMICON - if controller_settings.type == "lasmicon": + if isinstance(controller_settings, lasmicon.LASMIconSettings): self.submodules.controller = controller = lasmicon.LASMIcon(phy.settings, geom_settings, timing_settings, controller_settings, **kwargs) self.comb += Record.connect(controller.dfi, self.dfii.slave) @@ -26,8 +22,8 @@ class SDRAMCore(Module, AutoCSR): self.submodules.crossbar = crossbar = lasmixbar.LASMIxbar([controller.lasmic], controller.nrowbits) # MINICON - elif controller_settings.type == "minicon": + elif isinstance(controller_settings, minicon.MiniconSettings): self.submodules.controller = controller = minicon.Minicon(phy.settings, geom_settings, timing_settings) self.comb += Record.connect(controller.dfi, self.dfii.slave) else: - raise ValueError("Unsupported SDRAM controller type: {}".format(controller_settings.type)) + raise ValueError("Unsupported SDRAM controller type") diff --git a/misoclib/mem/sdram/core/lasmicon/__init__.py b/misoclib/mem/sdram/core/lasmicon/__init__.py index 5d213dd1d..e4502668d 100644 --- a/misoclib/mem/sdram/core/lasmicon/__init__.py +++ b/misoclib/mem/sdram/core/lasmicon/__init__.py @@ -6,6 +6,20 @@ from misoclib.mem.sdram.core.lasmicon.refresher import * from misoclib.mem.sdram.core.lasmicon.bankmachine import * from misoclib.mem.sdram.core.lasmicon.multiplexer import * +class LASMIconSettings: + def __init__(self, req_queue_size=8, + read_time=32, write_time=16, + with_l2=True, l2_size=8192, + with_bandwidth=False, + with_memtest=False): + self.req_queue_size = req_queue_size + self.read_time = read_time + self.write_time = write_time + self.with_l2 = with_l2 + self.l2_size = l2_size + self.with_bandwidth = with_bandwidth + self.with_memtest = with_memtest + class LASMIcon(Module): def __init__(self, phy_settings, geom_settings, timing_settings, controller_settings, **kwargs): if phy_settings.memtype in ["SDR"]: diff --git a/misoclib/mem/sdram/core/minicon/__init__.py b/misoclib/mem/sdram/core/minicon/__init__.py index 19a76373e..f26f052d2 100644 --- a/misoclib/mem/sdram/core/minicon/__init__.py +++ b/misoclib/mem/sdram/core/minicon/__init__.py @@ -34,6 +34,10 @@ class _AddressSlicer: else: return Cat(Replicate(0, self.address_align), address[:split]) +class MiniconSettings: + def __init__(self): + pass + class Minicon(Module): def __init__(self, phy_settings, geom_settings, timing_settings): if phy_settings.memtype in ["SDR"]: diff --git a/misoclib/soc/sdram.py b/misoclib/soc/sdram.py index e1409a3be..275763816 100644 --- a/misoclib/soc/sdram.py +++ b/misoclib/soc/sdram.py @@ -2,7 +2,9 @@ from migen.fhdl.std import * from migen.bus import wishbone, csr from migen.genlib.record import * -from misoclib.mem.sdram.core import ControllerSettings, SDRAMCore +from misoclib.mem.sdram.core import SDRAMCore +from misoclib.mem.sdram.core.lasmicon import LASMIconSettings +from misoclib.mem.sdram.core.minicon import MiniconSettings from misoclib.mem.sdram.frontend import memtest, wishbone2lasmi from misoclib.soc import SoC, mem_decoder @@ -15,66 +17,51 @@ class SDRAMSoC(SoC): } csr_map.update(SoC.csr_map) - def __init__(self, platform, clk_freq, - sdram_controller_type="lasmicon", sdram_controller_req_queue_size=8, - sdram_controller_read_time=32, sdram_controller_write_time=16, - with_l2=True, l2_size=8192, - with_bandwidth=False, # specific to LASMICON, - with_memtest=False, # ignored for MINICON + def __init__(self, platform, clk_freq, sdram_controller_settings, **kwargs): SoC.__init__(self, platform, clk_freq, **kwargs) - self.sdram_controller_type = sdram_controller_type - self.sdram_controller_settings = ControllerSettings( - type=sdram_controller_type, - # Below parameters are only used by LASMIcon - req_queue_size=sdram_controller_req_queue_size, - read_time=sdram_controller_read_time, - write_time=sdram_controller_write_time - ) - - self.with_l2 = with_l2 - self.l2_size = l2_size - - self.with_memtest = with_memtest - self.with_bandwidth = with_bandwidth or with_memtest - + if isinstance(sdram_controller_settings, str): + self.sdram_controller_settings = eval(sdram_controller_settings) + else: + self.sdram_controller_settings = sdram_controller_settings self._sdram_phy_registered = False def register_sdram_phy(self, phy, geom_settings, timing_settings): if self._sdram_phy_registered: raise FinalizeError self._sdram_phy_registered = True - if self.sdram_controller_type == "minicon" and phy.settings.memtype != "SDR": + if isinstance(self.sdram_controller_settings, MiniconSettings) and phy.settings.memtype != "SDR": raise NotImplementedError("Minicon only supports SDR memtype for now (" + phy.settings.memtype + ")") # Core self.submodules.sdram = SDRAMCore(phy, geom_settings, timing_settings, self.sdram_controller_settings) # LASMICON frontend - if self.sdram_controller_type == "lasmicon": - if self.with_bandwidth: + if isinstance(self.sdram_controller_settings, LASMIconSettings): + if self.sdram_controller_settings.with_bandwidth: self.sdram.controller.multiplexer.add_bandwidth() - if self.with_memtest: + if self.sdram_controller_settings.with_memtest: self.submodules.memtest_w = memtest.MemtestWriter(self.sdram.crossbar.get_master()) self.submodules.memtest_r = memtest.MemtestReader(self.sdram.crossbar.get_master()) - if self.with_l2: + if self.sdram_controller_settings.with_l2: + l2_size = self.sdram_controller_settings.l2_size # XXX Vivado 2014.X workaround, Vivado is not able to map correctly our L2 cache. # Issue is reported to Xilinx and should be fixed in next releases (2015.1?). # Remove this workaround when fixed by Xilinx. from mibuild.xilinx.vivado import XilinxVivadoToolchain if isinstance(self.platform.toolchain, XilinxVivadoToolchain): from migen.fhdl.simplify import FullMemoryWE - self.submodules.wishbone2lasmi = FullMemoryWE(wishbone2lasmi.WB2LASMI(self.l2_size//4, self.sdram.crossbar.get_master())) + self.submodules.wishbone2lasmi = FullMemoryWE(wishbone2lasmi.WB2LASMI(l2_size//4, self.sdram.crossbar.get_master())) else: - self.submodules.wishbone2lasmi = wishbone2lasmi.WB2LASMI(self.l2_size//4, self.sdram.crossbar.get_master()) + self.submodules.wishbone2lasmi = wishbone2lasmi.WB2LASMI(l2_size//4, self.sdram.crossbar.get_master()) lasmic = self.sdram.controller.lasmic main_ram_size = 2**lasmic.aw*lasmic.dw*lasmic.nbanks//8 self.register_mem("main_ram", self.mem_map["main_ram"], self.wishbone2lasmi.wishbone, main_ram_size) # MINICON frontend - elif self.sdram_controller_type == "minicon": + elif isinstance(self.sdram_controller_settings, MiniconSettings): sdram_width = flen(self.sdram.controller.bus.dat_r) main_ram_size = 2**(geom_settings.bank_a+geom_settings.row_a+geom_settings.col_a)*sdram_width//8 diff --git a/targets/de0nano.py b/targets/de0nano.py index 469bc7350..a1fd027d5 100644 --- a/targets/de0nano.py +++ b/targets/de0nano.py @@ -5,6 +5,7 @@ from misoclib.cpu.peripherals import gpio from misoclib.mem import sdram from misoclib.mem.sdram.module import IS42S16160 from misoclib.mem.sdram.phy import gensdrphy +from misoclib.mem.sdram.core.lasmicon import LASMIconSettings from misoclib.com import uart from misoclib.soc.sdram import SDRAMSoC @@ -82,10 +83,11 @@ class _CRG(Module): class BaseSoC(SDRAMSoC): default_platform = "de0nano" - def __init__(self, platform, **kwargs): + def __init__(self, platform, sdram_controller_settings=LASMIconSettings(), **kwargs): SDRAMSoC.__init__(self, platform, clk_freq=100*1000000, with_integrated_rom=True, + sdram_controller_settings=sdram_controller_settings, **kwargs) self.submodules.crg = _CRG(platform) diff --git a/targets/kc705.py b/targets/kc705.py index e7fd9a90e..a26bb712c 100644 --- a/targets/kc705.py +++ b/targets/kc705.py @@ -4,6 +4,7 @@ from migen.genlib.resetsync import AsyncResetSynchronizer from misoclib.mem import sdram from misoclib.mem.sdram.module import MT8JTF12864 from misoclib.mem.sdram.phy import k7ddrphy +from misoclib.mem.sdram.core.lasmicon import LASMIconSettings from misoclib.mem.flash import spiflash from misoclib.soc import mem_decoder from misoclib.soc.sdram import SDRAMSoC @@ -76,9 +77,10 @@ class BaseSoC(SDRAMSoC): } csr_map.update(SDRAMSoC.csr_map) - def __init__(self, platform, **kwargs): + def __init__(self, platform, sdram_controller_settings=LASMIconSettings(), **kwargs): SDRAMSoC.__init__(self, platform, clk_freq=125*1000000, cpu_reset_address=0xaf0000, + sdram_controller_settings=sdram_controller_settings, **kwargs) self.submodules.crg = _CRG(platform) diff --git a/targets/mlabs_video.py b/targets/mlabs_video.py index 3551cfc72..a193e7635 100644 --- a/targets/mlabs_video.py +++ b/targets/mlabs_video.py @@ -8,6 +8,7 @@ from misoclib.others import mxcrg from misoclib.mem import sdram from misoclib.mem.sdram.module import MT46V32M16 from misoclib.mem.sdram.phy import s6ddrphy +from misoclib.mem.sdram.core.lasmicon import LASMIconSettings from misoclib.mem.flash import norflash16 from misoclib.cpu.peripherals import gpio from misoclib.video import framebuffer @@ -33,10 +34,11 @@ class _MXClockPads: class BaseSoC(SDRAMSoC): default_platform = "mixxeo" # also supports m1 - def __init__(self, platform, **kwargs): + def __init__(self, platform, sdram_controller_settings=LASMIconSettings(), **kwargs): SDRAMSoC.__init__(self, platform, clk_freq=(83 + Fraction(1, 3))*1000000, cpu_reset_address=0x00180000, + sdram_controller_settings=sdram_controller_settings, **kwargs) self.submodules.crg = mxcrg.MXCRG(_MXClockPads(platform), self.clk_freq) diff --git a/targets/pipistrello.py b/targets/pipistrello.py index 737d9f3c7..e3663e077 100644 --- a/targets/pipistrello.py +++ b/targets/pipistrello.py @@ -6,6 +6,7 @@ from migen.genlib.resetsync import AsyncResetSynchronizer from misoclib.mem import sdram from misoclib.mem.sdram.module import MT46H32M16 from misoclib.mem.sdram.phy import s6ddrphy +from misoclib.mem.sdram.core.lasmicon import LASMIconSettings from misoclib.mem.flash import spiflash from misoclib.soc.sdram import SDRAMSoC @@ -89,12 +90,14 @@ class BaseSoC(SDRAMSoC): } csr_map.update(SDRAMSoC.csr_map) - def __init__(self, platform, **kwargs): + def __init__(self, platform, sdram_controller_settings=LASMIconSettings(), **kwargs): clk_freq = 75*1000*1000 if not kwargs.get("with_integrated_rom"): kwargs["rom_size"] = 0x1000000 # 128 Mb SDRAMSoC.__init__(self, platform, clk_freq, - cpu_reset_address=0x170000, **kwargs) # 1.5 MB + cpu_reset_address=0x170000, # 1.5 MB + sdram_controller_settings=sdram_controller_settings, + **kwargs) self.submodules.crg = _CRG(platform, clk_freq) diff --git a/targets/ppro.py b/targets/ppro.py index d12f89bb6..f52e3a785 100644 --- a/targets/ppro.py +++ b/targets/ppro.py @@ -6,6 +6,7 @@ from migen.genlib.resetsync import AsyncResetSynchronizer from misoclib.mem import sdram from misoclib.mem.sdram.module import MT48LC4M16 from misoclib.mem.sdram.phy import gensdrphy +from misoclib.mem.sdram.core.lasmicon import LASMIconSettings from misoclib.mem.flash import spiflash from misoclib.soc.sdram import SDRAMSoC @@ -67,10 +68,12 @@ class BaseSoC(SDRAMSoC): } csr_map.update(SDRAMSoC.csr_map) - def __init__(self, platform, **kwargs): + def __init__(self, platform, sdram_controller_settings=LASMIconSettings(), **kwargs): clk_freq = 80*1000*1000 SDRAMSoC.__init__(self, platform, clk_freq, - cpu_reset_address=0x60000, **kwargs) + cpu_reset_address=0x60000, + sdram_controller_settings=sdram_controller_settings, + **kwargs) self.submodules.crg = _CRG(platform, clk_freq)