diff --git a/migen/corelogic/roundrobin.py b/migen/corelogic/roundrobin.py
index 4b7546554..298c7d166 100644
--- a/migen/corelogic/roundrobin.py
+++ b/migen/corelogic/roundrobin.py
@@ -5,7 +5,7 @@ from migen.fhdl.structure import *
 class RoundRobin:
 	def __init__(self, n, switch_policy=SP_WITHDRAW):
 		self.n = n
-		self.request = Signal(max=self.n)
+		self.request = Signal(nbits=self.n)
 		self.grant = Signal(max=self.n)
 		self.switch_policy = switch_policy
 		if self.switch_policy == SP_CE: